RU2811404C1 - Programmable logic device - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention can be used to calculate logical functions in programmable logic integrated circuits (FPLIC). The result is achieved by introducing a subgroup of k-1 additional tuning inverters for each of the 2ⁿ tuning inverters of the group of 2ⁿ tuning inverters, a subgroup of k-1 additional tuning inputs for each input from the group of tuning inputs, k additional variable inputs, 2ⁿ additional groups of transmitting transistors k transistors per group, k additional input variable inverters and 2ⁿ additional outputs.

EFFECT: reducing the time delay when implementing logical functions of a large number of variables in the FPLIC, without increasing the complexity in the number of transistors.

1 cl, 4 tbl, 3 dwg

Description

The invention relates to computer technology and can be used to calculate logical functions in programmable logic integrated circuits (FPGAs).

A programmable logic device is known, containing the first, second and third groups of D-flip-flops with a number of m·2 ⁿ (n is the number of input variables, m is the number of output functions), a third group of D-flip-flops with a number of 2(n-1)m, a group m(n-1) AND elements, a counter, a group of m 2 ⁿ AND elements with three output states, a decoder, a group of m(n-1) OR elements, a second group of m 2 ⁿ AND elements with three output states and m function calculation blocks, each function calculation block contains a group of 4 2 ⁿ AND elements with three output states, two D-flip-flops, a T-flip-flop, an RS pulse fixation flip-flop, five OR elements, three AND elements, four inverters, n groups of elements 2·2 NAND-OR (each i-th group includes 2 ^n-1 elements, i=1,n), a delay element, an additional group of AND elements with three output states (RF patent No. 2146840 dated 20.03 .2000, class G11С 17/00, G06F7/00).

A disadvantage of the known device is the high hardware costs, expressed in the number of transistors, for implementing a logical function in programmable logic integrated circuits (FPGAs).

The closest device of the same purpose to the claimed invention in terms of the set of characteristics is a programmable logic device containing a group of n inverters, n groups of transmitting transistors (n is the number of input variables) according to transistors in a group, group inverter settings, output inverter, n variable inputs, group settings inputs, device output,

and the gate of each odd transistor of the i-th group of transmitting transistors connected to the output of the i-th inverter of a group of n inverters, the gate of each even transistor of the i-th group of transmitting transistors is connected to the i-th input of the inputs of n variables, sources transistors of the n-th group are connected to the outputs of the inverters of the group settings inverters whose inputs are a group settings inputs, the drains of the even and odd transistors of the n-th group are combined and connected to the sources of the corresponding transistors of the n-1st group, the drains of which are combined and connected to the sources of the corresponding transistors of the n-2nd group, the drains of the last two transistors of the 1st group are combined and connected to the input of the output inverter, the output of which is the output of the device (Look up table implementation of fast carry for adders and counters: US 005274581A, 12/28/1993; Stroganov A. , Tsybin S. Programmable switching in FPGA: an inside view// Components and Technologies. - 2010. - No. 11. P. 56-62, Fig. 9, [Electronic resource]. - URL: http://www.kit- e.ru/articles/plis/2010_11_56.php 02/20/23).

The disadvantage of the known device, adopted as a prototype, is the high latency when implementing logical functions of a large number of arguments.

This is due to the following circumstances. The prototype's technical means are focused on implementing a logical function in perfect disjunctive normal form (PDNF) with binary coding of a set of n variables, which leads to the fact that the chain of transistors in the corresponding tree contains at least n transistors. In the case of n > 3, it is necessary to use signal level restorers, which further increases the propagation delay from the configuration memory, in which the values of the logical function on this particular set are recorded, to the output of the function value.

When using unitary encoding of a set of n variables of a logical function, there is only one transistor in the corresponding tree, but the number of communication lines and hardware costs in the number of transistors for the implementation of input inverters increase exponentially. One of the possible ways to overcome this contradiction may be a combined implementation of logical functions, using both binary and unitary coding.

Features of the prototype that coincide with the essential features of the claimed invention - contains a group of n inverters of input variables, n groups of transmitting transistors (n is the number of input variables) according to transistors in the i-th group, group inverter settings, inverter, n variable inputs, group settings inputs, device output; the gate of each odd transistor of the i-th group of transmitting transistors is connected to the output of the i-th inverter of the group of n inverters, the gate of each even transistor of the i-th group of transmitting transistors is connected to the i-th input of the n variable inputs; inverter inputs from the group inverter settings are a group settings inputs; the drains of the corresponding even and odd transistors of the n-th group 2.n are combined and connected to the sources of the corresponding transistors of the 2.n-1st group, the drains of which are combined and connected to the sources of the corresponding transistors of the n-2nd group 2.n-2; The drains of the last two transistors of the 1st group are combined and connected to the input of the inverter, the output of which is the output of the device.

The objective of the invention is to reduce the time delay when implementing logical functions of a large number of variables in the FPGA, without increasing the complexity in the number of transistors.

The problem was solved due to the fact that in the claimed device containing a group of n inverters of input variables, n groups of transmitting transistors (n is the number of input variables) transistors in the i-th group, group inverter settings, inverter, n variable inputs, group settings inputs, device output,

and

the gate of each odd transistor of the i-th group of transmitting transistors is connected to the output of the i-th inverter of the group of n inverters, the gate of each even transistor of the i-th group of transmitting transistors is connected to the i-th input of the inputs of n variables, the inputs of inverters from the group inverter settings are a group settings inputs, the drains of the corresponding even and odd transistors of the n-th group 2.n are combined and connected to the sources of the corresponding transistors of the 2.n-1st group, the drains of which are combined and connected to the sources of the corresponding transistors of the n-2th group 2.n-2 , the drains of the last two transistors of the 1st group are combined and connected to the input of the inverter, the output of which is the output of the device, according to the invention, additional subgroups k-1 of additional inverters are introduced for each of the inverters. group settings inverter settings, subgroup k-1 additional settings inputs for each input from the group setting inputs, k additional variable inputs, additional groups of transmitting transistors, k transistors per group, k additional input variable inverters, additional outputs, and k additional variable inputs are connected to the inputs of the corresponding k additional input variable inverters, the outputs of which are connected to the gates of the corresponding i-th (i=1...k) k-th transistors in each of additional groups of transmitting transistors, k transistors per group, the sources of which are connected to the outputs of the corresponding i-th (i=1...k) inverters of the group tuning inverters and subgroups k-1 additional tuning inverters for each of the tuning inverters, k inverters in a group, and drains of transistors in each group from additional groups of transmitting transistors, k transistors in the group are combined and connected to the sources of the corresponding transistors in the n-th group of transmitting transistors (n is the number of input variables) by transistors in the i-th group, and are also outputs from additional outputs.

Features of the proposed technical solution that are different from the prototype - subgroups k-1 of additional inverters settings for each of inverter group settings inverter settings, subgroup k-1 additional settings inputs for each input from the group setting inputs, k additional variable inputs, additional groups of transmitting transistors, k transistors per group, k additional input variable inverters, additional outputs, k additional variable inputs are connected to the inputs of the corresponding k additional input variable inverters, the outputs of which are connected to the gates of the corresponding i-th (i=1...k) k-th transistors in each of additional groups of transmitting transistors, k transistors per group, the sources of which are connected to the outputs of the corresponding i-th (i=1...k) inverters of the group tuning inverters and subgroups k-1 additional tuning inverters for each of the tuning inverters, k inverters in a group, and drains of transistors in each group from additional groups of transmitting transistors, k transistors in the group are combined and connected to the sources of the corresponding transistors in the n-th group of transmitting transistors (n is the number of input variables) by transistors in the i-th group, and are also outputs from additional outputs.

Distinctive features in combination with known ones make it possible to reduce the time delay by combining unitary and binary coding of variables by introducing two modes: a mixed coding mode, a unitary coding only mode.

Introduction of subgroup k-1 additional inverter settings for each of inverter group settings tuning inverters provides the supply of tuning constants to additional groups of transmitting transistors with k transistors in a group when implementing both the mixed coding mode and the unitary coding only mode.

Introduction of a subgroup of k-1 additional configuration inputs for each input from the group tuning inputs provides reception of tuning constants for additional groups of transmitting transistors with k transistors in a group when implementing both the mixed coding mode and the unitary coding only mode.

The introduction of k additional variable inputs ensures the reception of input variables when implementing both the mixed coding mode and the unitary coding only mode.

Introduction additional groups of transmitting transistors, k transistors in a group, ensure the calculation of logical functions specified by the current setting when implementing both the mixed coding mode and the unitary coding only mode.

The introduction of k additional inverters of input variables ensures obtaining inverse values of input variables when implementing both the mixed coding mode and the unitary coding only mode.

Introduction additional outputs allows you to output the values of logical functions to external devices in unitary coding mode only.

Changing the connections in comparison with the known device ensures a reduction in the time delay for the passage of the value of a logical function on a given set of variables specified by the tuning signal, due to the implementation of a combination of unitary and binary coding of variables by introducing two modes: a mixed coding mode, a unitary coding only mode.

In fig. 1 - shows an electrical functional diagram of a programmable logic device.

In fig. 2 - shows a graph comparing the complexity of the proposed device relative to the prototype.

In fig. 3 - shows a graph comparing the complexity of the proposed device relative to the prototype and the version with completely unitary coding.

The programmable logic device contains

group of n inverters of input variables 1, n groups of transmitting transistors 2 (n is the number of input variables) by transistors in the i-th group, group inverter settings 3, inverter 4, n variable inputs 5, group setting inputs 6, device output 7.

The gate of each odd transistor of the i-th group of transmitting transistors 2 connected to the output of the i-th inverter of group n inverters 1, the gate of each even transistor of the i-th group of transmitting transistors 2 is connected to the i-th input of n variable inputs 5.

The drains of the corresponding even and odd transistors of the n-th group 2.n are combined and connected to the sources of the corresponding transistors of the 2.n-1st group, the drains of which are combined and connected to the sources of the corresponding transistors of the n-2nd group 2.n-2. The drains of the last two transistors of the 1st group 2.1.1 and 2.1.2 are combined and connected to the input of inverter 4, the output of which is output 7 of the device.

Additionally, subgroups of k-1 additional inverters have been introduced for each of the settings inverter settings 3 groups inverter settings, subgroup k-1 additional settings inputs for each input from the group setting inputs 6, k additional variable inputs 8.1,8.2,…8.k, additional groups of transmitting transistors, k transistors in group 9.1,9.2,…9.k, k additional inverters of input variables 10.1,10.2,…10.k, additional outputs …11.1.

k additional inputs of variables 8.1,8.2,…8.k are connected to the inputs of the corresponding k additional inverters of input variables 10.1,10.2,…10.k, the outputs of which are connected to the gates of the corresponding k transistors in each of additional groups of transmitting transistors 9.1,9.2,…9.k each with k transistors in the group, the sources of which are connected to the outputs of the corresponding inverters of the group inverters are configured with 3 k inverters in a group, and transistor drains in each group of additional groups of transmitting transistors 9.1,9.2,…9.k by k transistors in the group are combined and connected to the sources of the corresponding transistors in the n-th group of transmitting transistors 2 (n is the number of input variables) by transistors in the i-th group, and are also outputs from additional outputs …11.1.

The programmable logic device works as follows:

1.Programming stage. In this case, per group setting inputs 6, consisting of k subgroups, setting signals for one or k (depending on the operating mode) logical functions are set to no more than variables, where the nearest larger natural number.

Example

Let, for example, it is necessary to implement a logical function depending on four variables y ₂ y ₁ x ₂ x ₁ and specified by the numbers of the constituents of unity:

y ₂ (t+1) _y1y2x2x1 = 4,5,6,7,12,13,14,15.

In this case, a unitary code is also supplied to the gates of the transistors of additional group 8 (one logical one, the rest are zeros, for example, for k = 4 code 0001).

In the prototype and in the proposed device operating in binary variable coding mode, the settings are described in Tables 1, 2:

table 2

Setting up inputs 6 in the proposed device operating in binary coding mode of variables k =4, n=4:

In the known device, the delay in the tree of transmitting transistors 2 is equal to four in the number of variables. The complexity is estimated by the expression

(1)

In the proposed device we take , we get the complexity

(2)

Thus, the complexity did not worsen, and the delay became half as much: 1+1=2. The configuration of inputs 6 in the proposed device operating in combined mode is presented in Table. 3.

6.1
y ₂ (t+1) 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 0 0 0 0 1 1 1 1 6.2
y ₂ (t+1) 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 0 0 0 0 1 1 1 1

With a completely unitary implementation, when , the delay is equal to one, the output signal is taken from one of the outputs 11, the complexity is estimated by the expression:

(3)

In expression (3), it is assumed that only two transistors 2.1.2 and 2.1.1 are left to maintain multi-mode operation. In this case, it becomes possible to implement not one, but two functions, for example, another function

y ₁ (t+1) _y1y2x2x1 =0,1,2,3,4,5,6,7,14,15.

The configuration of inputs 6 in the proposed device in unitary mode with the implementation of two functions is shown in Table 4.

Table 4

Setting up 6 inputs in the proposed device in unitary mode:

6.1
y ₂ (t+1) 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 6.2
y ₁ (t+1) 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.11 6.2.12 6.2.13 6.2.14 6.2.15 6.2.16 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1

2. Computation stage. At this stage, the inputs of n variables 5 and k variables 8 receive combined values of input variables, and the inputs of n variables 5 are in binary code, and the inputs of k variables 8 are in unitary code, when only one of the inputs is equal to one.

2.1. Binary mode calculations

In this mode, inputs 8 do not change (some specified code is set on them, for example, one at 8.1), inputs 5 change depending on the sets of variables. In this case, the corresponding value of the logical function, written at inputs 6 taking into account the settings of inputs 8, is supplied through the corresponding inverter of group 3, transistor of group 9 to the corresponding transistors of groups 2.n, 2.n-1,...2.1, activated by the values of variables 5, through inverters 1 so that at the output of inverter 4 and output 7 the value of the logical function is formed similarly to the prototype.

2.2. Computations in combined coding mode

In this mode, both inputs 8 and inputs 5 change. Therefore, unlike the first mode, the unitary code on inputs 8 additionally determines for each binary set of inputs 5 one of the inputs 6, activating the corresponding transistor of group 9. In this case, k transistors in k are activated there are 9 groups, but due to the transistors of groups 2, only one is selected in one of the groups. Further passage of the signal is similar to the first mode. This makes it possible to reduce the delay in the implementation of logical functions of a large number of variables without increasing the complexity in the number of transistors.

2.3. Computations in unitary coding mode

In this mode, only the inputs 8 change, which determine the value of the logical function (logical functions) recorded at the inputs 6. These values are supplied through the corresponding inverters 3, transistors 9 to the corresponding outputs 11. This ensures a minimum delay equal to the delay of one transistor 9 , as well as the implementation of systems of logical functions that depend on the same variables, encoded with unitary code 8.

Technical efficiency assessment

Let us evaluate the effectiveness of the proposed device. The complexity of the prototype in the number of transistors depending on the number of variables n is estimated by the expression:

(4)

Where - complexity of the n-level tree of transmitting transistors;

- complexity of setup;

2 - complexity of the output inverter.

When increasing the number of inputs to Where - the nearest larger natural number, we get:

(5)

The proposed device is evaluated by the formula:

(6)

Where - complexity of the n-level tree of transmitting transistors + complexity of the output inverter without taking into account the settings from expression (1);

- setup complexity increased by k times;

- complexity of additional transmitting transistors;

- complexity of additional inverters for additional k inputs.

At the same time, a completely unitary implementation is evaluated by the expression:

(7)

Where - complexity of setup;

- complexity of inverters entrances.

The corresponding graph for k=8 has the form shown in Fig. 2.

In this case, the delay of the prototype would be n+3, and in the proposed device n+1. At the same time, the complexity is less than that of the prototype. With completely unitary encoding, the delay is unity (one transistor), but the complexity is very high (Fig. 3).

The proposed device can operate in a completely unitary coding mode (with appropriate settings) using k additional inputs of variables 8.1,8.2,…8.k, while the delay is also unit, the system values of their k output functions from variables are output …11.1, while output 7 is not used.

The achievement of the technical result of the invention is confirmed by the above estimates.

Claims (1)

A programmable logic device containing a group of n input variable inverters, n groups of transmitting transistors (n is the number of input variables) transistors in the i-th group, group inverter settings, inverter, n variable inputs, group setting inputs, device output, and the gate of each odd transistor of the i-th group of transmitting transistors is connected to the output of the i-th inverter of the group of n inverters, the gate of each even transistor of the i-th group of transmitting transistors is connected to the i-th input of the inputs of n variables, inverter inputs from the group inverter settings are a group settings inputs, the drains of the corresponding even and odd transistors of the n-th group 2.n are combined and connected to the sources of the corresponding transistors of the 2.n-1st group, the drains of which are combined and connected to the sources of the corresponding transistors of the n-2nd group 2.n -2, the drains of the last two transistors of the 1st group are combined and connected to the input of the inverter, the output of which is the output of the device, characterized in that it additionally includes subgroups k-1 of additional inverters settings for each of the inverters group settings inverter settings, subgroup k-1 additional settings inputs for each input from the group setting inputs, k additional variable inputs, additional groups of transmitting transistors, k transistors per group, k additional input variable inverters, additional outputs, and k additional variable inputs are connected to the inputs of the corresponding k additional input variable inverters, the outputs of which are connected to the gates of the corresponding i-th (i=1...k) k-th transistors in each of additional groups of transmitting transistors, k transistors per group, the sources of which are connected to the outputs of the corresponding i-th (i=1...k) inverters of the group tuning inverters and subgroups k-1 additional tuning inverters for each of the tuning inverters, k inverters in a group, and drains of transistors in each group from additional groups of transmitting transistors, k transistors in the group are combined and connected to the sources of the corresponding transistors in the n-th group of transmitting transistors (n is the number of input variables) by transistors in the i-th group, and are also outputs from additional outputs.