JP6159240B2 - Binary arithmetic encoding device, binary arithmetic encoding method, and binary arithmetic encoding program - Google Patents

Description

  The present invention relates to a binary arithmetic encoding device, a binary arithmetic encoding method, and a binary arithmetic encoding program for speeding up binary arithmetic encoding processing.

  HEVC / H. The encoded image data after compression by H.265 has statistical properties. In the binary arithmetic coding process, CABAC (Context-based Adaptive Binary Arithmetic Coding), which is a kind of entropy coding, is used in order to further reduce the redundancy using this statistical property. The CABAC process is largely performed by three processes: a binary series process, a context modeling process, and a binary arithmetic coding process. Data such as motion vectors and transform coefficients encoded by the video encoding process is called a symbol, and is converted into a binary number sequence by a method determined according to the property of each symbol, and bin (binary number) from the symbol. Converted to a column. The occurrence probability model for the binary number is dynamically determined according to the state of the symbol in the vicinity of the processing target block (context modeling process), and the binary number is binary according to the occurrence probability model determined by the context modeling process. Arithmetic encoded.

  Among these processes, the binary arithmetic coding unit may change the occurrence probability of the context for each binary-sequenced value called bin, and use the changed occurrence probability at the next bin process. Yes. In addition, since variables such as a range value and a low value are updated for each bin, data dependency exists. Therefore, it is difficult to process a plurality of bins simultaneously by parallel processing or the like, and it is necessary to increase the operating frequency in order to increase the speed of binary arithmetic encoding processing. In addition to the limitations in increasing the operating frequency, application of increasing the operating frequency is limited because the power consumption of the system is increased by increasing the operating frequency.

  On the other hand, a method of performing CABAC processing in an algorithmic parallel manner has been proposed (see, for example, Patent Document 1). In this method, one screen is divided into several regions (slices), and CABAC processing is performed independently in each slice. Since the CABAC process is executed by initializing the internal state at the start of each slice process, the coding efficiency is reduced if each CABAC process is operated completely independently. Therefore, after the CABAC process of the first slice in the screen has progressed to some extent, the CABAC process of the next slice is started using the internal state as an initial value, so that the CABAC process is parallelized while maintaining the coding efficiency. I am letting.

JP 2012-134757 A

  However, in the method of Patent Document 1, it is necessary for the encoding device and the decoding device to support this function, the compression performance is poor when executed without slice division, and CABAC. When determining the encoding mode including the number of subsequent bits, the speed of the context unit is required, so the application of this method is also limited. For this reason, it is necessary to increase the speed of the binary arithmetic encoding process by realizing parallel processing for bins input to the binary arithmetic encoding unit without using parallel processing by slice division.

  The present invention has been made in view of such circumstances, and a binary arithmetic encoding device, a binary arithmetic encoding method, and a binary arithmetic encoding program capable of speeding up binary arithmetic encoding processing are provided. The purpose is to provide.

  The present invention provides a context update unit that calculates a state transition value of symbol occurrence probability state and MPS / LPS information from context information and symbols, a state update value of the symbol occurrence probability state, MPS / LPS information, and a range value. A range update processing unit that calculates a normalized shift amount and simultaneously updates a range value; a low value update that updates a low value from the renormalized shift amount, the MPS / LPS information, and the updated range value and low value And a bit stream generation unit that generates a bit stream using the updated row value, wherein the context update unit starts from the occurrence probability state of the first bin, the second bin When simultaneously determining the occurrence probability states of a plurality of bins, a plurality of bins are processed in parallel with reference to the occurrence probability state table. .

  In the present invention, the range update processing unit reads the value of the LPS section length table using the occurrence probability states of the first bin and the second bin, and uses a plurality of values from the read values using the range value. And the range value is updated and the renormalization shift amount is calculated.

  In the present invention, the low value update unit receives a plurality of the MPS / LPS information, the renormalization shift amount, and the updated range value, and performs cumulative addition of the low value and the renormalization shift amount, When the result of the cumulative addition exceeds a specified threshold, data is output to the bitstream generation unit and the result of the cumulative addition is reduced by the low value and the number of bits of the output data. It is characterized by.

  In the present invention, the bitstream generation unit holds temporarily received data to perform carry processing, and does not output when there is a possibility of carry, but adds only the received data amount When it is confirmed that no carry occurs, the carry data is processed and the stored data is output as a bit stream, and 1 or 0 is output depending on the result of the carry process until the received data amount becomes 1. Then, the data used for confirmation is temporarily stored again.

  The present invention provides a context update unit that calculates a state transition value of symbol occurrence probability state and MPS / LPS information from context information and symbols, a state update value of the symbol occurrence probability state, MPS / LPS information, and a range value. A range update processing unit that calculates a normalized shift amount and simultaneously updates a range value; a low value update that updates a low value from the renormalized shift amount, the MPS / LPS information, and the updated range value and low value And a binary arithmetic encoding method performed by a binary arithmetic encoding device including a bitstream generation unit that generates a bitstream using the updated row value, wherein the context update unit includes a first bin When the occurrence probability state of the second bin is simultaneously determined from the occurrence probability state, the plurality of bins are arranged in parallel by referring to the occurrence probability state table. And characterized in that the processing.

  The present invention is a binary arithmetic encoding program for causing a computer to function as the binary arithmetic encoding device.

  According to the present invention, it is possible to increase the speed of binary arithmetic coding processing by performing parallel processing on a plurality of bin sequences without performing parallelization at an algorithm level such as slice division.

It is a block diagram which shows the basic composition of one Embodiment of this invention. It is a flowchart which shows the processing operation of the context update part 1 shown in FIG. It is a flowchart which shows the processing operation of the range update part 2 shown in FIG. It is a flowchart which shows the processing operation of the row update part 3 shown in FIG. It is a block diagram which shows the structure of 2 parallel binary arithmetic code processing. It is a block diagram which shows the apparatus structure for speeding up binary arithmetic coding processing. It is a figure which shows the content of a state transition table. It is a figure which shows the structure of the state transition table content for 2 parallel processing. It is a flowchart which shows selection operation | movement of an update value. It is a block diagram which shows the structure of the context update part 21 shown in FIG. 6 which performs 2 parallel processes. It is a figure which shows the logic of a selection signal generator. It is a figure which shows the logic of a selection signal generator. It is a figure which shows the flow of 2 parallel context update processing. It is a block diagram which shows the structure of the range update part 22 shown in FIG. 6 which performs 2 parallel processes. It is a block diagram which shows the structure of the row update part 23 shown in FIG. 6 which performs 2 parallel processes. It is a figure which shows the process example of a row update value. It is a figure which shows the bit stream production | generation part 24 structure shown in FIG. It is a figure which shows the example of a bit stream production | generation process state machine.

  Hereinafter, a basic configuration of a binary arithmetic coding apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of a binary arithmetic encoding unit in the embodiment. The binary arithmetic encoding process is roughly divided into three processes: a context update process, a range value update process, and a low value update process. In the HEVC Test Model (HM), these processes are implemented in one processing loop, and each update process cannot be updated for the next bin unless three processes are completed.

  However, each update process can be operated independently by passing an appropriate variable between the update processes. This indicates that each update process can be processed in parallel by pipeline processing, which cannot be executed in parallel due to dependency. As shown in FIG. 1, the context update unit 1 depends on the input symbol and context. The range update unit 2 depends on the context, the range value, and information on whether the symbol output from the context update unit 1 is a dominant symbol (MPS) or a recessive symbol (LPS). The row updating unit 3 depends on the MPS or LPS information, the updated range value, and the bit shift amount indicating the normalization amount and the row value when renormalized.

  With this configuration, context update, range update, and row update can be pipelined. Also, only the context update is performed, the output is stored in the memory, the range value is updated continuously after the context update processing is completed, the output is also stored in the memory, the range value is updated, and the low value is updated. It is also possible to adopt a processing form in which the processes are performed continuously.

  Further, in HEVC, bypass processing is performed in which occurrence probabilities of 0 and 1 are fixed to 0.5 and a part of arithmetic code processing is omitted for bins whose occurrence probability is difficult to estimate. In this bypass process, only the update of the low value is performed. Therefore, by making each update process independent, it is possible to execute the encoding process without operating the context update unit 1 and the range update unit 2. Become. Moreover, since the low value update is performed when the renormalization is performed when the range value becomes small (less than 256) in the range update unit 1, the low update unit 3 is updated until the situation is reached. Can be stopped. From these viewpoints, the present method that allows each updating unit to operate independently is also effective.

  Next, the processing operation of the context updating unit 1 shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a flowchart showing the processing operation of the context update unit 1 shown in FIG. The context update unit 1 inputs context information (encoding parameter and MPS symbol value) and a symbol, and reads a state transition value of a symbol generation probability corresponding to the encoding parameter and an MPS symbol value corresponding to the encoding parameter ( Steps S1, S2). Then, the state transition table is accessed using the value as an address, and the value when the input symbol is MPS or LPS is read (step S3). Then, by comparing with the MPS symbol value (step S4), it is determined whether the symbol value is MPS or LPS (step S5), and the symbol occurrence probability corresponding to the encoding parameter is set to a suitable one of the previously read values. The value is stored as an updated value in the table storing the state transition values (step S6). Then, information indicating whether the input symbol value is MPS or LPS and a state transition value of the symbol occurrence probability indicating the symbol occurrence probability before update are output.

  Next, the processing operation of the range update unit 2 shown in FIG. 1 will be described with reference to FIG. FIG. 3 is a flowchart showing the processing operation of the range update unit 2 shown in FIG. The range updating unit 2 reads the LPS section length from the rLPS table 4 using the received state transition value of the symbol occurrence probability as an address (step S11). Since the LPS section length to be read differs depending on the upper 2 bits of the received range value, four values are read simultaneously from the rLPS table 4 and one value is selected according to the range value (step S12). The range value itself is a value obtained by subtracting the value of the selected rLPS table from the received range value and the value of the selected rLPS table in the case of LPS, according to the received LPS / MPS information. Is selected (step S13), and if the value is less than 256, the value is shifted to the left so that it is 256 or more and less than 512 (step S14). This shift is a process called renormalization. In this way, the range value is updated. Then, LPS / MPS information necessary for updating the low value, the left shift amount obtained at the time of re-normalization, and a value obtained by subtracting the value of the selected rLPS table from the range value are output.

  Next, the processing operation of the row updating unit 3 shown in FIG. 1 will be described with reference to FIG. FIG. 4 is a flowchart showing the processing operation of the row update unit 3 shown in FIG. In the case of MPS, the row update unit 3 shifts the row value received from the range update unit to the left by the LPS / MPS information and updates the value (step S21). In the case of LPS, the value obtained by subtracting the value of the selected rLPS table 4 from the range value received from the range update unit 2 is subtracted from the range value and updated by shifting the received shift amount to the left (step S22). At this time, the bits determined from the MSB side of the low value are output as a bit stream, and the remaining bits are finally set to the updated low value (step S23). In this way, the binary arithmetic code processing is executed.

  Next, a configuration for performing parallel processing by cascading binary arithmetic coding processing will be described. Considering that a plurality of bins are processed simultaneously in each updating unit in order to speed up the binary arithmetic encoding process, for example, the processing blocks shown in FIG. 1 are arranged in parallel, and 2 as shown in FIG. Two bins (symbols) are read at the same time, and each update unit cascades the processing and passes the processing result to the update unit in the next stage, thereby enabling parallel processing. FIG. 5 is a block diagram showing a configuration of 2-parallel binary arithmetic code processing.

  When the context A and the context B are different, the context update is performed independently by the context update unit 5 using the context A and the symbol A and the context update unit 6 using the context B and the symbol B.

  However, when context A and context B are the same, context B information is not used, and context B is updated using the updated context A information. The context update is executed according to the LPS / MPS information from the state transition table using the state transition value of the symbol generation probability corresponding to the determined encoding parameter as an address. Since the normal state transition table is configured by a memory, it is necessary to read the memory for updating the context A and to perform the memory reading for updating the context B with the updated value. In general, since the memory access speed is slow, the time spent for simultaneously updating the context for 2 bins becomes long. Therefore, the merit of parallel processing is reduced. Since the contents of the state transition table are not rewritten, it is conceivable that the context B state transition table is configured not by a memory but by a combinational circuit. However, there are disadvantages such as an increase in circuit scale.

  Therefore, paying attention to the structure of the state transition table contents, the context A state transition table and the context B state transition table are accessed simultaneously even when the context A context update value is not fixed, thereby reducing the processing time. To do. FIG. 6 is a block diagram showing a device configuration for speeding up the binary arithmetic encoding process. The context update unit 21, the range update unit 22, the row update unit 23, and the bit stream generator 24 are connected as shown in FIG. 6, and the input context A and context B are processed simultaneously, and 2 bin / cycle is It becomes feasible, and the speed of the binary arithmetic encoding process can be realized.

  FIG. 7 is a diagram showing the contents of the state transition table. As shown in FIG. 7, the state transition table stores an update value when the received symbol is LPS or MPS, depending on the state value of the context before update. For example, if the current state value is 31, the state value is updated to 24 if the symbol is LPS and to 32 if the symbol is MPS. As is clear from FIG. 7, when the current state is 31, the possible state value is 24 or 32. Therefore, the state value that can be taken by the next context update is 24 when the current update value is 24. If it is 19 or 25 and the current update value is 32, it is 24 or 33. That is, the table contents are redundant, but when the current state value is 31, 24 and 32 that can be obtained by the first context update are stored, and 19, 25, 24, which can be obtained by the next context update. By storing 33 as well, it becomes possible to obtain a state value required at the time of updating the context one after another (see FIG. 8). FIG. 8 is a diagram showing the configuration of the state transition table contents for two parallel processing.

  Here, the update value selection process will be described with reference to FIG. FIG. 9 is a flowchart showing an update value selection operation. First, it is determined whether or not the context A and the context B are the same (step S31). If the result of this determination is that they are not the same, it is determined whether or not the LPS / MPS information of context A is LPS (step S32). If the result of this determination is LPS, LPS is selected as the update value, and if it is MPS, MPS is selected as the update value.

  On the other hand, if the context A and the context B are the same, it is determined whether the LPS / MPS information of the context A is LPS (step S33). If the result of this determination is LPS, it is further determined whether or not the LPS / MPS information of context B is LPS (step S34). If the result of this determination is LPS, LPSLPS is selected as the update value, and if it is MPS, LPSMPS is selected as the update value.

  If the result of determination in step S33 is MPS, it is further determined whether or not the LPS / MPS information of context B is LPS (step S35). If the result of this determination is LPS, MPSLPS is selected as the update value, and if it is MPS, MPSMPS is selected as the update value.

  Next, with reference to FIG. 10, a context update process for performing two parallel processes will be described. FIG. 10 is a block diagram illustrating a configuration of the context update unit 21 illustrated in FIG. 6 that performs two parallel processes. The context update unit 21 includes registers binValA31 and binValA′32 that temporarily store the value of the symbol of context A according to the process. In addition, registers binValB33 and binValB'34 for storing the value of the context B symbol in accordance with the processing are provided. Also provided are registers ctxIdxA35 and ctxIdxA'36 for temporarily storing a context number indicating the context information of context A. Also provided are registers ctxIdxB37 and ctxIdxB'38 for temporarily storing the context number of context B. Further, a memory valMps [] 39 for storing the dominant symbol value for each context and a memory pStateIdx [] 40 for storing the current probability state for the context are provided. In addition, selectors Sel1 · 41 and Sel5 · 42 that select valMps to be used for each context update process from valMps [] 39 using ctxIdxA35 and ctxIdxB37 or from values being updated are provided.

  In addition, selectors Sel2 · 43 and Sel6 · 44 that select pStateIdx used for each context update process from pStateIdx [] 40 using ctxIdxA and ctxIdxB or from values being updated are provided. Also, registers valMpsA45 and valMpsB46 that temporarily store the dominant symbols used for the update processing of context A and context B, and registers pStateIdxA47 that temporarily store the context numbers used for the update processing of context A and context B, pStateIdxB48 is provided. Also, transIdx [] 49, which is a state transition table of the symbol occurrence probability, Sel3 · 50, Sel11 · 51 for selecting the update value of the dominant symbol value of context A and context B, and the update value of the state of symbol occurrence probability of context A Sel4 · 52, Sel7 · 53, Sel10 · 54, and Sel12 · 55 for selecting the update value of the state of the symbol occurrence probability of context B.

  Further, Sel8 · 56, which selects whether to use the updated dominant symbol of context A or the value of valMpsB46 temporarily storing the dominant symbol of context B as the dominant symbol value of context B, Select whether to use the state value of the updated symbol occurrence probability of the context A or the value of the pStateIdxB48 that temporarily stores the state of the symbol occurrence probability of the context B as the state value of the symbol occurrence probability. 57, a selection signal generator 58 for generating selection signals of Sel1 · 41 and Sel2 · 43. In addition, a selection signal generator 59 for generating selection signals of Sel5 · 42 and Sel6 · 44 is provided.

  Also, selection signal generators 62 and 63 for generating selection signals of LPS / MPS generators 60 and 61, Sel3 · 50, and Sel11 · 51 that generate whether the symbols of the context A and the context B are dominant symbols or recessive symbols are provided. Prepare. If the contexts A and B are the same, the Sel8 / 56, Sel9 / 57 are instructed to use the context A information, and the Sel10 / 54 selects LPSLPS or LPSMPS, MPSLPS, MPSMPS of the occurrence probability state transition information. Same context signal generator for generating a signal that instructs to not write back the dominant symbol value and occurrence probability state value in context A to memory so that writing of the dominant symbol value and occurrence probability state value for the context does not collide 64.

  The selection signal generator 58 generates a selection signal based on the logic shown in FIG. 11, and the selection signal generator 59 generates a selection signal based on the logic shown in FIG. 11 and FIG. 12, A == A ′? The state with a circle in the column indicates that the value of ctxIdxA35 and the value of ctxIdxA'36 are the same, and the selection signal 001 is the input connected to Sel1 · 41 and Sel2 · 43 in FIG. This means that the right value is selected. For example, when this is 100, it means that the left value is selected. Thus, when contexts A and B are different, the dominant symbol and occurrence probability state of each context are updated independently. When context A and B are the same, the dominant symbol and occurrence probability state value in context A are updated. The context update process of the context B can be performed using the value.

  The LPS / MPS generators 60 and 61 compare the symbols of the context A or the context B with the dominant symbols, and if they are the same, output 1 to indicate that they are MPS, and if they are different, output 0 and the LPS. Indicates that there is.

  The selection signal generators 62 and 63 invert the dominant symbol value of the context when the output signal from the LPS / MPS generators 60 and 61 of the context A or the context B is LPS and the occurrence probability state value is 0. A selection signal is sent to Sel3 · 50 and Sel11 · 51.

  The same context signal generator 64 compares the values of ctxIdxA′36 and ctxIdxB′38 in order to determine whether the contexts A and B are the same as described above. If they are the same, the contexts A and B are the same. It is determined that there is a memory write in the processing on the context A side, and the context information on the context A side is used on the context B side.

  9 is realized by Sel7 · 53, Sel10 · 54, and Sel12 · 55.

  Here, valMps [] 39 and pStateIdx [] 40 storing the dominant symbol and occurrence probability state of each context are individually shown on the reading side and writing side, and further on the context A side and B side in FIG. Although illustrated, since the same stored contents are required, a 4-port memory having 2 read ports and 2 write ports is actually required. Further, the present invention is not limited to the memory and can be applied to any other multi-port storage device such as a register. Furthermore, transIdx [] 49, which is a state transition table, may be implemented individually in contexts A and B, or may be implemented in one ROM or the like. In that case, on the context A side, it is possible to reduce the circuit scale by outputting only the values of transLPS and transMPS.

  By configuring the context update unit as shown in FIG. 10, the pipeline processing shown in FIG. 13 is possible, and context update for 2 bins is executed every cycle. FIG. 13 shows the flow of processing when the second, third, fourth, and sixth bins are the same context, and the first and fifth bins are different contexts by arrows. The 1st bin and the 5th bin indicate that R → Ex → W is executed independently. Here, R, Ex, and W represent data reading, processing execution, and update data writing, respectively. The third and sixth bins indicate that the values written in the memory at the second and fourth bins are used instead of the read values. The fourth bin indicates that the updated value of the third bin is used instead of the read value. Thus, the context update process can be executed even in a state where continuous contexts and independent contexts are mixed.

  Next, a range update process for performing two parallel processes will be described with reference to FIG. FIG. 14 is a block diagram illustrating a configuration of the range update unit 22 illustrated in FIG. 6 that performs two parallel processes. The range updater 22 includes registers LPS / MPSA71 and LPS / MPSA'72 that temporarily store LPS / MPS information of context A, registers LPS / MPSB73 and LPS / MPS that temporarily store LPS / MPS information of context B MPSB'74. Also, pStateIdxA75 that temporarily stores the occurrence probability state value of the context A, pStateIdxB76 that temporarily stores the occurrence probability state value of the context B, rLPS realized by a memory, a register, or a combinational circuit that stores the LPS section length [] 77, and register groups 78 and 79 for temporarily storing the value of rLPS [] 77 read by using pStateIdxA75 and pStateIdxB76 as addresses.

  In addition, the register m_uiRangeA80 that temporarily stores the initial value of the range value, the register m_uiRangeA′81 that stores the updated value of the range value, and the LPS / MPS information corresponding to the context A and the occurrence probability state are updated. There are provided registers validA82 and validA'83 for temporarily storing a signal for designating. Similarly, there are provided registers validB84 and validB′85 for temporarily storing a signal for designating whether to update the range value using LPS / MPS information corresponding to the context B or the occurrence probability state.

  Also suitable for the range value from among the register groups 78 and 79 for temporarily storing the LPS section length read from the adders 86 and 87 and rLPS [] 77 necessary for updating the range value. Sel 2 and 86 corresponding to context A for selecting a value and Sel 5 and 87 corresponding to context B are provided. In addition, Sel3 · 88 corresponding to the context A for selecting the range value updated by the LPS / MPS signal, Sel6 · 89 corresponding to the context B, and the selected Ragne value to be renormalized to 256 or more and less than 512 It includes a priority encoder 90 for the context A and a left shifter 91, a priority encoder 94 for the context B and a left shifter 95. Also, depending on whether the information for context A and context B is valid or invalid, Sel4 • 92 for selecting a value for updating the range value, and selecting Sel4 input from the information for valid / invalid of context A and context B It consists of a selection signal generator 93 that generates a signal.

  By adopting such a configuration, the read address of rLPS [] 77 storing the LPS section length of the second bin does not depend on the updated range value of the first bin, and is generated from the context update unit. As soon as the probability state value is received, the LPS section length candidate can be read out, so that the rLPS [] 77 of the first bin and the second bin can be accessed simultaneously. As a result, the processing time is reduced by the memory access time of the second bin rLPS [] 77, and the range value update is speeded up.

  In addition, in the range update, it is conceivable that information for 2 bins is not always input because of processing timing, but only information for 1 bin is input, or nothing is input. Therefore, a valid signal is used to indicate whether the information corresponding to each context is valid. When validA'83 and validB'85 are both valid, it is necessary to perform processing for 2 bins, so the range value is updated with the value after the two-stage range value update for context A and context B information is performed. Therefore, the selection signal generator 93 generates a selection signal so that the signal on the right side of Sel4 · 92 is output.

  If only validA'83 is valid, the signal for the middle of Sel4 is output to update the range value with the value after the one-stage range update for the context A information to process 1 bin. As described above, the selection signal generator 93 generates a selection signal. If both are invalid, the selection signal generator 93 generates a selection signal so that the left signal of Sel4 • 92 is output in order to keep the current range value.

  LPS / MPS (LPS / MPSA, LPS / MPSB) of each context required for low value update, shift amount required for renormalization (numbitsA, numbitsB), value obtained by subtracting LPS section length from range value ( curr_m_uiRangeA, curr_m_uiRangeB), and signals (validA, validB) indicating whether the information output by each context is valid.

  Next, a row update process that performs two parallel processes will be described with reference to FIG. FIG. 15 is a block diagram illustrating a configuration of the row update unit 23 illustrated in FIG. 6 that performs two parallel processes. The row update unit 23 includes registers LPS / MPSA 101 and LPS / MPSA ′ 102, LPS / MPSB 103 and LPS / MPSB ′ 104 that temporarily store LPS / MPS signals for context A and context B. In addition, registers numBitsA105 and numBitsA'106, and numBitsB107 and numBitsB'108, which temporarily store bit shift amounts necessary for renormalization with respect to context A and context B, are provided.

  Further, registers curr_m_uiRangeA109, curr_m_uiRangeA'110, curr_m_uiRangeB'111, and curr_m_uiRangeB'112 are provided for temporarily storing values obtained by subtracting the LPS section length from the range values for context A and context B. In addition, there are provided registers validA113 and validA'114, and validB115 and validB'116 for temporarily storing signals for designating whether or not to perform row update for each of context A and context B.

  In addition, a register m_uiLow 117 that temporarily stores an initial value of a low value, a register m_uiLow '118 that is an updated value of Low, and an initial value of a total sum of shift amounts by renormalization processing for the current row are temporarily stored. A register acc_shift 119 to be stored, and a register acc_shift ′ 120 to store a shift amount by the renormalization process for the current row. Also, at the time of initialization, m_uiLow'118 and acc_shift'120 are set to m_uiLow117 and acc_shift119, and otherwise, the total amount of shift by renormalization processing for the updated current row is set in the same manner as the updated row. · 121 and Sel4 · 122 are provided.

  Further, when the LPS / MPS signals of the context A and the context B are LPS, the curr_m_uiRangeA'110 or the curr_m_uiRangeB'112 is added with the m_uiLow'118 value or the updated m_uiLow117 value, and the LPS / MPS signal is selected. When the MPS signal is MPS, selectors Sel2 · 123 and Sel7 · 124 for selecting rows that have not been updated are provided.

  In addition, when the information for the context B is invalid, the LPS / MPS signal is set to MPS, the renormalization shift amount is set to 0, and the information for the context B is valid so that the low value update for the context B is not performed. In order to perform row update, selectors Sel5 · 125 and Sel6 · 126 are selected to use the LPS / MPS signal and the renormalization shift amount for the received context B. In addition, l shifters 1 and 127 and l shifters 2 and 128 for shifting the updated low values selected in Sel2 · 123 and Sel7 · 124 to the left by shift amounts by renormalization for context A and context B are provided.

  Also, an adder 129 that adds the renormalization shift amount for the received contexts A and B, an adder 130 that adds the added value and the acc_shift ′ value, and the added value is a predesignated value. The determination unit 131 includes a determination unit 131 that determines whether or not one of the context A and the context B or both are valid. In addition, a logical product unit 133 that sets valid to 1 is provided to indicate that the output of the determiner 132 is valid and exceeds the threshold value that the determiner 131 has, and is valid for the bitstream generator.

  When the determination unit 131 determines that the threshold is exceeded, the shift amount subtracted from the output of the adder 130 (here, 8) is passed, and when it is determined that the threshold is not exceeded, the previous addition is performed. Selectors Sel 9 and 134 for selecting the output of the selector 130. Here, it is assumed that bits are passed to the bit stream generator in units of 8 bits, and the value obtained by the l shifter 2 · 128 is right-shifted by the number of bits obtained by adding 2 to the output of the adder 130, and the bit For example, a mask value for temporarily obtaining a value that is not output to the bit stream generator by the r shifter 4 or 135 from the output of the r shifter 4 or 135 or l shifter 2 or 128 output to the stream generator is 32, for example. In the case of a bit calculator, an r shifter 3 · 136 is provided that shifts the accumulated shift amount, which is the output of the adder 130, to a value obtained by subtracting from 0 to 0xffffffff to the right.

  Also, when sending data to the bitstream generator, the data excluding the bits passed to the bitstream generator as a low update value is output from the l shifter 2 · 128 when no data is sent to the bitstream generator. Sel8 · 137 for selecting the accumulated low value as the update candidate value of the low value. If neither context A nor context B is valid, the current row value is kept, and if any one is valid, the update candidate value that is the output of Sel8 · 137 is set as the row update value. 138.

  In the above description, the case where the threshold value is 8 has been described. Each shift amount is as shown in FIG. 16, and when configured by hardware, it can be realized by a barrel shifter or the like without using a mask or the like. Since the output value to the bit stream generator is acc_shift−8 + 10 as apparent from FIG. 16, the output of the l shifter 2 · 128 is right-shifted by a value obtained by adding 2 to acc_shift. Further, since it is necessary to set acc_shift + 2 minutes bit 1 as apparent from FIG. 16, it is necessary to shift the value of all 1s to the right by 32− (acc_shift + 2), that is, 30−acc_shift. Alternatively, when configured with hardware, a mask value can be easily generated by a left shift or a combinational circuit, so 1 may be set from the LSB side for acc_shift + 2 bits.

  By adopting such a configuration, it is possible to update the row values for the first bin and the second bin in parallel, and the bit that is no longer directly involved in the row value update in accordance with the shift of the row value by renormalization. Minutes can be sent to the bitstream generation processing unit, and the number of bits of the arithmetic unit that performs the low value update is reduced. This reduction in the number of bits improves the operation processing speed and speeds up the low value update during parallel operation.

  Next, an example of bit stream generation processing when data is received from the row update unit in units of 8 bits will be described. FIG. 17 is a diagram showing the configuration of the bit stream generation unit 24 shown in FIG. The bit stream generation unit 24 receives selectors Sel1 and 151 that select whether to continue holding the values of outByte_r150 and outByte_r150 for temporarily storing the output bitstream or to receive new data according to the instruction of the state machine. When it is necessary to add the carry of the data to outByte_r150, an adder 152 that adds the carry, whether the value output as a bit stream is outByte_r, 0xff, or 0x00 is determined by the instruction of the state machine Sel4 and 153 to be selected are provided.

  In addition, Sel 2 155 for selecting whether the count value used by the state machine 154 is initialized or updated using the updated value, the number of data not yet output from the bit stream generator used by the state machine 154 Counter cnt_r 156 and Sel 3 157 for selecting whether to increment or decrement cnt_r 156 according to an instruction from state machine 154. The state machine changes the state to Idle, Store, Out1, or Out2 as shown in FIG. 18 according to the received data, the valid information of the data, and the value of cnt_r156.

  Basically, the value received from the row update unit is output as a bit stream. However, when the received data is 0xff, if a carry bit is set in the next data, 0xff is inverted to 0x00 and 0xff The carry propagates to the previous data. Therefore, the temporarily received data is held, and it is checked whether or not the next data is 0xFF. If it is not 0xFF, the previously held data is output as a bit stream, and the newly received data is registered in the register. Repeat to hold on. If the next data is 0xFF, even if 0xFF continues one after another, if the data that is not 0xFF has a carry, they all become 0x00. As described above, a carry is added to the data before 0xFF. Propagate.

  Therefore, when the next data is 0xFF, the data of outByte_r is continuously held, and the number of data is added to the count together with the amount of outByte_r. This can be dealt with by increment or the like. When data that is not 0xFF is received after 0xFF continues, it is confirmed whether there is a carry. If there is, carry is added to outByte_r, so the left data of Sel4 • 153 is selected and output. Then, the counter is decremented. If the counter exceeds 1, it indicates that there is 0xFF of data for the excess, so if there is a previous carry, 0x00 continues to be output until the counter reaches 1, and the counter is decremented, otherwise 0xFF Is continuously output until the counter reaches 1. When it becomes 1, the received data is held in outByte_r.

  In this way, the bitstream generation process is executed, and a bitstream is generated from the received low value.

  As described above, in addition to independently updating the state of symbol generation probability, range value, and low value of each context representing the internal state of the binary arithmetic coding unit, the dependency of the state of symbol occurrence probability By using, the occurrence probabilities for a plurality of bins are read out at once, and the update process is performed, so that high speed can be realized.

  The binary arithmetic coding apparatus in the above-described embodiment may be realized by a computer. In that case, a program for realizing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be read into a computer system and executed. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” dynamically holds a program for a short time like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. In this case, a volatile memory inside a computer system serving as a server or a client in that case may be included and a program held for a certain period of time. Further, the program may be for realizing a part of the functions described above, and may be a program capable of realizing the functions described above in combination with a program already recorded in the computer system. It may be realized using hardware such as PLD (Programmable Logic Device) or FPGA (Field Programmable Gate Array).

  As mentioned above, although embodiment of this invention has been described with reference to drawings, the said embodiment is only the illustration of this invention, and it is clear that this invention is not limited to the said embodiment. is there. Therefore, additions, omissions, substitutions, and other modifications of the components may be made without departing from the technical idea and scope of the present invention.

  Even if parallelization at the algorithm level such as slice division is not performed, it can be applied to an application in which it is indispensable to speed up binary arithmetic coding processing by parallel processing of a plurality of bin sequences.

  1, 5, 6, 21 ... context update unit, 2, 7, 8, 22 ... range update unit, 3, 9, 10, 23 ... row update unit, 4, 11, 12 ... rLPS table, 24... bitstream generation unit

Claims (5)

A context update unit for calculating a state transition value of the symbol occurrence probability state and MPS / LPS information from the context information and the symbol;
A range update processing unit that calculates a renormalization shift amount from the state transition value of the symbol occurrence probability state, the MPS / LPS information and the range value, and simultaneously updates the range value;
A low value update unit that updates a low value from the renormalization shift amount, the MPS / LPS information, the updated range value and a low value;
A binary arithmetic encoding device comprising: a bitstream generation unit that generates a bitstream using the updated row value;
The context update unit performs parallel processing on a plurality of bins with reference to the occurrence probability state table when simultaneously determining the occurrence probability state of the second bin from the occurrence probability state of the first bin ,
The range update processing unit reads the value of the LPS section length table using the occurrence probability state of the first bin and the second bin, selects a plurality of values from the read values using the range value, A binary arithmetic coding apparatus, wherein the range value is updated and a renormalization shift amount is calculated . The low value update unit receives a plurality of the MPS / LPS information, the renormalization shift amount, and the updated range value, performs cumulative addition of the low value and the renormalization shift amount, and performs the cumulative addition When the result exceeds a specified threshold, the data is output to the bitstream generation unit, and is reduced from the result of the cumulative addition by the number of bits of the low value and the output data. The binary arithmetic coding apparatus according to claim 1 . The bit stream generation unit holds the received data temporarily to perform carry processing, does not output when there is a possibility of carry, adds only the received data amount, and carries When it is confirmed that no carry occurs, the carry data is processed and the stored data is output as a bit stream, and 1 or 0 is continuously output until the received data amount becomes 1, and the check is continued. The binary arithmetic coding apparatus according to claim 2 , wherein the data used in the step is temporarily held again. A context update unit for calculating a state transition value of the symbol occurrence probability state and MPS / LPS information from the context information and the symbol;
A range update processing unit that calculates a renormalization shift amount from the state transition value of the symbol occurrence probability state, the MPS / LPS information and the range value, and simultaneously updates the range value;
A low value update unit that updates a low value from the renormalization shift amount, the MPS / LPS information, the updated range value and a low value;
A binary arithmetic encoding method performed by a binary arithmetic encoding device including a bitstream generation unit that generates a bitstream using the updated row value,
When the context update unit simultaneously determines the occurrence probability state of the second bin from the occurrence probability state of the first bin, the plurality of bins are processed in parallel with reference to the occurrence probability state table ,
The range update processing unit reads the value of the LPS section length table using the occurrence probability state of the first bin and the second bin, selects a plurality of values from the read values using the range value, A binary arithmetic coding method, wherein the range value is updated and a renormalization shift amount is calculated . A binary arithmetic encoding program for causing a computer to function as the binary arithmetic encoding device according to any one of claims 1 to 3 .

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