JP2005217871A - Arithmetic decoding apparatus and arithmetic decoding program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic decoding apparatus and an arithmetic decoding program for performing decoding processings of a plurality of bits in batch. <P>SOLUTION: An internal state information storing unit 3 stores internal state information and an MPS column which is a bit column of MPS ranging from a first bit to the nth bit; an internal state information evacuating unit 4 stores internal state information which is stored in the internal state information storing unit 3, when an decoding request is made; a look-up table storing unit 5 stores table information; a batch decoding processing managing unit 2 determines whether it is possible to perform batch decoding processing and when the batch decoding processing is determined to be possible, supplies a plural bits batch decoding unit 6 with a decoding request, a graph value for indicating a method of batch decoding, a batch-decoding bit number n, and MPS column; and the plural bit batch decoding unit 6 generates and outputs decoding data comprising MPS of n bit continuous, or generates and outputs decoding data, comprising 1 bit LPS after MPS of n-1 bit continuity based on the MPS column. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an arithmetic decoding device and an arithmetic decoding program that perform decoding processing at high speed.

  Arithmetic coding is one of entropy coding, and it is known that efficient coding is possible. Arithmetic coding is a method of coding by associating a symbol sequence to be coded with a coded sequence having a value of 0 or more and less than 1, and performs decoding by following the value of the coded sequence. The number of bits for expressing a coded sequence for a symbol sequence with a high probability of occurrence or a short symbol sequence may be small, but for a symbol sequence with a low probability of occurrence or a long symbol sequence, the number of bits for representing a coded sequence Will grow.

  Arithmetic coding is used for image compression, audio compression, and the like, and the symbol sequence to be encoded may be composed of a sequence of a plurality of symbol sequences having different characteristics. In such a case, it is known that by preparing a plurality of probability models in advance and sequentially switching to the probability model that matches the characteristics of the sequence to be encoded, the encoding efficiency can be improved. . A group of probabilistic models prepared in advance is called a context. Generally, a context is composed of a dominant symbol (MPS) and a state necessary for obtaining the occurrence probability of MPS. Arithmetic coding in which a plurality of contexts are prepared in advance and the context is switched by a symbol to be coded and a bit to be decoded is called multi-context arithmetic coding.

  Here, the multi-context binary arithmetic code operation will be described with reference to FIG.

  In FIG. 9, (v) is the initial area width at the start of decoding, and (u) is the initial value of the data series to be decoded.

  First, a predetermined initialization process is performed before starting decoding. The initialization process is performed on the current area width, the data series to be decoded, and the context.

  Decode the first bit. When a context is given, the region (v) is divided based on the context. (W) is a region corresponding to the inferior symbol (LPS), and (x) is a region corresponding to the dominant symbol (MPS). Since the data sequence (u) to be decoded is included in (x), the first bit outputs MPS. Hereinafter, the decoding proceeds by repeating the same operation with (x) as the current region width, but it is necessary to perform a normalization process to maintain the calculation accuracy.

  The normalization process will be specifically described. When the current region width becomes smaller than a predetermined normalization determination value, the current region width and the data sequence to be decoded are left by 1 bit until the current region width becomes equal to or greater than the normalization determination value. Repeat the shift. Zeros are filled in the bits on the right side with the empty current area width, and the bits on the right side of the data series to be decoded are padded with data bit by bit from the bit stream. The number of bits is determined for both the current area width and the data series to be decoded, and both overflow bits are discarded.

  Normalization is for maintaining the calculation accuracy of arithmetic coding, and the normalization determination value is used for determining whether normalization is necessary. In general, the normalization determination value takes a value that is half the maximum value of the region width.

  As an example of multi-context arithmetic decoding, FIG. 10 shows the configuration of CABAC arithmetic decoding apparatus 101 employed in H.264 (Non-patent Document 1). The arithmetic decoding apparatus 101 includes a control unit 102, an arithmetic decoding unit 103, an internal state information storage unit 104, and a reference table storage unit 105.

  The context index indicates the context of the bit to be decoded now.

  When the decoding request is input together with the context index, the control unit 102 reads out necessary data from the internal state information storage unit 104 and the reference table storage unit 105, updates the internal state information in the internal state information storage unit 104, It has a function to send the updated internal state information to the arithmetic decoding unit 103 together with the decoding request. Also, when receiving a decoding end notification from the arithmetic decoding unit 103, the control unit 102 reads internal state information from the arithmetic decoding unit 103, performs normalization if necessary, and performs internal state information storage unit 104. Has a function of updating.

  The arithmetic decoding unit 103 has a function of performing arithmetic decoding and outputting it as decoded data when a decoding request is sent from the control unit 102 together with the internal state information. The arithmetic decoding unit 103 has a function of updating the internal state information and sending a decoding end notification to the control unit 102.

  The internal state storage unit 104 stores internal state information. The internal state information includes at least a current area width, a data series to be decoded, and a context. If there is a request from the control unit 102, the internal state information stored in the internal state information storage unit 104 is sent to the control unit 102.

  The reference table storage unit 105 stores reference table information necessary for updating the internal state information in the internal state information storage unit 104. If there is a request from the control unit 102, reference table information stored in the control unit 102 is sent.

  Next, the operation of the arithmetic decoding apparatus 101 during the CABAC decoding process will be described using the flowchart of FIG. A context index is given as input.

  First, the control unit 102 reads data necessary for updating the current region width from the internal state information storage unit 104 and the reference table storage unit 105, and updates the current region width (step S101).

  The control unit 102 reads the current region width and the data sequence to be decoded from the internal state information storage unit 104, compares both, and determines whether or not the current region width is equal to or smaller than the data sequence to be decoded. (Step S102). If the current area width is equal to or smaller than the data sequence to be decoded, the control unit 102 sends the LPS decoding request and the current MPS to the arithmetic decoding unit 103, and if not, the MPS decoding request and the current MPS are sent. send.

  When an LPS decoding request and the current MPS are sent from the control unit 102 to the arithmetic decoding unit 103, the arithmetic decoding unit 103 outputs a value obtained by inverting the MPS, and the control unit 102 outputs an internal state information storage unit. The internal state information 104 is updated (step S103).

  When the MPS decoding request and the current MPS are sent from the control unit 102 to the arithmetic decoding unit 103, the arithmetic decoding unit 103 outputs the MPS value, and the control unit 102 stores the MPS value in the internal state information storage unit 104. The internal state information is updated (step S104).

  Next, the control unit 102 determines whether it is necessary to reverse MPS and LPS (step S105).

  When it is necessary to invert MPS and LPS, the control unit 102 reads the context corresponding to the context index from the internal state information storage unit 104, inverts the MPS value, and returns it to the internal state information storage unit 104 (step S106).

  Next, the control unit 102 reads necessary internal state information from the internal state information storage unit 104, updates it, and returns it to the internal state information storage unit 104 (step S107).

  Next, the control unit 102 performs normalization (step S108) and ends the process.

  Real-time performance is required for image compression and the like, and the amount of arithmetic coding and decoding is reduced, and the processing speed is required. In arithmetic decoding processing, normalization processing is generally required, and normalization determination is required every time one bit is decoded. Therefore, it is very difficult to decode a plurality of bits at once. Met.

  By the way, an arithmetic decoding device that speeds up decoding processing by performing n-bit batch decoding processing on the condition that normalization does not occur even if arbitrary n bits are decoded even if the same context continues. (For example, Patent Document 1) is disclosed.

  In the method of Patent Document 1, when the same context is continuous and the MPS is continuous, the LPS width is constant (this is referred to as Qe). Therefore, if the initial region width is set as Areg, n bits The previous region width can be calculated by Areg−n × Qe. When this value is equal to or greater than the normalization determination value and the condition that the MPS is continuous is satisfied, a multi-bit batch decoding process is performed. Otherwise, a sequential process for each bit is performed.

  This technique was devised to speed up the decoding process of an arithmetic decoding apparatus that handles the encoding of an image composed of binary pixels. For encoded data in which one pixel value is continuous. Therefore, it is possible to perform decoding at a very high speed.

  The outline of the decoding process of the arithmetic decoding apparatus in Patent Document 1 will be described with reference to the flowchart of FIG.

  When starting the decoding process, the arithmetic decoding apparatus calculates Areg−n × Qe, determines whether the calculation result is equal to or greater than the normalization determination value (step S111), and the calculation result is equal to or greater than the normalization determination value. If there is, it is determined whether the context is continuous and the MPS is continuous (step S112).

  If the context is continuous and the MPS is continuous, the arithmetic decoding apparatus performs n-bit batch decoding processing (step S113), and if the calculation result is not equal to or greater than the normalization determination value, or the context is If continuous and MPS is not continuous, sequential decoding processing for each bit is performed (step S114).

  As described above, the arithmetic decoding device of Patent Document 1 determines whether batch decoding processing is possible according to the condition that the same context continues and the condition that normalization does not occur even when n bits are decoded. Is going.

  For this reason, in multi-context arithmetic coding such as CABAC, the frequency with which batch decoding processing is selected is drastically reduced for coded sequences in which contexts are frequently switched, and most of the bits are sequentially changed bit by bit. As a result, the decoding process cannot be speeded up.

In addition, normalization in the middle of n-bit decoding and normalization immediately after n-bit decoding cannot be distinguished under the condition that normalization does not occur even when n-bit decoding is performed. Even when this occurs, switching to sequential processing for each bit makes it difficult to increase the speed.
ITU-TH. H.264 Japanese Patent No. 3350482

  The present invention has been made in view of the above circumstances, and determines whether or not a plurality of bits can be decoded at once, and performs arithmetic decoding processing at high speed by performing batch decoding processing if possible. It is an object to provide a decoding device and an arithmetic decoding program.

  In order to achieve the above object, the arithmetic decoding apparatus according to claim 1, wherein the decoding request includes at least the current region width, the previous region width, the data sequence to be decoded, and the internal state information including the context. An arithmetic decoding device that, when supplied, performs arithmetic decoding and outputs decoded data, the internal state information, and a dominant symbol string that is a bit string of dominant symbols from the first bit to the nth bit. Internal state information storage means for storing, initial internal state information saving means for storing the internal state information stored in the internal state information storage means when the decryption request is made, and update of the internal state information Table data storage means for storing the table information necessary for generating the decoded data consisting of n-bit consecutive dominant symbols based on the dominant symbol string, and outputting it Alternatively, the multi-bit batch decoding unit that generates and outputs the decoded data including the 1-bit inferior symbol after the n−1-bit consecutive dominant symbol and the initial data recorded in the initial internal state information saving unit Sending internal state information to the internal state information storage means, using the initial internal state information stored in the internal state information storage means, performing an arithmetic decoding process for each bit, generating the decoded data, The 1-bit decoding means to output, whether the batch decoding process is possible, the current area width read from the internal state information storage means, the previous area width, and the data series to be decoded If it is determined based on the above and batch decoding is possible, the decoding request, the flag value indicating the batch decoding method, the number of batch decoding bits, to the multi-bit batch decoding means And characterized in that it comprises a batch decoding processing management means for supplying the major symbol sequence.

  Further, the arithmetic decoding program according to claim 2, when a decoding request is supplied together with at least the current region width, the previous region width, the data sequence to be decoded, and the internal state information including the context, the arithmetic decoding program An arithmetic decoding program for causing a computer to function as an arithmetic decoding device that performs decoding and outputs decoded data, the computer having the internal state information, and predominance from the first bit to the nth bit An internal state information storage means for storing a dominant symbol string, which is a bit string of symbols, and an initial internal state information saver for storing the internal state information stored in the internal state information storage means when the decoding request is made Means, reference table storage means for storing table information necessary for updating the internal state information, and a dominant symbol string, Multiple-bit batch decoding means for generating and outputting the decoded data consisting of n-bit continuous dominant symbols, or generating and outputting the decoded data consisting of 1-bit inferior symbols after n-1 consecutive bits And sending the initial internal state information recorded in the initial internal state information saving means to the internal state information storage means, and using the initial internal state information stored in the internal state information storage means, The current area width read out from the internal state information storage means for performing 1-bit arithmetic decoding processing, generating and outputting the decoded data, and whether or not collective decoding processing is possible , Determining based on the previous area width and the data series to be decoded, and if batch decoding is possible, the multi-bit batch decoding means, No. request, characterized in that to function as a flag value, batch decoding processing management means for supplying batch decoded bit number n, and the dominant symbol string for indicating the method of batch decoding.

  According to the present invention, batch decoding can be performed even when context switching occurs. As a result, the frequency of decoding a plurality of bits at a time increases, and the decoding process can be speeded up.

  Also, if normalization occurs when performing n-bit batch decoding, the frequency of decoding multiple bits at once increases by determining whether normalization occurred immediately after n-bit decoding or not. The decoding process can be speeded up.

  An embodiment of the present invention will be described with reference to FIGS.

<< First Embodiment >>
In the first embodiment, a case will be described in which “MPS is n-bit continuous” and “normalization does not occur after n-bit decoding” regardless of whether context switching occurs.

  FIG. 1 is a functional block diagram illustrating a functional configuration of the arithmetic decoding device 1 according to the first embodiment.

  As shown in FIG. 1, the arithmetic decoding apparatus 1 according to the first embodiment includes a collective decoding processing management unit 2, an internal state information storage unit 3, an initial internal state information saving unit 4, a reference table storage unit 5, a plurality of bits. The block decoding unit 6 and the 1-bit decoding unit 7 are configured.

  The batch decoding process management unit 2 determines whether the batch decoding process is possible based on the current area width read from the internal state information storage unit 3, the previous area width, and the data series to be decoded. When batch decoding is possible, the multi-bit batch decoding unit 6 has a function of supplying a decoding request, a flag value indicating a batch decoding method, the batch decoding bit number n, and an MPS sequence. Have. Further, when batch decoding is not possible, the batch decoding processing management unit 2 has a function of supplying a decoding request to the 1-bit decoding unit 7. The batch decoding process management unit 2 has a function of updating the internal state information with respect to the internal state information storage unit 3, and the current area width of the internal state information storage unit 3 is less than the normalization determination value. In the case of a failure, it has a function of performing normalization processing. In the first embodiment, the batch decoding process management unit 2 sets a flag value indicating a batch decoding processing method when “MPS is n bits continuous” and “normalization does not occur after n bits decoding”. The multi-bit batch decoding unit 6 is supplied.

  The internal state information storage unit 3 stores internal state information and an MPS sequence. The internal state information includes at least the current region width, the previous region width, the data series to be decoded, and the context. Further, the MPS sequence is an MPS sequence from the first bit to the nth bit, and by storing the MPS sequence in the internal state information storage unit 3, it is possible to easily generate a sequence of MPSs. Become. The internal state information in the internal state information storage unit 3 is read by the batch decoding process management unit 2.

  The initial internal state information saving unit 4 stores the internal state information stored in the internal state information storage unit 3 when a decoding request is sent to the arithmetic decoding device 1.

  The reference table storage unit 5 stores reference table information necessary for updating the internal state information.

  The multi-bit batch decoding unit 6 has a function of performing multi-bit batch decoding processing. Specifically, the multi-bit batch decoding unit 6 generates and outputs decoded data composed of n-bit continuous MPS based on the flag value and the MPS sequence sent from the batch decoding processing management unit 2, or n− Generate and output decoded data consisting of 1-bit LPS after 1-bit MPS. In any case, the multi-bit batch decoding unit 6 updates the data in the internal state information storage unit 3.

  The 1-bit decoding unit 7 has a temporary storage unit (not shown) for temporarily storing the decoded data (not shown), and has a function of performing sequential decoding for each bit to generate and output decoded data. . Specifically, the 1-bit decoding unit 7 receives the initial internal state recorded in the initial internal state information saving unit 4 when a decoding request is notified from the batch decoding process management unit 2 to the 1-bit decoding unit 7. After the information is sent to the internal state information storage unit 3 and returned, the arithmetic decoding process for each bit is performed n times using the data in the internal state information storage unit 3. The 1-bit decoding unit 7 supplies the decoded data to the temporary storage unit bit by bit every time 1-bit decoding is performed.

  Next, the operation at the time of the decoding process of the arithmetic decoding apparatus 1 in the first embodiment will be described with reference to the flowchart of FIG.

  The number n of bits to be collectively decoded is input to the batch decoding process management unit 2, and the bit stream and context index are input to the internal state information storage unit 3 via the batch decoding process management unit 2.

  Here, the number of bits n for batch decoding, the context index n corresponding to each bit, and the bit stream to be decoded have already been given as inputs to the arithmetic decoding apparatus 1, and at this stage, all internal states It is assumed that the information has been initialized.

  First, the collective decoding process management unit 2 records all the internal state information at the start of the decoding process stored in the internal state information storage unit 3 in the initial internal state information saving unit 4 (step S01). The internal state information stored here is regarded as being incapable of batch decoding, and becomes initial state information when performing sequential decoding for each bit.

  Next, assuming that the MPS continues n times, the collective decoding process management unit 2 reads the reference table information stored in the reference table storage unit 5 and further stores the reference table information in the internal state information storage unit 3. The process of reading the internal state information and updating the area width and context is repeated n times (step S02). The area width when MPS continues n times is stored in the internal state information storage unit 3 as the current area width, and the area width when MPS continues n−1 times is stored as the previous area width. Recorded in part 3 respectively. In addition, the state where MPS continues n−1 times is recorded in the internal state information storage unit 3.

  This is shown in FIG. (A) to (e) of FIG. 3 show respective region widths when MPS continues from 0 to n times. The batch decoding process management unit 2 records the (n−1) th region width (d) as the previous region width in the internal state information storage unit 3, and sets the nth region width (e) as the current region width. Record in the internal state information storage unit 3. Also, an MPS sequence is generated based on the input context index and recorded in the internal state information storage unit 3.

  The batch decoding process management unit 2 reads the current area width and the data series to be decoded from the internal state information storage unit 3, and determines whether or not the current area width is larger than the data series to be decoded (step). S03).

  When the current region width is larger than the data series to be decoded, the collective decoding process management unit 2 reads the region width from the internal state information storage unit 3 and determines whether the region width is larger than the normalization determination value. However, if the region width is larger than the normalization determination value, a decoding request is notified to the multi-bit batch decoding unit 6 and an MPS sequence is supplied. It is assumed that the normalization determination value is stored in advance in the collective decoding process management unit 2.

  When a decoding request is notified to the multi-bit batch decoding unit 6 from the batch decoding process management unit 2 and an MPS sequence is supplied, the multi-bit batch decoding unit 6 generates and outputs decoded data composed of n-bit continuous MPS. (Step S05).

  Since the internal state information storage unit 3 records a value of a state in which MPS is continued n−1 times as a context, the batch decoding process management unit 2 stores the reference table information stored in the reference table storage unit 5. Is updated to the state where MPS has occurred once again (step S06).

  If the current area width is not larger than the data sequence to be decoded in step S03, or if the area width is not larger than the normalization determination value in step S04, the collective decoding process management unit 2 Reads out all internal state information recorded in the initial internal state information saving unit 4 at the start of the decoding process, records it in the internal state information storage unit 3 (step S07), and notifies the 1-bit decoding unit 7 of the decoding request. To do.

  When the decoding request is notified from the batch decoding processing management unit 2, the 1-bit decoding unit 7 performs a sequential decoding process for each bit, and each time 1-bit decoding is performed, a temporary storage unit in the 1-bit decoding unit 7 The encoded data is generated by supplying the decoded bits, and after the n-bit decoding is completed, the 1-bit decoding unit 7 outputs the decoded data stored in the temporary storage unit in the 1-bit decoding unit (step S08).

  By performing processing in this way, it becomes possible to perform batch decoding of an encoded sequence in which “MPS is n bits continuous” and “normalization does not occur after n bit decoding” regardless of whether context switching occurs, Decoding processing can be performed at high speed even for multi-context arithmetic decoding.

  FIG. 4 shows the region width when “MPS is n bits continuous” and “normalization does not occur after n bits decoding”. As shown in FIG. 4, when the area width from the initial state (f) to n bits (j) is not less than the normalization determination value, the collective decoding process is performed.

<< Second Embodiment >>
In the second embodiment, in addition to the collective decoding process described in the first embodiment, a case where “MPS is n-bit continuous” but “normalization occurs after n-bit decoding” will be described.

  The arithmetic decoding apparatus 1 according to the second embodiment includes a batch decoding process management unit 2, an internal state information storage unit 3, an initial internal state information saving unit 4, a reference table storage unit 5, a multi-bit batch decoding unit 6, and 1 The bit decoding unit 7 is used.

  The arithmetic decoding device 1 in the second embodiment has the same functional configuration as the arithmetic decoding device 1 in the first embodiment shown in FIG. In the second embodiment, the collective decoding process management unit 2 “MPS is n-bit continuous” and “normalization does not occur after n-bit decoding” or “MPS is n-bit continuous”. , A flag value indicating one of the batch decoding processing methods when “normalization occurs after n-bit decoding” is supplied to the multi-bit batch decoding unit 6.

  Next, the operation | movement at the time of the decoding process of the arithmetic decoding apparatus 1 in 2nd Embodiment is demonstrated using the flowchart of FIG.

  The number n of bits to be collectively decoded is input to the batch decoding process management unit 2, and the bit stream and context index are input to the internal state information storage unit 3 via the batch decoding process management unit 2.

  Here, the number of bits n for batch decoding, the context index n corresponding to each bit, and the bit stream to be decoded have already been given as inputs to the arithmetic decoding apparatus 1, and at this stage, all internal states It is assumed that the information has been initialized.

  First, the collective decoding process management unit 2 records all the internal state information at the start of the decoding process stored in the internal state information storage unit 3 in the initial internal state information saving unit 4 (step S11). The internal state information stored here is regarded as being incapable of batch decoding, and becomes initial state information when performing sequential decoding for each bit.

  Next, assuming that the MPS continues n times, the collective decoding process management unit 2 reads the reference table information stored in the reference table storage unit 5 and further stores the reference table information in the internal state information storage unit 3. The process of reading the internal state information and updating the area width and context is repeated n times (step S12). The area width when MPS continues n times is stored in the internal state information storage unit 3 as the current area width, and the area width when MPS continues n−1 times is stored as the previous area width. Recorded in part 3 respectively. In addition, the state where MPS continues n−1 times is recorded in the internal state information storage unit 3.

  The batch decoding process management unit 2 reads the current area width and the data series to be decoded from the internal state information storage unit 3, and determines whether or not the current area width is larger than the data series to be decoded (step). S13).

  When the current region width is larger than the data series to be decoded, the collective decoding process management unit 2 reads the region width from the internal state information storage unit 3 and determines whether the region width is larger than the normalization determination value. However, if the region width is larger than the normalization determination value, a decoding request is notified to the multi-bit batch decoding unit 6 and an MPS sequence is supplied. It is assumed that the normalization determination value is stored in advance in the collective decoding process management unit 2.

  When a decoding request is notified to the multi-bit batch decoding unit 6 from the batch decoding process management unit 2 and an MPS sequence is supplied, the multi-bit batch decoding unit 6 generates and outputs decoded data composed of n-bit continuous MPS. (Step S15).

  Since the internal state information storage unit 3 records a value of a state in which MPS is continued n−1 times as a context, the batch decoding process management unit 2 stores the reference table information stored in the reference table storage unit 5. Is updated to the state where MPS has occurred once again (step S16).

  If the region width is not larger than the normalization determination value in step S14, the batch decoding process management unit 2 reads the previous region width from the internal state information storage unit 3, and the previous region width Is larger than the normalization determination value (step S17), and if the previous area width is larger than the normalization determination value, the multi-bit batch decoding unit 6 is notified of the decoding request.

  When a decoding request is notified from the batch decoding processing management unit 2 to the multi-bit batch decoding unit 6, the batch decoding processing management unit 2 reads the current area width recorded in the internal state information storage unit 3 and the data to be decoded. A 1-bit normalization process is performed on the series (step S18), and the process proceeds to step S15.

  If the current region width is not larger than the data sequence to be decoded in step S13, or if the previous region width is not larger than the normalization determination value in step S17, batch decoding is performed. The process management unit 2 reads all the internal state information at the start of the decoding process recorded in the initial internal state information saving unit 4 and records it in the internal state information storage unit 3 (step S19), to the 1-bit decoding unit 7. Notify decryption request.

  When the decoding request is notified from the batch decoding processing management unit 2, the 1-bit decoding unit 7 performs a sequential decoding process for each bit, and each time 1-bit decoding is performed, a temporary storage unit in the 1-bit decoding unit 7 The encoded data is generated by supplying the decoded bits, and after the n-bit decoding is completed, the 1-bit decoding unit 7 outputs the decoded data stored in the temporary storage unit in the 1-bit decoding unit (step S20).

  By performing processing in this way, in addition to “MPS is n bits continuous” and “normalization does not occur”, “MPS is n bits continuous”, but “normalization is performed immediately after n bit decoding” Even in the case of “occurs”, the encoded sequence can be collectively decoded. Therefore, the frequency of performing the batch decoding process increases, and the decoding process can be speeded up.

  FIG. 6 shows the region width when “MPS is n bits continuous” but “normalization occurs after n bits decoding”. As shown in FIG. 6, in the region width from the initial state (k) to n bits (o), normalization after MPS occurs even if the region width of n bits (o) is less than the normalization determination value. Since 1 is always 1 bit, the batch decoding process is performed after normalizing 1 bit.

<< Third Embodiment >>
In the third embodiment, in addition to the collective decoding process described in the first and second embodiments, “MPS is continued for n−1 bits and then LPS occurs” is “n−1 bit decoding. A case where normalization does not occur later will be described.

  The arithmetic decoding apparatus 1 according to the third embodiment includes a collective decoding process management unit 2, an internal state information storage unit 3, an initial internal state information saving unit 4, a reference table storage unit 5, a multi-bit batch decoding unit 6, and 1 The bit decoding unit 7 is used.

  The arithmetic decoding device 1 in the third embodiment has the same functional configuration as the arithmetic decoding device 1 in the first and second embodiments shown in FIG. In the second embodiment, the collective decoding process management unit 2 “MPS is n-bit continuous” and “normalization does not occur after n-bit decoding” or “MPS is n-bit continuous”. , "When normalization occurs after n-bit decoding", "MPS continues n-1 bits, then LPS occurs", or "Normalization does not occur after n-1 bit decoding" The multi-bit batch decoding unit 6 is supplied with a flag value indicating the batch decoding processing method.

  Next, the operation | movement at the time of the decoding process of the arithmetic decoding apparatus 1 in 3rd Embodiment is demonstrated using the flowchart of FIG.

  The number n of bits to be collectively decoded is input to the batch decoding process management unit 2, and the bit stream and context index are input to the internal state information storage unit 3 via the batch decoding process management unit 2.

  Here, the number of bits n for batch decoding, the context index n corresponding to each bit, and the bit stream to be decoded have already been given as inputs to the arithmetic decoding apparatus 1, and at this stage, all internal states It is assumed that the information has been initialized.

  First, the collective decoding process management unit 2 records all the internal state information at the start of the decoding process stored in the internal state information storage unit 3 in the initial internal state information saving unit 4 (step S21). The internal state information stored here is regarded as being incapable of batch decoding, and becomes initial state information when performing sequential decoding for each bit.

  Next, assuming that the MPS continues n times, the collective decoding process management unit 2 reads the reference table information stored in the reference table storage unit 5 and further stores the reference table information in the internal state information storage unit 3. The process of reading the internal state information and updating the area width and context is repeated n times (step S22). The area width when MPS continues n times is stored in the internal state information storage unit 3 as the current area width, and the area width when MPS continues n−1 times is stored as the previous area width. Recorded in part 3 respectively. In addition, the state where MPS continues n−1 times is recorded in the internal state information storage unit 3.

  The batch decoding process management unit 2 reads the current area width and the data series to be decoded from the internal state information storage unit 3, and determines whether or not the current area width is larger than the data series to be decoded (step). S23).

  When the current region width is larger than the data series to be decoded, the collective decoding process management unit 2 reads the region width from the internal state information storage unit 3 and determines whether the region width is larger than the normalization determination value. However, if the region width is larger than the normalization determination value, a decoding request is notified to the multi-bit batch decoding unit 6 and an MPS sequence is supplied. It is assumed that the normalization determination value is stored in advance in the collective decoding process management unit 2.

  When a decoding request is notified to the multi-bit batch decoding unit 6 from the batch decoding process management unit 2 and an MPS sequence is supplied, the multi-bit batch decoding unit 6 generates and outputs decoded data composed of n-bit continuous MPS. (Step S25).

  Since the internal state information storage unit 3 records a value of a state in which MPS is continued n−1 times as a context, the batch decoding process management unit 2 stores the reference table information stored in the reference table storage unit 5. Is updated to the state where MPS has occurred once again (step S26).

  In step S24, if the area width is not larger than the normalization determination value, the collective decoding process management unit 2 reads the previous area width from the internal state information storage unit 3, and the previous area width Is larger than the normalization determination value (step S27), and when the previous area width is larger than the normalization determination value, the multi-bit batch decoding unit 6 is notified of the decoding request.

  When a decoding request is notified from the batch decoding processing management unit 2 to the multi-bit batch decoding unit 6, the batch decoding processing management unit 2 reads the current area width recorded in the internal state information storage unit 3 and the data to be decoded. A 1-bit normalization process is performed on the sequence (step S28), and the process proceeds to step S25.

  In step S27, if the previous area width is not larger than the normalization determination value, the collective decoding process management unit 2 records all the decoding processes at the start of the decoding process recorded in the initial internal state information saving unit 4. The internal state information is read out, recorded in the internal state information storage unit 3 (step S29), and a decoding request is notified to the 1-bit decoding unit 7.

  When the decoding request is notified from the batch decoding processing management unit 2, the 1-bit decoding unit 7 performs a sequential decoding process for each bit, and each time 1-bit decoding is performed, a temporary storage unit in the 1-bit decoding unit 7 The encoded data is generated by supplying the decoded bits, and after the n-bit decoding is completed, the 1-bit decoding unit 7 outputs the decoded data stored in the temporary storage unit in the 1-bit decoding unit (step S30).

  If the current area width is not larger than the data series to be decoded in step S23, the collective decoding process management unit 2 stores the previous area width and the data to be decoded from the internal state information storage unit 3. Each series is read out, and it is determined whether or not the previous area width is larger than the data series to be decoded and the previous area width is larger than the normalization determination value (step S31). When the width is larger than the data series to be decoded and the previous area width is larger than the normalization determination value, a decoding request is notified to the multi-bit batch decoding unit 6 and an MPS sequence is supplied.

  When the decoding request is notified to the multi-bit batch decoding unit 6 from the batch decoding process management unit 2 and the MPS sequence is supplied, the multi-bit batch decoding unit 6 receives the decoded data composed of n−1 bits of continuous MPS. After generation and output, the last bit of the MPS sequence is inverted to generate and output a decoded value consisting of 1-bit LPS (step S32).

  Since the internal state information storage unit 3 records a value of a state in which MPS is continued n−1 times as a context, the batch decoding process management unit 2 stores the reference table information stored in the reference table storage unit 5. And the process of updating the context to the state where LPS has occurred next is performed (step S33).

  The batch decoding process management unit 2 reads the current region width from the internal state information storage unit 3, and repeats the 1-bit normalization process while the current region width is below the normalization determination value (step S34).

  In step S31, when the above condition is not satisfied, the process proceeds to step S29.

  By performing the processing in this way, “MPS is n bits continuous” and “normalization does not occur after n bits decoding” and “MPS is n bits continuous”, but “normalization is not performed after n bits decoding” Perform batch decoding for each of the cases where "occurs" and "MPS continues for n-1 bits and then LPS occurs" but "normalization does not occur after n-1 bits decoding" Can do. As a result, the frequency of batch decoding is increased, so that the decoding process can be performed at high speed.

  As shown in FIG. 8, in the area width from the initial state (p) to n bits (t), the area width (t) after n-bit prefetching is equal to or smaller than the data series, and after n-1 bit prefetching If the area width (s) is larger than the data series and the area width (t) after n−1 bit prefetching is greater than or equal to the normalization judgment value, “MPS is n−1 bits continuous, then LPS is Occurs, and “normalization does not occur after n−1 bit decoding”, and in other cases, normalization occurs during n−1 bit decoding.

  If normalization occurs in the middle, the batch decoding process becomes complicated, so that the initial decoding is performed and then the sequential decoding process for each bit is performed from the beginning.

  As described above, according to the present invention, it is possible to perform batch decoding even when context switching occurs. As a result, the frequency of decoding a plurality of bits at a time increases, and the decoding process can be speeded up.

  Also, if normalization occurs when performing n-bit batch decoding, the frequency of decoding multiple bits at once increases by determining whether normalization occurred immediately after n-bit decoding or not. The decoding process can be speeded up.

It is a figure which shows the function structure of the arithmetic decoding apparatus of this invention. It is a flowchart which shows operation | movement of the arithmetic decoding apparatus in 1st Embodiment. It is a figure which shows transition of the area | region width to n bits (when MPS continues from 0 to n times). It is a figure which shows transition of the area width to n bits (when "MPS is n bits continuous" and "normalization does not occur after n bit decoding"). It is a flowchart which shows operation | movement of the arithmetic decoding apparatus in 2nd Embodiment. It is a figure which shows transition of the area | region width | variety to n bits (When "MPS is n bit contiguous", but normalization occurs after n bit decoding). It is a flowchart which shows operation | movement of the arithmetic decoding apparatus in 3rd Embodiment. It is a figure which shows transition of the area | region width | variety to n bits (When MPS continues n-1 bits and LPS occurs next and normalization does not occur after n-1 bit decoding). It is a figure which shows transition of the area | region width to n bits. It is a figure which shows the function structure of the conventional arithmetic decoding apparatus. It is a flowchart which shows operation | movement of the conventional arithmetic decoding apparatus. 10 is a flowchart showing the operation of the arithmetic decoding device in Patent Document 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Arithmetic decoding apparatus 2 Batch decoding process management part 3 Internal state information storage part 4 Initial internal state information saving part 5 Reference table storage part 6 Multi-bit batch decoding part 7 1-bit decoding part 101 Arithmetic decoding apparatus 102 Control part 103 Arithmetic Decoding unit 104 Internal state information storage unit 105 Reference table storage unit

Claims (2)

Arithmetic decoding that performs arithmetic decoding and outputs decoded data when a decoding request is supplied together with internal state information including at least the current region width, the previous region width, the data sequence to be decoded, and the context A device,
Internal state information storage means for storing the internal state information and a dominant symbol string which is a bit string of a dominant symbol from the first bit to the nth bit;
Initial internal state information saving means for storing the internal state information stored in the internal state information storage means when the decryption request is made;
Reference table storage means for storing table information necessary for updating the internal state information;
Based on the dominant symbol string, the decoded data consisting of n-bit consecutive dominant symbols is generated, output, or the decoded data consisting of 1-bit inferior symbols after the n-1 bit consecutive dominant symbols are generated, Multi-bit batch decoding means for outputting;
The initial internal state information recorded in the initial internal state information saving unit is sent to the internal state information storage unit, and the initial internal state information stored in the internal state information storage unit is used to set 1 bit. 1-bit decoding means for performing arithmetic decoding processing for each and generating and outputting the decoded data;
Whether batch decoding is possible is determined based on the current area width read from the internal state information storage means, the previous area width, and the data series to be decoded. If possible, batch decoding processing management for supplying the decoding request, a flag value for indicating a batch decoding method, a batch decoding bit number n, and the dominant symbol string to the multi-bit batch decoding means Means,
An arithmetic decoding device comprising: Arithmetic decoding that performs arithmetic decoding and outputs decoded data when a decoding request is supplied together with internal state information including at least the current region width, the previous region width, the data sequence to be decoded, and the context An arithmetic decoding program for causing a computer to function as a device,
The computer,
Internal state information storage means for storing the internal state information and a dominant symbol string which is a bit string of a dominant symbol from the first bit to the nth bit;
Initial internal state information saving means for storing the internal state information stored in the internal state information storage means when the decryption request is made;
Reference table storage means for storing table information necessary for updating the internal state information;
Based on the dominant symbol string, the decoded data consisting of n-bit consecutive dominant symbols is generated, output, or the decoded data consisting of 1-bit inferior symbols after the n-1 bit consecutive dominant symbols are generated, Multi-bit batch decoding means for outputting;
The initial internal state information recorded in the initial internal state information saving unit is sent to the internal state information storage unit, and the initial internal state information stored in the internal state information storage unit is used to set 1 bit. 1-bit decoding means for performing arithmetic decoding processing for each and generating and outputting the decoded data;
Whether batch decoding is possible is determined based on the current area width read from the internal state information storage means, the previous area width, and the data series to be decoded. If possible, batch decoding processing management for supplying the decoding request, a flag value for indicating a batch decoding method, a batch decoding bit number n, and the dominant symbol string to the multi-bit batch decoding means Means,
An arithmetic decoding program characterized by being made to function.

Images