RU2659492C1 - Unification unit with parallel comparison of terms - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering. Technical result is provided by a unit of unification with parallel comparison of terms containing internal working memory, inputs connected to an input data bus, and the output of the dispatch node, and the outputs are connected to the input of the variable matching node, the input of the predicate name matching node and the inputs of the term comparison nodes, the input control node is connected to the input control bus, the output of the variable matching node, the output of the predicate name matching node and the outputs of the term comparison nodes, the dispatching node, the inputs connected to the outputs of the term comparison nodes, and the outputs are connected to the input of the internal working memory and the inputs of the term comparison nodes, the node for mapping predicate names to the input is connected to the output of the internal working memory, and the output is connected to the input of the control node, the term comparison nodes whose inputs are connected to the outputs of the internal working memory and the outputs of the dispatching node, and the outputs are connected to the inputs of the control node, the inputs of the variable matching node and the inputs of the dispatching node, the variable-input matching unit connected to the outputs of the term-matching nodes and the output of the internal working memory.

EFFECT: shortening the time for unification of predicates.

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Description

The invention relates to computer technology, and in particular to devices for processing symbolic information, and is aimed at increasing the productivity and expanding the functionality of logical inference processors and systems based on knowledge that implements any method of logical inference.

The invention can be used in the design and development of specialized inference processors or as an independent device for conducting research on the analysis of the effectiveness of various methods of parallel unification.

Currently, in the field of computer systems and technologies, systems that solve knowledge processing tasks are becoming especially relevant. Presentation of knowledge about the selected subject area is, as a rule, a rather laborious task for interpretation on a computer, therefore, to work with such information, new semantic approaches to the extraction, presentation, storage and processing of information are necessary. The tasks of intellectual data and knowledge processing include: management of large enterprises, transport logistics, business analytics, medical and technical diagnostics, logical forecasting, etc. The number of the above tasks is growing steadily, and the computational aspect in them is being relegated to the background. That is why special logical programming languages were created, and there was also a demand for various kinds of expert systems and decision support systems. The main problem is that when implemented on computers, logical programming languages are used inefficiently, since they are designed to process symbolic information, and the programs written on them are translated into a set of microcommands for execution on serial universal processors, designed primarily for processing numerical data.

The solution to these problems can be hardware support of specialized inference machines, which form the basis of any intelligent knowledge processing system.

In the process of inference, one of the most common operations on symbolic data is the operation of unification of predicates. The generalized structure of an abstract logical inference machine is known, as well as data formats and structures [Meltsov V.Yu. High-performance systems of deductive i nference: Monograph. Yelm, WA, USA: Science Book Publishing House, 2014 .-- 216 p., P. 101, 124-132].

From the source [Vishnyakov, V.A., Hardware and software of logical inference processors [Text] / V.A. Vishnyakov, D.Yu. Boulanger, O.V. Hermann. - M .: Radio and communications, 1991 .-- 264 p., P. 136-139] a unification processor is known that implements the following unification stages: the stage of checking the equality of names of unified structures, the stage of calculating the argument of unified structures, the stage of transition to the next processed arguments, the stage of dereference of a variable, the stage of dereference of an argument, the stages of writing to stacks, the read operations from unified stack; creating lookups. This unification processor has the following elements: a block of general purpose registers, which includes: registers of unified arguments, storage registers for the maximum upper value of the global, local and trail stacks, registers for storing current addresses in stacks, registers for storing vectors of variables included in the skeletons of unified structures , a register for storing a pointer to a unified stack, a register for storing a pointer to a pair of unified arguments, an address register for a tagged value read from memory and registers unifitsiruemyh arguments. Also, the specified unification processor includes: comparators, adder, status register, ROM, input buffer registers, control device, input and output data buses, input address bus, input command bus, write gating bus and status bus. This device has the following disadvantages. Firstly, a considerable time of unification due to the consistent comparison of terms. Secondly, the processed data is stored each time in the external memory for the unification unit, which significantly increases the unification time if it is necessary to access it again in the unification process. Thirdly, the use of compressed data formats, such as a molecule, although it slightly reduces the amount of memory required for storage, however, it makes it necessary to unpack the structure each time when unifying such terms, which complicates the design of the processor. Fourthly, the operation of variable desensing is carried out each time in the process of comparing two arguments-variables, which leads to the need to carry out it repeatedly for the same global variable and, accordingly, a significant increase in unification time.

From the source [RU No. 158945 (Ul), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification unit with sequential matching of terms] a unit of unification with sequential matching of terms is known. This unification block contains: a control device, working memory, multiplexers for selecting the source of loading the operand into registers, registers for storing operands, address management counters for the first and second ports of the working memory block, operand tag decoders, a comparator for comparing term names, a memory address management counter lookups, lookup memory, counter recovery counter register, comparator for comparing lookup memory address values and stored address. This unit of unification has the following disadvantages. Firstly, a considerable time of unification due to the consistent comparison of terms. Secondly, in order to take into account the possible replacement of the thermal variable made by comparing the previous arguments, additional hardware (register, counter, decoder) and considerable time are required to search for existing substitutions and restore the address counter value. Thirdly, there is no possibility of accounting for the permutations made before the currently unified command.

From the source [Application for invention No. 2016120823 from 05.26.2016. IPC G06N 5/04. Unification block with parallel term matching. Authors: Meltsov V.Yu., Kuvaev AS, Chistyakov GA, Shipitsyna AA] A unit of unification with parallel matching of terms is known. This block contains: internal working memory, control node, dispatch node, predicate name matching node, term matching nodes, permutation formation node. This unit of unification has the following drawback: there is no possibility of correct unification of predicates if one of the predicates has more than two pairs of the same free variables specified in the process of matching with different constants. A free (or non-specific) variable is a variable that has not yet received a value. A variable that has received some value and turned out to be associated with a particular object is called related or concretized. An example demonstrating a similar situation is shown in figure 8 (in the device [Application for invention No. 2016120823 dated 05/26/2016. IPC G06N 5/04. Unification unit with parallel term comparison. Authors: Meltsov V.Yu., Kuvaev AS , Chistyakov GA, Shipitsyna AA] there is no way to perform several steps 2 in the third stage). It should be noted that the increasing use of parallel inference methods in areas such as the management of large enterprises, medical and technical diagnostics, multi-criteria logical forecasting, makes it necessary to use predicates with 15-20 or more arguments, while the probability of the situation described above increases markedly.

The technical result achieved by using the present invention is to reduce the time of unification of predicates with great arity, as well as to add the option of unifying a pair of predicates, if one of them has more than two pairs of the same free variables, specified in the process of comparison with different constants. This result is achieved through the development and inclusion in the unification block of a set of separate, functionally complete nodes for comparing terms and a node for matching variables, which is necessary for matching concrete variables and generating final substitutions.

The introduction of several comparison nodes allows you to compare all terms in parallel and reduce the influence of predicate arity on the duration of the unification operation. The functionality has been implemented to change the number of matching nodes, taking into account the features of the data available in the knowledge base of the inference machine (arity of predicates, number of predicates in the initial premises, etc.). Due to the regular structure, the device can be easily implemented on the basis of a programmable logic integrated circuit (FPGA) or custom VLSI.

The technical problem to which the invention is directed is the development of a device that significantly reduces the time for predicate unification compared to serial devices due to the parallel implementation of the operation of matching all pairs of terms, as well as the ability (resources) to unify predicates when there are more than one predicate two pairs of the same free variables, specified in the process of comparison by different constants. The presented provisions are ensured by the use of special formats for unified predicates and their arguments, the introduction of specialized jointly working units for comparing terms, and also the unit for matching variables into the unit of unification. The peculiarity of the representation of the processed data is the use of tags: 1111 - predicate, 0001 - constant, 0010 - variable of the source rule (the original premise-clause), 0011 - variable of the displayed rule (target statement, request), as well as unique numbers (addresses) of the symbol table for unambiguous identification of processed terms. The tag field is taken with a dimension of 4 bits to further expand the number of data types being compared, for example, by introducing functors and lists. The name table is stored in external shared memory.

A block diagram of a unification unit with parallel term matching is shown in Figure 1. The device comprises:

1 - internal working memory of the unification unit (GRP);

2 - unidirectional communication line for loading unified predicates from external memory via the input data bus;

3 - unidirectional communication line with an external control device to start the unification operation on the input control bus;

4 - control unit (UE);

5 - scheduling node (UD);

6 - unidirectional communication line for controlling reading from the internal working memory;

7 - unidirectional communication line for transmitting predicate names;

8 - predicate name matching node;

9 - unidirectional communication line for transmitting the results of matching predicate names;

10 - unidirectional communication line for transmitting terms;

11 - unidirectional communication line for transmitting terms;

12 - the first node of the comparison of terms (TSI);

13 - last TSI;

14 - unidirectional communication line for transmitting variables;

15 - node coordination of variables (USP);

16 - bidirectional communication line for the management of TSI;

17 - bidirectional communication line for the management of TSI;

18 - unidirectional communication line for transmitting the results of the comparison of terms;

19 is a unidirectional communication line for transmitting the results of the comparison of terms;

20 - unidirectional communication line for transmitting substitutions from TSI;

21 - unidirectional communication line for transmitting substitutions from TSI;

22 - unidirectional communication line for transmitting the result of the operation of matching variables in the control node;

23 - unidirectional communication line for outputting the result of unification to the output control bus;

24 - unidirectional communication line for issuing the resulting substitutions on the output data bus.

In the unification block, it is possible to change the number of terms matching nodes, which allows parallel matching of all terms and thereby significantly reduces the time spent on standardizing predicates compared to the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification block with sequential matching of terms].

The predicate name matching node is selected as a separate specialized element, since its structure is much simpler than TSI, and there is no need to form variable substitutions.

The internal structure of the variable matching node (15) is shown in figure 2. It contains:

20 - unidirectional communication line for transmitting substitutions from TSI;

21 - unidirectional communication line for transmitting substitutions from TSI;

14 - unidirectional communication line for transmitting variables;

25 - node consistency check variables (UPS);

26 is a bi-directional communication line for transmitting instantiations of negotiable variables;

27 is a bi-directional communication line for conveying instantiation: negotiable variables;

28 - site storage substitutions (UHP);

29 - unidirectional communication line for transmitting the result of matching a pair of variables;

30 - unidirectional communication line for transmitting the result of matching a pair of variables;

40 - node generating errors in the coordination of all variables (UFO);

22 - unidirectional communication line for transmitting the result of the operation of matching variables in the control node;

24 - unidirectional communication line for issuing the resulting substitutions on the output data bus.

The node for checking the consistency of variables is a multistage combinational circuit for comparing constants that specify the variables of the same name of the original and output rules. The number of cascades is determined by the formula n / 2-1, where n is the maximum permissible arity of predicates.

The associative memory-based substitution storage node is necessary not only for storing the substitutions received during the execution of the current unification command, but also for storing the substitutions received earlier in the processing of the previous unification commands for the predicates of the selected clause sending (source rule) and the target conclusion (deduced rule ) This allows us to carry out the operation of unification of all terms taking into account previously accepted replacements (concretizations) of variables, without spending extra time on dereference and coordination of variables, which is very significant if the concretization of variables is stored in external memory.

The error generating unit generates a signal about the unsuccessful completion of the variable matching procedure if for the same variable at least once there are different constant values specifying this variable.

Description of the operation of the unit of unification of two predicates Variables (non-specific variables), named constants (atoms), and numerical constants can serve as arguments (attributes, terms) of predicates. Constant names always begin with an uppercase letter, and variable names with an uppercase one. The predicate name is all uppercase letters.

- переменная выводимого правила). С учетом введенных тэгов (см. выше), структура первого предиката будет занимать первые пять ячеек рабочей памяти (фигура 4, ячейки с адреса 000 по 007), второй предикат - ячейки с 008 по 015. По правилам, введенным в теории логического программирования, предикаты с одинаковым именем, всегда должны иметь одинаковую арность (количество термов).Consider an example of organizing a name table (figure 3) and internal working memory (figure 4) for the unification command for the two predicates CAR (Lada Vesta, x, y, z, z, Red, x) and CAR (u, v, 43, к785ne, k875ne, Red, Ivanov). The predicate CAR has seven terms: car model, name of owner, code of the region of registration of the car, front state registration number, rear state registration number, color of the car and surname of the driver (currently driving). In this example, the first predicate characterizes the silver Lada Vesta car, and the owner, region code and state numbers are set by the variables x, y and z, respectively, which can be specified in the future. For the second predicate, the following are known: the region code, the number and color of the car, the name of the driver, and the owner and model of the car are not defined - the variables u and v can be specified later (

- variable of the displayed rule). Based on the entered tags (see above), the structure of the first predicate will occupy the first five cells of working memory (Figure 4, cells from addresses 000 to 007), the second predicate will occupy cells from 008 to 015. According to the rules introduced in the theory of logical programming, predicates with the same name must always have the same arity (number of terms).

Consider an example of organizing a lookup table in the USP (figure 5). At first (columns 3 and 4) the tag and number of the variable to be replaced are indicated, and at the end (columns 5 and 6) - the new value of the variable.

The algorithm for performing an operation parallel to the unification of the terms of two predicates on the claimed device consists of the following steps (see figure 1).

Stage 0. Two predicates are loaded into the internal working memory 1 via the communication line 2 - complex-structured groups of tagged data. On the communication line 3 to the control unit 4 receives a signal about the start of the operation of unification.

Stage 1. Node scheduling 5 on the communication line 6 sends a command to read from the internal working memory 1:

- names of predicates on the communication line 7 to the node matching the names of predicates 8;

- predicate terms (first, second, third, ..., etc.) in pairs along the communication lines 10 and 11 to the nodes of the comparison of terms 12 and 13, respectively.

Stage 2. On the matching nodes 8, 12-13, a parallel asynchronous procedure for matching the specified arguments is performed.

If the names of the predicates do not match, then from the mapping node 8 via the communication line 9 to the control node 4 receives a signal - "0". Otherwise, the signal "1".

When matching terms, the following situations are possible:

- if a pair of "constant-constant" is unified and the names of the constants do not match, then from the mapping node 12 (13) via the communication line 18 (19) to the control node 4 receives the signal "0". Otherwise, the signal "1";

- if the variable-constant pair (or “constant-variable”) is unified, then from the mapping node 12 (13) via the communication line 18 (19), the signal “1” arrives at the control node 4, and the variable matching node 15 receives communication lines 20 (21) - a variable substitution formed when matching terms;

- if the pair “variable-variable” is unified, and one of them is a variable of the displayed rule, then from the mapping node 12 (13) via the communication line 18 (19) the signal “1” is sent to the control node 4, and to the variable matching node 15 on the communication line 20 (21) - a substitution formed during the comparison of terms (the variable of the displayed rule is a “replaceable variable”).

An example of the organization of the lookup table after the second stage of unification of the above predicates CAR is shown in figure 5.

If, as a result of matching the names of predicates or any pair of terms, at least one “0” is received in the control unit 4, then the unification operation is stopped and a signal (“0”) is issued on the communication line 23 indicating the operation was unsuccessful.

Stage 3. If, as a result of matching the names of predicates and all pairs of terms, the signals “1” are received in the control node 4, then the procedure for matching the specified variables is performed in the variable matching node 15, consisting of the following steps:

- step 1. All instantiations of the variables of the same name are compared with constants (see figure 5, the columns "Replaceable variable" and "New value"). If in the column "New value" at least once there are different constant values for the same variable, then to the control unit 4 via communication line 22 a signal "0" is sent about the failure of the variable matching procedure. If all records are instantiated with the same constant, then in the associative memory of the substitutions there is only one (first) record about replacing this variable with the corresponding constant, and the rest of the records are deleted.

- step 2. In all the “variable-variable” pairs, the arguments - the variables are replaced with the corresponding constants in the other concretization entries. Moreover, if in the pair only the variable of the displayed rule is replaced with a constant (the column “Replaceable variable”), and the variable of the original rule is not (the column “New value”), then the cells (the contents of the cells) in the columns “Replaceable variable” and “New value” such records are reversed.

If for any record in the columns “Replaceable Variable” and “New Value” there are two constants with different values (names), then a signal “0” is sent to control node 4 via communication line 22 about the unsuccessful completion of the variable matching procedure. Records with two identical constants are deleted to reduce the amount of information stored in the lookup table.

In the process of unifying predicates with a large number of pairs of variables of the same name, it may be necessary to perform several similar steps. Worst case, i.e. the greatest number of steps 2 at the third stage of matching two n-local predicates can be obtained if there are n / 2 pairs of homonymous free variables in one predicate and (n / 2-l) pairs of homogeneous free variables in the other predicate. The number of steps 2 in this case will be equal to (n / 2-l).

- step 3. All instantiations of the variables of the same name are compared with constants (see figure 5, the columns “Replaceable variable” and “New value”). If in the column "New value" at least once there are different values of constants, then to the control unit 4 via communication line 22 a signal "0" is sent about the unsuccessful completion of the procedure for matching variables. If all records are specified by the same constant, then in the associative memory of the substitutions there is only one (first) record about replacing this variable with the corresponding constant, and the rest of the records are deleted, and a signal “1” is sent to control node 4 via communication line 22 about successful completion of the variable matching procedure.

Stage 4. If the procedure for reconciling the specified variables failed (a signal “0” was received from the node for coordinating the variables 15 via the communication line 22), then the control unit 4 sends a “0” signal via the communication line 23, which means that it is impossible to unify the analyzed pair of predicates. If the procedure for reconciling the specified variables was completed successfully (the signal “1” was received from the node for reconciling the variables 15 via the communication line 22), the control unit 4 via the communication line 23 issues a “1” signal, which indicates the successful completion of the unification operation of the pair of predicates. In this case, from the coordination node of the variables 15 via the communication line 24, replacements are made of all variables obtained by unifying the specified pair of predicates.

Example 1 (Fig. 6) demonstrates the case of successful completion of the procedure for matching variables - all pairs are marked (1), and the unification of predicates as a whole. Signal “1” is sent to control unit 4 from the substitution formation unit. Concretization of variables (substitutions) were obtained at stage 3, step 1.

Example 2 (Fig. 7) demonstrates the case of unsuccessful completion of the procedure for matching variables in the third step of the third stage and the unification of predicates in general. Step 2 of the third stage is enough to perform once.

Example 3 (Fig. 8) demonstrates the case of unsuccessful completion of the procedure of matching variables in the third step of the third stage and the unification of predicates in general. However, the second step of the third stage must be performed twice, which is not provided by the functioning algorithm (and resources) of the device [4].

Example 4 (Fig. 9) demonstrates the case of an unsuccessful completion of the variable matching procedure in the third step of the third stage. However, the second step of the third stage must be performed three times, which is also not provided for by the functioning algorithm (and resources) of the device [4].

The minimum performance increase of the claimed device can be estimated as follows. We assume that the unified predicates are loaded into the internal memory in advance and the time is counted from the moment the trigger signal arrives (i.e., without taking stage 0 into account). The execution time of steps 1, 2, 4, as well as each step of step 3 (it will be required only if there is at least one variable in the pair of terms to be compared) will be called the device operation cycle.

For comparison, take the device [RU No. 158945 (Ul), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification block with sequential comparison of terms] and [4]. Steps 1, 2, and 4 on them are also performed in one cycle each. In the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification unit with sequential comparison of terms] to search for and possibly coordinate (de-reference) a variable in the substitution memory, 6 cycles (if necessary, matching) or 4 cycles (if there are no substitutions in the memory for previous instantiations of the analyzed variable) will be required. Thus, the minimum possible unification time will be 3 cycles - if constants with different names (values) are used as the very first terms in the unified pair of predicates. In the device [4] and the claimed device, this time is also equal to 3 clock cycles.

In the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification unit with sequential comparison of terms] unification for example 1 (Fig. 6) will be performed in 45 cycles: reading predicate names (1 cycle); matching predicate names (1 measure); reading the first pair of arguments (1 clock); matching the first pair of arguments (1 clock); reading the second pair of arguments (1 clock); matching the second pair of arguments (1 clock); attempt to match the variable v (4 measures); attempt to reconcile variable x (4 measures); reading the third pair of arguments (1 clock); matching the third pair of arguments (1 clock); an attempt to coordinate the variable y (4 measures); reading the fourth pair of arguments (1 clock); comparison of the fourth pair of arguments - (1 clock cycle); attempt to match the variable z (4 measures); reading the fifth pair of arguments (1 clock); matching the fifth pair of arguments (1 clock); matching the variable z - (6 measures); reading the sixth pair of arguments (1 clock); matching the sixth pair of arguments (1 clock); reading the seventh pair of arguments (1 clock); matching the seventh pair of arguments (1 clock); coordination of the variable x (6 measures); delivery of results (1 step).

In the device [Application for invention No. 2016120823 dated 05/26/2016. IPC G06N 5/04. Unification block with parallel term matching. Authors: Meltsov V.Yu., Kuvaev AS, Chistyakov GA, Shipitsyna AA] - for 4 measures (Stage 1; Stage 2; Stage 3_step 1; Stage 4).

In the inventive device - also for 4 cycles (Stage 1; Stage 2; Stage 3_step1; Stage 4).

In the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification unit with sequential comparison of terms] unification for example 2 (Fig. 7) will be performed in 32 measures: reading the names of predicates (1 measure); matching predicate names (1 measure); reading the first pair of arguments (1 clock); matching the first pair of arguments (1 clock); reading the second pair of arguments (1 clock); attempt to reconcile variable x (4 measures); attempt to match the variable t (4 measures); reading the third pair of arguments (1 clock); matching the third pair of arguments (1 clock); attempt to reconcile variable x (4 measures); attempt to match the variable s (4 measures); reading the fourth pair of arguments (1 clock); matching the fourth pair of arguments (1 clock); matching s variable (6 measures); delivery of results (1 step).

In the device [Application for invention No. 2016120823 dated 05/26/2016. IPC G06N 5/04. Unification block with parallel term matching. Authors: Meltsov V.Yu., Kuvaev A.S., Chistyakov G.A., Shipitsyna A.A.] - for 6 cycles (Stage 1; Stage 2; Stage 3_step 1; Stage 3_step 2; Stage 3_step 3; Stage four).

In the inventive device, also for 6 clock cycles (Stage 1; Stage 2; Stage 3_step 1; Stage 3_step 2; Stage 3_step 3; Stage 4).

In the device [RU No. 158945 (Ul), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification unit with sequential comparison of terms] unification for example 3 (Fig. 8) will be performed in 52 measures: reading the names of predicates (1 measure); matching predicate names (1 measure); reading the first pair of arguments (1 clock); matching the first pair of arguments (1 clock); reading the second pair of arguments (1 clock); attempt to reconcile variable x (4 measures); attempt to match the variable t (4 measures); reading the third pair of arguments (1 clock); matching the third pair of arguments (1 clock); attempt to reconcile variable x (4 measures); attempt to reconcile the variable u (4 measures); reading the fourth pair of arguments (1 clock); matching the fourth pair of arguments (1 clock); an attempt to reconcile the variable y (4 measures); attempt to reconcile the variable u (4 measures); reading the fifth pair of arguments (1 clock); matching the fifth pair of arguments (1 clock); an attempt to reconcile the variable y (4 measures); attempt to match the variable s (4 measures); reading the sixth pair of arguments (1 clock); matching the sixth pair of arguments (1 clock); matching s variable (6 measures); delivery of results (1 step).

In the device [Application for invention No. 2016120823 dated 05/26/2016. IPC G06N 5/04. Unification block with parallel term matching. Authors: Meltsov V.Yu., Kuvaev AS, Chistyakov GA, Shipitsyna AA] - there is no possibility of complete coordination of variables and, accordingly, correct unification of predicates.

In the inventive device - for 7 clock cycles (Stage 1; Stage 2; Stage 3_step 1; Stage 3_step 2.1; Stage 3_step 2.2; Stage 3_step 2.3; Stage 3_step 3; Stage 4).

In the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification unit with sequential comparison of terms] unification for example 4 (Fig. 9) will be performed in 72 measures: reading predicate names (1 measure); matching predicate names (1 measure); reading the first pair of arguments (1 clock); matching the first pair of arguments (1 clock); reading the second pair of arguments (1 clock); attempt to reconcile variable x (4 measures); attempt to match the variable t (4 measures); reading the third pair of arguments (1 clock); matching the third pair of arguments (1 clock); attempt to reconcile variable x (4 measures); attempt to reconcile the variable u (4 measures); reading the fourth pair of arguments (1 clock); matching the fourth pair of arguments (1 clock); attempt to match the variable z (4 measures); attempt to reconcile the variable u (4 measures); reading the fifth pair of arguments (1 clock); matching the fifth pair of arguments (1 clock); attempt to match the variable z (4 measures); attempt to match the variable v (4 measures); reading the sixth pair of arguments (1 clock); matching the sixth pair of arguments (1 clock); Attempting to match the variable y (4 measures); attempt to match the variable v (4 measures); reading the seventh pair of arguments (1 clock); matching the seventh pair of arguments (1 clock); an attempt to reconcile the variable y (4 measures); attempt to match the variable s (4 measures); reading the eighth pair of arguments (1 clock); matching the eighth pair of arguments (1 clock); matching s variable (6 measures); delivery of results (1 step).

In the device [Application for invention No. 2016120823 dated 05/26/2016. IPC G06N 5/04. Unification block with parallel term matching. Authors: Meltsov V.Yu., Kuvaev AS, Chistyakov GA, Shipitsyna AA] - there is no possibility of complete coordination of variables and, accordingly, correct unification of predicates.

In the inventive device - for 8 clock cycles (Stage 1; Stage 2; Stage 3_step 1; Stage 3_step 2.1; Stage 3_step 2.2; Stage 3_step 2.3; Stage 3_step 3; Stage 4).

All comparisons are given for the case when the previous variable substitutions are in the internal memory of the unification block. For the inventive device, this condition is always satisfied. For the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification unit with sequential matching of terms] in the internal memory, only the substitutions performed during the unification of the current pair of predicates of the processed clause rules are stored. The remaining instantiations are stored in external memory.

Based on the foregoing, it can be argued that the inventive device significantly reduces the time of unification compared to serial devices, which will allow to achieve significant superiority in performance of specialized logical output processors developed on its basis over existing analogs. In addition, in the claimed device it is possible to compare pairs of predicates, even if in one of the predicates there are more than two pairs of the same free variables, specified in the process of comparison by different constants, which distinguishes it from the device [Application for invention No. 2016120823 from 05.26.2016. IPC G06N 5/04. Unification block with parallel term matching. Authors: Meltsov V.Yu., Kuvaev A.S., Chistyakov G.A., Shipitsyna A.A.].

Preliminary estimates of the hardware implementation of the claimed device on the budget Altera Cyclone III FPGA indicate the free placement of more than 100 matching nodes on a chip in one unification block, which makes it possible to parallelly compare all arguments of processed predicates at the same time.

Claims (1)

A unification unit with parallel term matching containing internal working memory, the inputs of which are connected to the input data bus and the output of the dispatch node, and the outputs are connected to the input of the variable mapping node, the input of the predicate name matching node and the inputs of the term matching nodes, the control node whose inputs are connected with an input control bus, the output of the variable mapping node, the output of the predicate name matching node and the outputs of the term matching nodes, the dispatch node, whose inputs are connected to the outputs of the term matching nodes, and the outputs are connected to the input of the internal working memory and the inputs of the term matching nodes, the predicate name matching node, the input of which is connected to the output of the internal working memory, and the output is connected to the input of the control node, the term matching nodes, the inputs of which are connected with the outputs of the internal working memory and the outputs of the scheduling node, and the outputs are connected to the inputs of the control node, the inputs of the variable matching node and the inputs of the scheduling node, characterized in that up to olnitelno comprises variable matching unit having inputs connected to outputs of terms and the output matching internal working memory nodes and outputs connected to control input node and an output data bus.

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