RU2631158C1 - Unification unit with parallel therm matching - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: unification unit with parallel therm matching is used, which contains internal working memory, one of the inputs of which is connected to the input data bus, a control node, one of the inputs of which is connected to the input control bus. The predicate name matching node, the input of which is connected to one of the internal working memory outputs and the output is connected to one of the control node inputs, therm matching nodes, the inputs of which are connected to the internal working memory outputs and the dispatching node outputs, and the outputs are connected to the control node inputs, the inputs of the substitution generating node and the inputs of the dispatching node, the dispatching node, the inputs of which are connected to the outputs of the therm matching nodes, and the outputs are connected to one of the internal working memory inputs and the inputs of the therm matching nodes, the inputs of which are connected to the outputs of the therm matching nodes and one of the outputs of the internal working memory, and the outputs are connected to one of the control node inputs and the output data bus.

EFFECT: reducing the time for the unification of predicates.

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Description

The invention relates to computing, and in particular to devices for processing symbolic information, and is aimed at increasing the performance of logical inference processors and systems based on knowledge that implements any method of logical inference.

The invention can be used in the design of specialized inference processors or as an independent device for conducting research on the analysis of the effectiveness of various methods of parallel unification.

Currently, in the field of computer systems and technologies, systems that solve knowledge processing tasks are becoming especially relevant. Presentation of knowledge about the selected subject area is, as a rule, a rather laborious task for interpretation on a computer, therefore, to work with such information, new semantic approaches to the extraction, presentation, storage and processing of information are necessary. The tasks of intellectual data and knowledge processing include: management of large enterprises, transport logistics, business analytics, medical and technical diagnostics, logical forecasting, etc. The number of the above tasks is growing steadily, and the computational aspect in them is being relegated to the background. That is why special logical programming languages were created, and there was also a demand for various kinds of expert systems and decision support systems. The main problem is that when implemented on computers, logical programming languages are used inefficiently, since they are designed to process symbolic information, and the programs written on them are translated into a set of microcommands for execution on serial universal processors with von Neumann architecture, designed primarily , to process numerical data.

The solution to these problems can be hardware support of specialized inference machines, which form the basis of any intelligent knowledge processing system.

In the process of inference, one of the most common operations on symbolic data is the operation of unification of predicates. The generalized structure of an abstract inference machine, as well as data formats and structures, were taken from [Meltsov V. Yu. High-performance systems of deductive inference: Monograph. - Yelm, WA, USA: Science Book Publishing House, 2014. - 216 p., P. 101, 124-132].

From the source [Vishnyakov, V.A. Hardware-software means of logical inference processors [Text] / V.A. Vishnyakov, D.Yu. Boulanger, O.V. Hermann. - M .: Radio and communications, 1991, 264 pp., Pp. 136-139] there is a unification processor that implements the following unification stages: the stage of checking the equality of names of unified structures, the stage of calculating the argument of unified structures, the stage of transition to the following processed arguments, variable dereference stage, argument dereference stage, stack writing steps, read operations from the unified stack, creating substitutions. This unification processor has the following elements: a block of general purpose registers, which includes: registers of unified arguments, storage registers for the maximum upper value of the global, local and trail stacks, registers for storing current addresses in stacks, registers for storing vectors of variables included in the skeletons of unified structures, unified stack pointer storage register, unified argument pair register storage register, tagged address address register read from memory and into registers of unified arguments. Also, the specified unification processor includes: comparators, adder, status register, ROM, input buffer registers, control device, input and output data buses, input address bus, input command bus, write gating bus and status bus. This device has the following disadvantages. Firstly, a considerable time of unification due to the consistent comparison of terms. Secondly, the processed data is stored each time in the external memory for the unification unit, which significantly increases the unification time if it is necessary to access it again in the unification process. Thirdly, the use of compressed data formats, such as a molecule, although it slightly reduces the amount of memory required for storage, however, it makes it necessary to unpack the structure each time when unifying such terms, which complicates the design of the processor. Fourth, the operation of de-referencing variables is carried out each time in the process of comparing two arguments-variables, which leads to the need to carry out it repeatedly for the same global variable and, accordingly, a significant increase in unification time.

From the source [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification unit with sequential matching of terms] a unit of unification with sequential matching of terms is known. This unification block contains: a control device, working memory, multiplexers for selecting the source of loading the operand into registers, registers for storing operands, address management counters for the first and second ports of the working memory block, operand tag decoders, a comparator for comparing term names, a memory address management counter lookups, lookup memory, counter recovery counter register, comparator for comparing lookup memory address values and stored address. This unit of unification has the following disadvantages. Firstly, a considerable time of unification due to the consistent comparison of terms. Secondly, to take into account the possible replacement of the term variable made by comparing the previous arguments, additional hardware (register, counter, decoder) and considerable time are required to search for existing substitutions and restore the value of the address counter. Thirdly, there is no possibility of accounting for the permutations made before the currently unified command.

The technical problem to which the invention is directed is the development of a device that significantly reduces the time for predicate unification due to the parallel implementation of the unification operation, at the same time taking into account all the permutations made when comparing the terms of the unified predicates, as well as accounting for the permutations made in the previous stages of the logical conclusion.

The presented provisions are ensured by the use of special formats for unified predicates and their arguments, the introduction of a dispatch node, a predicate name matching node, a substitution generation node necessary to coordinate specific variables, and specialized jointly working terms matching terms as part of the unification block. The peculiarity of the representation of the processed data is the use of tags: 1111 - predicate, 0001 - constant, 0010 - variable of the source rule (the original premise-clause), 0011 - variable of the displayed rule (target statement, request), as well as unique numbers (addresses) of the symbol table for unambiguous identification of processed terms. The tag field is taken in a 4-bit dimension to further expand the number of data types being compared, for example, by introducing functors and lists. The name table is stored in external shared memory.

The introduction of matching nodes allows you to compare all terms in parallel and reduce the effect of predicate arity on the duration of the unification operation. In addition, the functionality was implemented to change the number of matching nodes, taking into account the features of the data available in the knowledge base of the logical inference engine (arity of predicates, number of predicates in the initial premises, etc.). Due to the regular structure, the device can be easily implemented on the basis of a programmable logic integrated circuit (FPGA) or custom VLSI.

A block diagram of a unification unit with parallel term matching is shown in Figure 1.

The device contains the following:

1 - internal working memory of the unification unit (GRP);

2 - unidirectional communication line for loading unified predicates from external memory via the input data bus;

3 - unidirectional communication line with an external control device to start the unification operation on the input control bus;

4 - control unit (UE);

5 - scheduling node (UD);

6 - unidirectional communication line for controlling reading from the internal working memory;

7 - unidirectional communication line for transmitting predicate names;

8 - predicate name matching node;

9 - unidirectional communication line for transmitting the results of matching predicate names;

10 - unidirectional communication line for transmitting terms;

11 - unidirectional communication line for transmitting terms;

12 - the first node of the comparison of terms (TSI);

13 - last TSI;

14 - unidirectional communication line for transmitting variables;

15 - node formation of substitutions (UVP)

16 - bidirectional communication line for the management of TSI;

17 - bidirectional communication line for the management of TSI;

18 - unidirectional communication line for transmitting the results of the comparison of terms;

20 - unidirectional communication line for transmitting substitutions;

21 - unidirectional communication line for transmitting substitutions;

22 - unidirectional communication line for transmitting the result of the operation of matching variables;

23 - unidirectional communication line for outputting the result of unification to the output control bus;

22 - unidirectional communication line for issuing the resulting substitutions on the output data bus.

The nodes of the term comparison (12-13) are introduced into the structure of the unification block and the possibility of changing their number is provided, which allows parallel terms to be implemented by matching and thereby significantly reduce the time spent on unification as a whole. The presence of the dispatch node (5) allows you to balance the load of the term mapping nodes during the unification procedure, reducing their downtime. In addition, the possibility of varying the number of TSIs allows you to choose the configuration of the unification block that most effectively implements the processing of input data structures for a specific user task.

The predicate name matching node is selected as a separate specialized element, since its structure is much simpler than TSI, and there is no need to form variable substitutions.

The substitution generation node (15) contains associative memory, which is necessary not only for storing the substitutions received during the execution of the current unification command, but also for storing the substitutions received earlier in the processing of the previous unification commands for the predicates of the selected clause sending (the original rule ) and the conclusion (target rule). This allows us to carry out the operation of unification of terms taking into account previously accepted substitutions (concretizations) of variables without spending extra time on coordinating substitutions and dereference of variables, which is very significant if the concretization of variables is stored in external memory.

Description of the unification block of two predicates

Variables (non-specific variables), named constants (atoms), and numerical constants can serve as arguments (attributes, terms) of predicates. Constant names always begin with an uppercase letter, and variable names with an uppercase one. The predicate name is all uppercase letters.

Consider an example of organizing a name table (figure 2) and internal working memory (figure 3) for the unification command for the two predicates CAR (Lada_vesta, x, y, z, z, Silver, x) and CAR (u, v, 43, к785ne, к875not , Silver, Ivanov). The predicate CAR has seven terms: car model, name of owner, code of the region of registration of the car, front state registration number, rear state registration number, color of the car and surname of the driver (currently driving). In this example, the first predicate characterizes the silver Lada Vesta car, and the owner, region code and state numbers are set by x, y and z variables, respectively, which can be specified later (the variable `is a variable of the displayed rule). For the second predicate, the following are known: the region code, the number and color of the car, the name of the driver, and the owner and model of the car are not defined. Based on the entered tags (see above), the structure of the first predicate will occupy the first five cells of working memory (Figure 3, cells from addresses 000 to 007), the second predicate will occupy cells from 008 to 015. According to the rules introduced in the theory of logical programming, predicates with the same name must always have the same arity (number of terms).

Consider an example of organizing a lookup table in UVP (figure 4). At first (columns 3 and 4) the tag and number of the variable to be replaced are indicated, and at the end (columns 5 and 6) - the new value of the variable.

The algorithm for performing the operation of parallel unification of the terms of two predicates on the claimed device consists of the following steps.

Stage 0. Two predicates are loaded into the internal working memory 1 via the communication line 2 - complex-structured structures of tagged data. On the communication line 3 to the control unit 4 receives a signal about the start of the operation of unification.

Stage 1. Node scheduling 5 on the communication line 6 sends a command to read from the internal working memory 1:

- names of predicates on the communication line 7 to the node matching the names of predicates 8;

- predicate terms (first, second, third, ..., etc.) in pairs along the communication lines 10 and 11 to the nodes of the comparison of terms 12 and 13, respectively.

Stage 2. On the matching nodes 8, 12-13, a parallel asynchronous procedure for matching the specified arguments is performed.

If the names of the predicates do not match, then from the mapping node 8 via the communication line 9 to the control node 4 receives a signal - "0". Otherwise, the signal "1".

When matching terms, the following situations are possible:

- if a pair of "constant - constant" is unified and the names of the constants do not match, then from the mapping node 12 (13) via the communication line 18 (19) to the control node 4 receives the signal "0". Otherwise, the signal "1";

- if the pair “variable - constant” (or “constant - variable”) is unified, then from the mapping node 12 (13), via the communication line 18 (19), the signal “1” is sent to the control node 4, and to the substitution formation node 15 by communication lines 20 (21) - a variable substitution formed when matching terms;

- if the pair “variable - variable” is unified, and one of them is a variable of the displayed rule, then from the mapping node 12 (13) via the communication line 18 (19), the signal “1” is sent to the control node 4, and to the substitution formation node 15 on the communication line 20 (21) - a substitution formed during the comparison of terms (the variable of the displayed rule is a “replaceable variable”).

An example of the organization of the lookup table after the second stage of unification of the above predicates CAR is shown in figure 4.

If, as a result of matching the names of predicates or any pair of terms, at least one “0” is received in the control unit 4, then the unification operation is stopped and a signal (“0”) is issued on the communication line 23 indicating that the operation was unsuccessful.

Stage 3. If, as a result of matching the names of predicates and all pairs of terms, the signals “1” are received in the control node 4, then the procedure for matching the specified variables is performed in the node of substitution generation 15, consisting of the following steps:

- step 1. All instantiations of the variables of the same name are compared by constants (see figure 4, the columns "Replaceable variable" and "New value"). If in the column "New value" at least once there are different constant values for the same variable, then to the control unit 4 via communication line 22 a signal "0" is sent about the failure of the variable matching procedure. If all records are instantiated with the same constant, then in the associative memory of the substitutions there is only one (first) record about replacing this variable with the corresponding constant, and the rest of the records are deleted.

- step 2. In all pairs “variable - variable” the argument-variables are replaced with the corresponding constants in the other concretization entries. Moreover, if in a pair only the variable of the displayed rule is replaced with a constant (the column “Replaceable variable”), and the variable of the original rule is not (the column “New value”), then the cells (cell contents) in the columns “Replaceable variable” and “New value” are such records are swapped.

If for any record in the columns “Replaceable Variable” and “New Value” there are two constants with different values (names), then a signal “0” is sent to control node 4 via communication line 22 about the unsuccessful completion of the variable matching procedure. Records with two identical constants are deleted to reduce the amount of information stored in the lookup table.

- step 3. All instantiations of the variables of the same name are compared with constants (see figure 4, the columns “Replaceable variable” and “New value”). If in the column "New value" at least once there are different values of constants, then to the control unit 4 via communication line 22 a signal "0" is sent about the unsuccessful completion of the procedure for matching variables. If all records are specified by the same constant, then in the associative memory of the substitutions there is only one (first) record about replacing this variable with the corresponding constant, and the rest of the records are deleted, and a signal “1” is sent to control node 4 via communication line 22 about successful completion of the variable matching procedure.

Stage 4. If the procedure for concretizing the specified variables was unsuccessful (a signal “0” was received from the node of substitution formation 15 on the communication line 22), then the control unit 4 on the communication line 23 gives a “0” signal, which means that it is impossible to unify the analyzed pair of predicates. If the procedure for reconciling the specified variables was completed successfully (from the node of substitution formation 15, the signal “1” was received via the communication line 22), the control unit 4 via the communication line 23 gives the signal “1”, which means the successful completion of the unification of the pair of predicates. In this case, from the node of the formation of substitutions 15 via the communication line 24, replacements are made of all variables obtained by unifying the specified pair of predicates.

Example 1 (Fig. 5) demonstrates the case of successful completion of the process of matching variables - all pairs are marked (1), and the unification of predicates as a whole. Signal “1” is sent to control unit 4 from the substitution formation unit. Concretization of variables (substitutions) were obtained at stage 3, step 1.

Example 2 (Fig. 6) demonstrates the case of unsuccessful completion of the procedure for matching variables in the first step of the third stage and the unification of predicates in general.

Example 3 (Fig. 7) demonstrates the case of an unsuccessful completion of the procedure for matching variables in the second step of the third stage and the unification of predicates in general.

Example 4 (Fig. 8) demonstrates the case of unsuccessful completion of the procedure for matching variables in the third step of the third stage and the unification of predicates in general.

It should be noted that the traditional test (artificial) problems used to verify the correctness and effectiveness of various modifications of the classical principle of resolutions (including numerous implementations of the parallel Prolog) contain predicates with arity no more than 6-7. However, the increasing use of parallel inference methods in areas such as the management of large enterprises, medical and technical diagnostics, multi-criteria logical forecasting, makes it necessary to use predicates with 15–20 or more arguments. Preliminary estimates of the hardware implementation of the claimed device on the budget Altera Cyclone III FPGA indicate the free placement of more than 100 matching nodes on a chip in one unification block, which makes it possible to parallelly compare all arguments of processed predicates at the same time.

The minimum performance increase of the claimed device can be estimated as follows. We assume that the unified predicates are loaded into the internal memory in advance and the time is counted from the moment the trigger signal arrives (i.e., without taking stage 0 into account). The execution time of steps 1, 2, 4, as well as each step of step 3 (it will be required only if there is at least one variable in the pair of terms to be compared) will be called the device operation cycle. Then the unification execution time for examples 1 and 2 (Figs. 5 and 6) will be 4 measures: reading the arguments from the internal working memory, matching the arguments, matching the variables (step 1), and outputting the result.

For comparison, take the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification block with sequential matching of terms]. Steps 1, 2, and 4 on it are also performed in one cycle each. To search for and possibly coordinate (dereference) a variable in the substitution memory, 6 cycles (if necessary, matching) or 4 cycles (if there are no substitutions in the memory of the previous instantiations of the analyzed variable) are required. Thus, the minimum possible unification time will be 3 cycles if constants with different names (values) are used as the very first terms in the unified pair of predicates. In the inventive device, this time is also equal to 3 ticks.

In the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification unit with sequential comparison of terms] unification for example 1 (Fig. 5) will be performed in 45 cycles: reading predicate names (1 cycle); matching predicate names (1 measure); reading the first pair of arguments (1 clock); matching the first pair of arguments (1 clock); reading the second pair of arguments (1 clock); matching the second pair of arguments (1 clock); attempt to reconcile the variable x (4 measures); attempt to match the variable v (4 measures); reading the third pair of arguments (1 clock); matching the third pair of arguments (1 clock); attempt to reconcile y variable (4 measures); reading the fourth pair of arguments (1 clock); matching the fourth pair of arguments - 1 clock; attempt to match the variable z (4 measures); reading the fifth pair of arguments (1 clock); matching the fifth pair of arguments (1 clock); matching z variable (6 measures); reading the sixth pair of arguments (1 clock); matching the sixth pair of arguments (1 clock); reading the seventh pair of arguments (1 clock); matching the seventh pair of arguments (1 clock); coordination of the variable x (6 measures); delivery of results (1 step). In the inventive device - 4 cycles.

In the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unit unification with sequential comparison of terms] unification for example 2 (Fig. 6) will be performed in 35 cycles. Unification will fail when matching the variable z from the pair z / е578kn with the previously specified value z / к875not. In the inventive device, unification will be performed in 4 cycles.

In the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unit unification with sequential comparison of terms] unification for example 4 (Fig. 6) will be performed in 23 cycles. In the inventive device, unification will be performed in 6 cycles: reading arguments from the internal working memory, matching arguments, matching variables (step 1), matching variables (step 2), matching variables (step 3), outputting the result.

All comparisons are given for the case when the previous variable substitutions are in the internal memory of the unification block. For the inventive device, this condition is always satisfied. For the device [RU No. 158945 (U1), G06N 5/04. Application: 2015120634/08, 05/29/2015; publ. 01/20/2016. Unification unit with sequential matching of terms] in the internal memory, only the substitutions performed during the unification of the current pair of predicates of the processed clause rules are stored. The remaining instantiations are stored in external memory. For the device [Vishnyakov, VA, Hardware-software means of logical output processors [Text] / V.A. Vishnyakov, D.Yu. Boulanger, O.V. Hermann. - M.: Radio and Communications, 1991. - 264 p.] All instantiations of variables are stored in external memory, which must be accessed at each agreement of the compared variables. This significantly increases the total unification time of a pair of predicates.

Based on the foregoing, it can be argued that the inventive device significantly reduces the time of unification, which will allow to achieve significant superiority in performance of specialized logical output processors developed on its basis over existing analogs.

Claims (5)

A unification unit with parallel term matching, containing an internal working memory, one of the inputs of which is connected to the input data bus, a control unit, one of the inputs of which is connected to the input control bus, characterized in that it further comprises: node predicate name matching, the input of which is connected to one of the outputs of the internal working memory, and the output is connected to one of the inputs of the control node, term comparison nodes, the inputs of which are connected to the outputs of the internal working memory and the outputs of the dispatch node, and the outputs are connected to the inputs of the control node, the inputs of the substitution formation node and the inputs of the dispatch node, a dispatching node, the inputs of which are connected to the outputs of the term mapping nodes, and the outputs are connected to one of the inputs of the internal working memory and the inputs of the term mapping nodes, a substitution formation unit, the inputs of which are connected to the outputs of the term mapping nodes and one of the outputs of the internal working memory, and the outputs are connected to one of the inputs of the control node and the output data bus.

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