RU2553057C1 - Device to generate systems of double derivative non-linear recurrent sequences - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: device to generate systems of double derivative non-linear recurrent sequences comprises a system unit of control and provision of a possibility of program control of the process of replacement of lengths and code forms, types and subtypes. The device includes a device to generate code words of non-linear recurrent sequences, a double-input summator by module two, the outlet of which is the outlet of the device, and also a system control unit, made of decoders of one and another type, counters. It makes it possible to generate a system of double derivatives of various durations, types and subtypes in a program-controlled mode, which makes it possible to generate systems of pseudorandom sequences, improving authentication, security, as well as the arsenal of replaceable parameters.

EFFECT: increased reliability of operation.

1 tbl, 10 dwg

Description

The invention relates to digital data processing, and in particular to a technique for generating pseudo-random sequences of discrete noise-like signals (SHPS) used in broadband communication systems, radio navigation and radar systems.

In special systems with complex signals, noise immunity and signal immunity are achieved, firstly, by expanding their spectrum by manipulating the informative parameters of the carrier wave according to the law of pseudorandom sequences (PSP), and secondly, by using such PSPs that have high required structural secrecy. At the same time, they strive to achieve the best correlation and ensemble properties of the PSP, taking into account that, in the general case, the noise immunity of the system increases with the duration and arsenal of replaceable parameters of the SSP [1, 3, 4, 5, 6]. The latter include the number of elementary symbols in the PSP and its code form from the set of code forms possible for this class of PSP.

The classes of PSPs widely used in practice for these purposes include linear recurrent PSPs in the form of M-sequences and derivatives of PSPs from them [1, 2, 5]. However, as shown in [2, 3, 4, 5, 6], due to the fact that M-sequences have low structural secrecy and immitability, limited by the volume of durations L and an arsenal of interchangeable parameters V _SP , gradually the place of M-sequences for solving the above tasks are occupied by simple nonlinear recurrence sequences (NLRP) based on characteristic codes and quadratic residue codes existing for the durations L = {p, p-1, p ⁿ , p ⁿ -1} = {4t, 4t + 1, 4t + 2, 4t + 3}, where p is a prime, n = 2, 3, 4 ..., t = 2, 3, 4, ..., and having absolute linear the complexity of the disclosure of the structure (LSRS) equal to L (LSRS = L). At the same time, as shown in [3, 4, 6], due to their secrecy, simulated resistance, duration and arsenal of interchangeable parameters, the generated from them primarily have undeniable advantages over simple NLRP (characteristic codes and quadratic residue codes [3, 4]) derivatives of NLRP (PNLRP). The rules for the formation of PNLRP are fundamentally known [3]. So, in particular, according to [3], two-fold (DC) PNLRPs of the form W ² are called such SRPs that are formed from 2 simple NLRPs of the form V ^j , j = 1, 2, according to the rule:

where l ₁ , l ₂ are the durations of simple NLRP V ^j , j = 1,2, j is the number of the generating element is simple NLRP, k is the largest common divisor (GCD) for durations l ₁ , l ₂ : k = GCD (l ₁ , l ₂ ).

в правиле (1) характерен для случая, если простые НЛРП представляют собой бинарные последовательности, т.е. состоящие из символов (-1, 1) [2]. Если же представлять простые НЛРП V^j как дискретные (двоичные) последовательности, т.е. состоящие из символов (1, 0), когда «-1» заменяется на «0», то в правиле (1) необходимо знак произведения $${П}_{j=1}^2$$

для $$W_i^2$$

заменить на знак суммы $${\Sigma }_{j=1}^2$$

по модулю 2 (⊕). Тогда для дискретного случая представления V^j правило (1) будет иметь вид:Note: Multiplication Sign $$P_{j=\mathrm{one}}^2$$

in rule (1) is characteristic of the case if simple NLRPs are binary sequences, i.e. consisting of characters (-1, 1) [2]. If we represent simple NLRP V ^j as discrete (binary) sequences, i.e. consisting of characters (1, 0), when "-1" is replaced by "0", then in rule (1) the product sign is necessary $$P_{j=\mathrm{one}}^2$$

for $${\mathrm{<figure-callout\; id="2"\; label="W\; i"\; filenames="00000044.png,00000046.png"\; state="\{\{state\}\}">W\; </figure-callout>}}_i^{}$$

replace with a sum sign $${\Sigma }_{j=\mathrm{one}}^2$$

modulo 2 (⊕). Then, for the discrete case of the representation V ^j, rule (1) will have the form:

имеют идентичные отображения. Так, например, для правила (1) имеем: (1+1)=1, 1·(-1)=-1, (-1)·1=-1, (-1)·(-1)=-1, - для правила (2) имеем: 1⊕0=1, 0⊕1=1, 1⊕1=0, 0⊕0=0. То есть сочетания одинаковых символов в правиле (1) приводит к результирующему символу «0», а разных - к символу «1». При этом внутренняя структура ДК ПНЛРП, т.е. порядок взаимного расположения различающихся символов («1» и «-1» в правиле (1) и «1» и «0» в правиле (2)) изменяться не будет, следовательно, не будут меняться и структура корреляционных функций и их свойства. Мы будем в дальнейшем иметь дело с правилом (2).From the point of view of the internal structure of DC PNLRP and the structure of the correlation functions of DC PNLRP systems, differences in rules (1) and (2) do not matter, because various combinations of characters “1” and “-1” in rule (1) and characters “1” and “0” in rule (2) to express $${\mathrm{<figure-callout\; id="2"\; label="W\; i"\; filenames="00000044.png,00000046.png"\; state="\{\{state\}\}">W\; </figure-callout>}}_i^{}$$

have identical mappings. So, for example, for rule (1) we have: (1 + 1) = 1, 1 · (-1) = - 1, (-1) · 1 = -1, (-1) · (-1) = - 1, - for rule (2) we have: 1⊕0 = 1, 0⊕1 = 1, 1⊕1 = 0, 0⊕0 = 0. That is, the combination of the same characters in rule (1) leads to the resulting character “0”, and different characters to the character “1”. Moreover, the internal structure of the PNLRP recreation center, i.e. the order of mutual arrangement of different characters (“1” and “-1” in rule (1) and “1” and “0” in rule (2)) will not change, therefore, the structure of correlation functions and their properties will not change. In the future, we will deal with rule (2).

Moreover, the volume of interchangeable parameters (SP) V _SP (vocabulary) of PNLRP is determined by the number of different lengths l _{i of the} simple NLRP used, as well as the number of their isomorphic and automorphic transformations in the case of fixed isomorphisms [2, 3].

. Общее же число-объем кодового словаря НЛРП фиксированной длины l_j равен $$V_j=N_{и{з}_j}\cdot l_j$$

, где $$N_{и{з}_j}=\varphi \left(p_j,p_j-1\right)$$

- число изоморфных преобразований, где φ(·) - функция Эйлера [2], p_j - простое число. Объем кодового словаря ДК ПНЛРП равен V_ПНЛРП=V_j·V_i, где {i,j} - различные длины простых НЛРП - производящих элементов, то есть:So according to [2, 3], the number of automorphic transformations V _{A of} simple NLRP in the form of quadratic residue codes or characteristic codes is the number of cyclic shifts of simple NLRP and is equal to V _A = l _j . Therefore, the automorphic volume V _{A of the} ensemble of simple NLRP of duration l _j is $${\left(V_A\right)}_{l_j}=l_j$$

. The total number-volume of the NLRP code dictionary of fixed length l _j is $$V_j=N_{\mathrm{and}{s}_j}\cdot l_j$$

where $$N_{\mathrm{and}{s}_j}=\varphi \left(p_j,p_j-\mathrm{one}\right)$$

is the number of isomorphic transformations, where φ (·) is the Euler function [2], p _j is a prime. The volume of the code dictionary DK PNLRP is equal to V _PNLRP = V _j · V _i , where {i, j} are different lengths of simple NLRP - generating elements, that is:

. To есть V_ПНЛРП,L>>V_НЛРП,L. Если теперь сравнить, например, только автоморфные объемы V_A словарей фиксированных длительностей для ПНЛРП и простой НЛРП, близких по величине L_ПНЛРП≈L_НЛРП, то можно уже установить, что: $${(V_A)}_{ПНЛРП,L}=l_1\cdot l_2>{(V_A)}_{НЛРП,L}=\frac{l_1\cdot l_2}{k}$$

, k=НОД (l₁, l₂). Отсюда видно, что объем арсенала сменных параметров (при близких по значениям L_ПНЛРП≈L_НЛРП), у ПНЛРП значительно больше, чем y НЛРП минимум в k раз, а максимум в $$k\cdot \{[{\varphi }_i(\cdot )][{\varphi }_j(\cdot )]/\varphi *\}$$

раз. Кроме того, хотя на настоящий момент простые НЛРП и обладают абсолютной ЛСРС=L, но понятно, что это свойство «абсолютным» является временно, так как регулярность и детерминированность правил построения простых НЛРП [2] предполагает в обозримом будущем разработку алгоритмов раскрытия их структуры по аналогии алгоритму Берлекемпа-Месси, обеспечивающему раскрытие структур М-последовательностей [5]. В этой связи применение ПНЛРП, которые в сравнении с НЛРП «разрушают» регулярность нелинейной структуры простых НЛРП и тем самым становятся незаменимыми с точки зрения высоких требований по скрытности и имитостойкости, и с учетом выигрыша по (V_A)_ПНЛРП и V_СП, в специальных информационных системах, становится весьма актуальным и целесообразным.Given that the duration of NLRP l _{i, j} = {p = (4t + 1,4t + 3); p - 1 = (4t, 4t + 2)}, then, taking into account the calculation of the Euler function φ (·), it is easy to establish, for example, according to [2], that $$\varphi *(p\approx N_{\mathrm{and}s}^{*},p-\mathrm{one})<<[{\varphi }_j(p=N_{\mathrm{and}{s}_j},p-\mathrm{one})][{\varphi }_i(p=N_{\mathrm{and}{s}_j},p-\mathrm{one})]$$

. To have V _{PNLRP, L} >> V _{NLRP, L.} If we now compare, for example, only automorphic volumes V _{A of} dictionaries of fixed durations for PNLRP and simple NLRP, close in magnitude L _PNLRP ≈L _NLRP , then we can already establish that: $${(V_A)}_{PNLRP,L}=l_{\mathrm{one}}\cdot {\mathrm{<figure-callout\; id="2"\; label="l"\; filenames="00000044.png,00000046.png"\; state="\{\{state\}\}">l</figure-callout>}}_2>{(V_A)}_{NLRP,L}=\frac{l_{\mathrm{one}}\cdot l_2}{k}$$

, k = GCD (l ₁ , l ₂ ). From this it can be seen that the volume of the arsenal of interchangeable parameters (at close L _LNLRP ≈L _NLRP with similar L values), LNLRP is much larger than y LNLR at least k times, and the maximum at $$k\cdot \{[{\varphi }_i(\cdot )][{\varphi }_j(\cdot )]/\varphi *\}$$

time. In addition, although at the moment simple NLRPs have absolute LSRS = L, it is clear that this property is “absolute” temporarily, since the regularity and determinism of the rules for constructing simple NLRP [2] suggests in the foreseeable future the development of algorithms for revealing their structure according to analogies to the Berlekamp-Messi algorithm, which provides the disclosure of the structures of M-sequences [5]. In this regard, the use of PNLRP, which, in comparison with NLRP, “destroys” the regularity of the nonlinear structure of simple NLRP and thereby becomes indispensable in terms of high requirements for stealth and _{imitation resistance} , and taking into account the gain in (V _A ) _PNLRP and V _SP , in special information systems, it becomes very relevant and appropriate.

It should be borne in mind that if, to solve the problems of generating simple NLRP of any kind, a modern relevant concept and theory [7, 8, 9, 10], as well as a number of technical solutions, for example [11, 12], have been developed, then devices (technical solutions), allowing to generate PNLRP, and even more so PNLRP systems of various durations L = var and volumes V _СП = var have not been developed so far. Thus, the task of developing such technical solutions, and in particular, the formation of double-entry systems (SDK) PNLRP is relevant. The solution to this problem is seen, first of all, along the natural path, which is defined by rules (1) and (2), indicating that the devices for the formation of DC PNLRP can be built through the joint use of 2 devices for the formation of simple NLRP of various durations and code forms . A model of this use is shown in FIG. 1. At the same time, if the code forms and the duration of the NLRP formed by these 2 devices are changed according to the corresponding program, then we can already talk about the formation of the PNLRP DC system (SDK).

Thus, the desired result in the formation of SDL PNLP taking into account the model of FIG. 1, software-controlled generation of the largest number of code forms and lengths of the PNLRP DC should be considered based on the use of program-controlled generation of simple NLRP code dictionaries by 2 NLRP formation devices, that is, {(V _A ) _PNLRP , V _SP } → max while minimizing time and hardware costs.

Based on the need to achieve this result in the formation of SDLP SDK, the closest to the claimed one is a device for generating code dictionaries of nonlinear recurrence sequences of various durations L = 8, 10, 11, 12, 13, 16 lengths L = 8, 10, 11, ... 30 (cm Patent 2439657 Russian Federation, IPC G06F 7/00, Device for generating code dictionaries of nonlinear recurrence sequences [Text] / Snytkin II, Fedoseev V.E., Snytkin TI, Kurlyandchik DA - No. 2009112944 / 08; claimed 06.04.09; published on 01/10/12, Bull. No. 1. - 2 pp. Ill.).

It contains a device for generating code dictionaries of nonlinear recurrence sequences (UFKS NLRP), consisting of a block for generating a cyclic sequence of characters (BFTSPS), a block for generating an optimal sequence (BFOP) and a control unit (BU), moreover, BFTSPS consists of a decryption unit, including the first to the sixth element And, the delay element, the adder modulo two, the first multiplexer and the shift register, and the information inputs from the first to the fourth BFTSPS are connected respectively to the information the first to fourth shift register inputs, the first to fourth direct outputs of which are connected respectively to the direct outputs of the BFTSPS, the synchronization input of which is connected to the shift register synchronization input, the first to fourth inverse outputs of which are connected respectively to the inverse outputs from the first to fourth BFPSS , six outputs (according to the number of NLRP lengths) of six elements And whose decryption node is connected to the inputs of the first multiplexer, while the “decryption address” is fed to the other inputs of the first the second multiplexer, the output of which is connected to the input of the delay element, the output of which is connected to the first input of the adder modulo two, the output of which is connected to the input of the “mode” of the shift register, while the control unit has an input of “start” and an input of “record of the initial state”, the first to fifth inputs of the "dictionary code", from the first to fourth inputs of the "initial phase code", and the inputs of the "initial phase code" are combined respectively with direct outputs from the first to fourth BFPSS and connected respectively to the inputs of the mode from first to even the second group of control units, while the control unit contains the first, second and third registers, the first and second counters, a clock pulse generator, a key and an OR element, the inputs of the “dictionary cipher code” from the first to fifth of the first control unit are connected respectively to mode inputs with the first to fifth of the first register, the first to fifth outputs of which are connected respectively to the inputs from the first to fifth of the first counter, the transfer output of which is combined with the input of the initial state record and connected to the first synchronization inputs of the first and second histr, to the first information input of the key, the output of which is connected to the counting input of the first counter, and the input "start" BU is also connected to the first input of the OR element, to the start input of the clock generator, the output of which is connected to the control third input of the key and the second input of the element OR, whose output is connected to the synchronization input of the first counter and the output of the control unit, the mode inputs from the first to the fourth second groups of which are connected respectively to the inputs from the first to the fourth second register, the outputs from the first the fourth through which are connected respectively to the outputs from the first to the fourth control unit, the inputs of the “NLRP length code” from the first to fifth are connected to the analogous inputs of the “NLRP length code” from the first to fifth of the third register, the first to fifth outputs of which are connected to the corresponding the inputs of the second counter, the output of which is combined with the input of the "start" and connected to the second synchronization inputs of the first, second and third registers, to the second information input of the key, as well as to the output "end of the NLRP" BU, and the input of the "start" BU also connected to the counting input of the second counter and the second input of the OR element, the output of which is connected to the synchronization input of the first and second counters, while the BFOP includes the first to eleventh OR elements, from the seventh to twenty-seventh AND elements and the second multiplexer, and with the first to fourth direct and inverse outputs of the BFTSPS are connected to the BFOP and the control unit so that the first direct output of the BFTSPS is combined with the first input of the "initial phase code" and connected to the first input of the second register mode of the control unit, to the first input of the first and second of the first element AND of the BFTSPS decryption unit, to the first input of the seventh, eighth, tenth and twenty-seventh elements And, the third input of the twenty third element And and the second input of the first element OR BFOP, and the first inverse output of the BFTSPS is connected to the first input of the third, fourth, fifth, of the sixth, eleventh and twenty-first AND elements to the first input of the second OR OR BFOP element, and the second direct output of the BFTSPS is combined with the second input of the "initial phase code" and connected to the second input of the second register mode of the control unit, and also connected to the second input of the ninth, twelfth and seventeenth AND elements, as well as the second input of the first, third, fifth, seventh and twenty-first elements AND BFOP, and the second inverse output of the BFTSS is connected to the first inputs of the fourteenth, fifteenth and eighteenth elements And, as well as to the second inputs the fourth and tenth elements And, the third direct output is combined with the third input of the initial phase code and is connected to the third input of the second register mode of the control unit, and is also connected to the second input of the second, twentieth, twenty-sixth elements And, ne the second input of the thirteenth AND element, the second input of the ninth OR element, the third input of the third AND element and the third adder input modulo two BFTSPS, the third inverse output of which is connected to the first input of the nineteenth, twenty second and twenty third elements And, to the second input of the sixteenth, seventeenth , twenty-fourth and twenty-fifth elements AND, to the third input of the first, second, fourth and sixth elements AND BFOP, and the fourth direct output is combined with the fourth input of the "initial phase code" and connected to the fourth input of the second register mode of the control unit, and is also connected to the first input of the twenty-fourth element And, the second input of the eighth, eleventh, thirteenth and eighteenth elements And, the fourth input of the second, third and fourth elements And BFOP and to the second input of the adder modulo two BFTSPS, the fourth inverse output of which is connected to the first input of the first OR element and the twentieth element And, to the second input of the ninth, twelfth and fourteenth elements And, as well as to the fourth input of the first, fifth and sixth element And BFOP, while the output of the first OR element is connected to the second input of the sixteenth AND element, the output of which is connected to the first input of the third OR element, the output of which is connected to the first input of the second multiplexer, the output of the seventh AND element is connected to the second input of the fifth OR element, the output of which connected to the third input of the second multiplexer, the output of the seventeenth element And connected to the first input of the fifth element OR, the output of the twenty-fourth element And connected to the second input of the fourth element OR, the output to or connected to the second input of the second multiplexer, the output of the eighth AND element is connected to the first input of the fourth OR element and to the second input of the fifth OR element, the output of the second OR element is connected to the first input of the twenty-fifth AND element, the output of which is connected to the first input of the sixth OR element, the output of which is connected to the fourth input of the second multiplexer, the output of the ninth AND element is connected to the second input of the third and sixth OR elements, as well as to the second input of the twenty third AND element, the output is eighteen of the AND element is connected to the second input of the second OR element, the output of the tenth OR element is connected to the first input of the twenty-sixth AND element and the seventh OR element, the output of which is connected to the fifth input of the second multiplexer, the output of the eleventh AND element is connected to the second input of the seventh OR element and the nineteenth AND element, whose output is connected to the first input of the eighth OR element, whose output is connected to the sixth input of the second multiplexer, the output of the twentieth element And is connected to the second input of the eighth electronic OR, the output of the twelfth element AND is connected to the third input of the eighth OR element and to the first input of the ninth OR element, the output of which is connected to the second input of the twenty-seventh AND element, the output of the twenty-first element AND is connected to the first input of the tenth OR element, the output of which is connected to the seventh the input of the second multiplexer, the output of the thirteenth AND element is connected to the second input of the tenth OR element and the fifteenth And element, the output of the twenty second element And is connected to the third input of the tenth OR element, the output of the fourteenth AND element is connected to the third input of the ninth OR element and to the second input of the twenty second AND element, the output of the twenty third element AND is connected to the second input of the eleventh OR element, the output of the twenty sixth element AND is connected to the third input of the fourth element OR, the output of the ninth OR element connected to the second input of the twenty-seventh AND element, the output of which is connected to the first input of the eleventh OR element, the output of the fifteenth AND element is connected to the second input of the eleventh AND element LI, the output of which is connected to the eighth input of the second multiplexer, to the other inputs of which there is an "NLRP type code", and its output is connected to the "NLRP output" of the device, from which the generated simple nonlinear SRP is removed.

These essential features of this device [12] are similar to the set of essential features of the claimed device, moreover, the claimed device contains 2 data of the device with a complete set of the indicated features of each device.

However, the known prototype device [12] provides the formation of simple NLRP in program-controlled modes of durations L = 8, 10, 11, 12, 13, 16 (total m = 6 is the number of different durations) and all kinds of their code-based automorphic and isomorphic transformations (forms ), whereas for the formation of FFAP PNLRP, it is necessary to control the generation of a large number of different types, subspecies and volumes of FFOR PNLRP according to rule (2) and the model in FIG. 1. Namely:

длительностей l_j в правиле (2), где n=2 (для двукратных ПНЛРП), а m=6 - число различных l_j в (2) (всего число видов равно $$C_6^2=15$$

): 1-й вид: (8×10); 2-й вид: (8×11); 3-й вид: (8×12); 4-й вид: (8×13); 5-й вид: (8×16); 6-й вид: (10×11); 7-й вид: (10×12); 8-й вид: (10×13); 9-й вид: (10×16); 10-й вид: (11×12); 11-й вид: (11×13); 12-й вид: (11×16); 13-й вид: (12×13); 14-й вид: (12×16); 15-й вид: (13×16), - то есть число видов ДК ПНЛРП V_в=15.1) "Types" of SDK PNLRP are various combinations $$C_m^n$$

durations l _j in rule (2), where n = 2 (for double PNLRP), and m = 6 is the number of distinct l _j in (2) (the total number of species is $${\mathrm{<figure-callout\; id="6"\; label="C"\; filenames="00000044.png,00000046.png"\; state="\{\{state\}\}">C</figure-callout>}}_6^2=\mathrm{fifteen}$$

): 1st view: (8 × 10); 2nd view: (8 × 11); 3rd view: (8 × 12); 4th view: (8 × 13); 5th view: (8 × 16); 6th view: (10 × 11); 7th view: (10 × 12); 8th view: (10 × 13); 9th view: (10 × 16); 10th view: (11 × 12); 11th view: (11 × 13); 12th view: (11 × 16); 13th view: (12 × 13); 14th view: (12 × 16); 15th type: (13 × 16), that is, the number of types of DC PNLRP V _in = 15.

ДК ПНЛРП являются различные сочетания кодовых форм (авто- и изоморфных преобразований) простых НЛРП данного вида. Число подвидов $$V_{П{В}_k}$$

, $$k=\overline{\mathrm{1,15}}$$

, каждого k-го вида определяется, учитывая, что для НЛРП длительностей L=(10,12) имеется $$N_{и{з}_{\mathrm{1,2}}}=2[\mathrm{2,12}]$$

и следуя (3), числом указанных преобразований каждой (l₁ и l₂) производящей НЛРП:2) “Subspecies” of each k-th species $$(k=\overline{1.15})$$

DC PNLRP are various combinations of code forms (auto- and isomorphic transformations) of simple NLRP of this type. Number of subspecies $$V_{P{\mathrm{AT}}_k}$$

, $$k=\overline{1.15}$$

, each k-th species is determined, given that for NLRP of durations L = (10,12) there is $$N_{\mathrm{and}{\mathrm{<figure-callout\; id="1"\; label="s"\; filenames="00000044.png,00000046.png"\; state="\{\{state\}\}"><figure-callout\; id="2"\; label="s"\; filenames="00000044.png,00000046.png"\; state="\{\{state\}\}">s</figure-callout></figure-callout>}}_{\mathrm{1,2}}}=2[2.12]$$

and following (3), the number of these transformations of each (l ₁ and l ₂ ) producing NLRP:

and then the number of subspecies for each type of PNLRP, given that the prototype device provides the formation of 2 non-inverse isomorphic (NL) transformations for NLRP with l = 10 and l = 12, is:

, которые возможно обеспечить равно: $$V_{ПВ}^{\Sigma }={\Sigma }_{i=1}^{24}{V}_{П{В}_i}=3439$$

, то есть в 1,7 раза больше возможных подвидов кодовых форм, чем для НЛРП близких по длительности. При этом следует учесть, что такое число кодовых форм ДК ПНЛРП обеспечивается для длительностей ДК ПНЛРП соответственно: L_ПНЛРП=(40, 88, 24, 104, 16, 110, 60, 130, 80, 132, 143, 176, 156, 48, 208), то есть в диапазоне длительностей L={16…208}. Формирование такого же числа длин L и в том же диапазоне и объема $$V_{ПВ}^{\Sigma }$$

кодовых форм в виде простых НЛРП потребовало бы создания технических решений, подобных прототипу, которые по сложности их создания и объему простейших логических элементов на несколько порядков превышали бы устройство-прототип, так как число устройств, подобных прототипу, будет равно числу требуемых кодовых форм V_СП и длительностей L ДК ПНЛРП. Это приведет не только к значительным аппаратным затратам, но и осложнит существенно реализацию централизованного оперативного управления процессом смены кодовых форм и длин ПНЛРП. Тогда как согласно модели на фиг. 1 для генерирования СДК ПНЛРП необходимо лишь два базовых одинаковых устройства формирования НЛРП и соответствующий системный блок управления (СБУ), как показано на фиг. 2, обеспечивающий смену кодовых форм простых НЛРП.Thus, the total (total, ∑) number of subspecies of the DC PNLRP, $$V_{P\mathrm{AT}}^{\Sigma }$$

which may be provided equal to: $$V_{P\mathrm{AT}}^{\Sigma }={\Sigma }_{i=\mathrm{one}}^{24}{V}_{P{\mathrm{AT}}_i}=3439$$

, that is, 1.7 times more possible subspecies of code forms than for NLRP close in duration. It should be borne in mind that such a number of code forms of DC PNLRP is provided for the durations of DC PNLRP, respectively: L _PNLRP = (40, 88, 24, 104, 16, 110, 60, 130, 80, 132, 143, 176, 156, 48 , 208), that is, in the duration range L = {16 ... 208}. Formation of the same number of lengths L and in the same range and volume $$V_{P\mathrm{AT}}^{\Sigma }$$

code forms in the form of simple NLRP would require the creation of technical solutions similar to the prototype, which, by the complexity of their creation and the volume of the simplest logical elements, would be several orders of magnitude greater than the prototype device, since the number of devices similar to the prototype would be equal to the number of required code forms V _SP and durations L DC PNLRP. This will lead not only to significant hardware costs, but also significantly complicate the implementation of centralized operational management of the process of changing the code forms and lengths of PNLRP. Whereas according to the model in FIG. 1 in order to generate an NLRP SDK, only two basic identical NLRP formation devices and a corresponding system control unit (SBU) are required, as shown in FIG. 2, providing a change in the code forms of simple NLRP.

An object of the invention is the program-controlled (from the point of view of the choice of types, subspecies, current lengths, code forms, codebook volume) the formation of SDLPLP based on characteristic codes and quadratic residue codes of various lengths from a set of values L = {8, 10, 11, 12, 13, 16} achieved by using one functionally complete device.

, и в диапазоне длин L=(16, 24, 40, 48, 60, 80, 88, 104, 110, 130, 132, 143, 156, 176, 208), при значительном сокращении аппаратных затрат на построение устройства формирования возможно такого же объема кодовых форм разных длин в этом же диапазоне, но только в виде НЛРП, за счет интеграции в одном устройстве функциональных возможностей двух идентичных устройств формирования простых НЛРП, а также обеспечение возможности программного управления процессом смены видов и подвидов, объемов, длин и кодовых форм СДК ПНЛРП, что крайне актуально для значительного повышения скрытности, имитостойкости широкополосных систем с адаптивно изменяемой структурой и базой ШПС.The technical result achieved by the implementation of the invention lies in the possibility of generating SDK PNLRP (in program-controlled mode) with a volume of code forms equal to $$V_{P\mathrm{AT}}^{\Sigma }=3439$$

, and in the range of lengths L = (16, 24, 40, 48, 60, 80, 88, 104, 110, 130, 132, 143, 156, 176, 208), with a significant reduction in hardware costs for building the forming device, this is possible the same amount of code forms of different lengths in the same range, but only in the form of NLRP, due to the integration of the functionality of two identical devices for forming simple NLRP in one device, as well as providing the ability to programmatically control the process of changing types and subspecies, volumes, lengths and code forms KFOR PNLRP, which is extremely important for a significant increase in hidden characteristics, imitation resistance of broadband systems with adaptively changing structure and base of ShPS.

The application of the invention provides increased noise immunity, adaptability, secrecy and imitation resistance of broadband systems due to the increase in the volume V _{cn of} replaceable codebook parameters through the use of program-controlled SDK PNLRP obtained from simple NLRP of different shapes and lengths.

, в диапазоне длин L=(16, 24, 40, 48, 60, 80, 88, 104, 110, 130, 132, 143, 156, 176, 208) введены второе идентичное УФКС НЛРП, двухвходовый элемент И, выход которого является выходом «конец ПНЛРП» устройства, двухвходовый сумматор по модулю два, выход которого является выходом ПНЛРП устройства, системный блок управления (СБУ), состоящий из системного дешифратора «вида ПНЛРП», системного дешифратора «подвида ПНЛРП» и первого и второго счетчиков, причем выход «НЛРП» первого и выход «НЛРП» второго УФКС НЛРП являются соответствующими выходами НЛРП-1 и НЛРП-2 первого и второго УФКС НЛРП и подключены соответственно к первому и второму входам двухвходового сумматора по модулю два, а вход «запуска» и вход «записи начального состояния» первого и аналогичные входы второго УФКС НЛРП соответственно объединены и подключены соответственно к входу «запуска» и входу «записи начального состояния» устройства, а входы с первого по четвертый «кода вида ПНЛРП» и входы с первого по одиннадцатый «кода подвида ПНЛРП» устройства являются соответствующими входами соответственно системного дешифратора «вида ПНЛРП» и системного дешифратора «подвида ПНЛРП» и соответствующими входами СБУ, первый и второй выходы «конец ПНЛРП» которого подключены соответственно к первому и второму входам двухвходового элемента И и соответственно к выходу переноса первого и выходу переноса второго счетчиков, счетные входы которых подключены соответственно к входам «конец НЛРП-1» и «конец НЛРП-2» СБУ и к выходам «конец НЛРП» соответственно первого и второго УФКС НЛРП, а синхронизирующие входы первого и второго счетчиков подключены соответственно к первому и второму синхронизирующим входам СБУ и подключены соответственно к синхронизирующим выходам первого и второго УФКС НЛРП и подключены соответственно к выходу элемента ИЛИ БУ первого и к выходу элемента ИЛИ БУ второго УФКС НЛРП, входы «код длины НЛРП» с первого по пятый, входы «код вида НЛРП» и входы «адреса дешифрации» которых соответственно подключены к соответствующим выходам «код длины НЛРП-1» с первого по пятый, «код длины НЛРП-2» с первого по пятый, «код вида НЛРП-1», «код вида НЛРП-2» и «адреса дешифрации НЛРП-1», «адреса дешифрации НЛРП-2» первого системного дешифратора «вида ПНЛРП», выходы «код числа НЛРП-1» с первого по четвертый и выходы «код числа НЛРП-2» с первого по четвертый которого подключены соответственно к установочным входам с первого по четвертый соответственно первого и второго счетчиков, а входы «кода начальной фазы» с первого по четвертый и входы «кода шифра словаря» с первого по пятый первого и второго УФКС НЛРП подключены соответственно к выходам «код начальной фазы НЛРП-1» с первого по четвертый, «код начальной фазы НЛРП-2» с первого по четвертый и выходам «код шифра словаря НЛРП-1» с первого по пятый, «код шифра словаря НЛРП-2» с первого по пятый второго системного дешифратора «подвида ПНЛРП».The essence of the invention lies in the fact that the device for generating SDK PNLRP contains a known device for generating code dictionaries NLRP (UFKS PNLRP) and with the aim of realizing the possibility of forming SDK PNLRP with a volume of code forms equal to $$V_{P\mathrm{AT}}^{\Sigma }=3439$$

, in the length range L = (16, 24, 40, 48, 60, 80, 88, 104, 110, 130, 132, 143, 156, 176, 208) the second identical UFKS NLRP, two-input element And, the output of which is the output “PNLRP end” of the device, a two-input adder modulo two, the output of which is the PNLRP output of the device, a system control unit (SBU), consisting of a “PNLRP type” system decoder, a PNLRP subsystem decoder and the first and second counters, and the output The “NLRP” of the first and the output of “NLRP” of the second UFKS NLRP are the corresponding outputs of NLRP-1 and NLRP-2 of the first and second about UFKS NLRP and are connected respectively to the first and second inputs of the two-input adder modulo two, and the input of the "start" and the input of the "entry of the initial state" of the first and similar inputs of the second UFKS NLRP are respectively combined and connected respectively to the input of the "start" and the "record" input the initial state "of the device, and the first to fourth inputs of the" PNLRP type code "and inputs from the first to eleventh" PNLRP subspecies code "of the device are the corresponding inputs of the" PNLRP type "system decoder and system second decoder "subspecies PNLRP" and the corresponding inputs of the SBU, the first and second outputs "end PNLRP" which are connected respectively to the first and second inputs of the two-input element And, respectively, to the transfer output of the first and transfer output of the second counters, the counting inputs of which are connected respectively to the inputs " the end of NLRP-1 ”and“ the end of NLRP-2 ”of the SBU and to the outputs“ end of NLRP ”of the first and second UFKS NLRP, respectively, and the synchronizing inputs of the first and second counters are connected respectively to the first and second synchronizer SBU inputs and are connected respectively to the synchronizing outputs of the first and second UFKS NLRP and connected respectively to the output of the element OR BU of the first and the output of the element OR BU of the second UFKS NLRP, the inputs are “NLRP length code” from first to fifth, the inputs are “NLRP type code” and the “decryption address” inputs of which are respectively connected to the corresponding outputs “NLRP-1 length code” from first to fifth, “NLRP-2 length code” from first to fifth, “NLRP-1 type code”, “NLRP-2 type code "And" NLRP-1 decryption addresses "," NLRP-2 decryption addresses "of the first system of the “PNLRP type” decoder, outputs “NLRP-1 number code” from first to fourth and “NLRP-2 number code” outputs from first to fourth of which are connected respectively to installation inputs from first to fourth respectively of first and second counters, and inputs “ the initial phase code "from the first to the fourth and the inputs of the" dictionary cipher code "from the first to the fifth of the first and second UFKS NLRP are connected respectively to the outputs" the initial phase code of NLRP-1 "from the first to the fourth," the initial phase code of NLRP-2 "with first through fourth and outputs "dictionary cipher code NLRP-1 "from the first to the fifth," the cipher code of the dictionary NLRP-2 "from the first to the fifth of the second system decoder of the" subspecies PNLRP ".

, и в диапазоне длин L=(16, 24, 40, 48, 60, 80, 88, 104, 110, 130, 132, 143, 156, 176, 208).The technical result of the invention is ensured by the presence of significant distinguishing features and new connections in the device, namely, by introducing a second identical device for generating code dictionaries of nonlinear recurrence sequences (UFKS NLRP), a two-input element And, the output of which is the output “PNLRP” of the device, two-input adder modulo two, the output of which is the output of the PNLRP device, the system control unit (SBU), consisting of a system decoder "type PNLRP", si dark decoder "subspecies PNLRP" and the first and second counters, as well as by introducing relevant new bonds between SSU and both UFKS NLRP that allows for the possibility of generating SDK PNLRP in program-controlled manner forms the code amount equal to $$V_{P\mathrm{AT}}^{\Sigma }=3439$$

, and in the length range L = (16, 24, 40, 48, 60, 80, 88, 104, 110, 130, 132, 143, 156, 176, 208).

Device description

In FIG. 1 shows a model for the joint use of 2 devices for the formation of simple NLRP for the formation of double PNLRP.

In FIG. 2 shows a model of the structural diagram of the device for the formation of DC PNLRP through the joint use of 2 devices for the formation of simple NLRP with the system control unit, which provides a change in the code forms of simple NLRP.

In FIG. 3 is a functional electrical diagram of one of 2 identical devices for forming codebooks of NLRP (UFKS NLRP) (durations {l _i } = {8, 10, 11, 12, 13, 16}), which contains: block 55 for generating a cyclic sequence characters in the composition: the first multiplexer 1, the delay element 2, the adder modulo two 3, decryption unit 4, consisting of six elements And 5-10 from the first to the sixth, respectively, shifting the register 11; block 12 forming the optimal sequence, consisting of twenty-one element And 14-24, 26-33, 39, 43 from the seventh to the twenty-seventh, respectively, eleven elements OR 13, 25, 34-38, 40-42, 44 from the first to the eleventh accordingly, the second multiplexer 45; control unit 46, consisting of registers 47, 49, 52, counters 53 and 54, OR element 48, key 51 and clock generator 50.

In FIG. 4 shows a functional electric circuit as a whole of the PNLRP SDK forming device, which contains: first 56 and second 63 UFKS NLRP, first 57 and second 62 counters, element 58 I, adder 59 modulo two, system decoder 60 “subspecies” PNLRP, system decoder 61 "types" of PNLRP, - with corresponding links.

Description of the work of UFKS NLRP

In FIG. 5, 6, 7, 8, 9, 10 — truth tables of the UFKS NLRP states and other additional information explaining his work on the formation of NLRP code dictionaries of durations {l _i } = 8, 10, 10 _NI , 11, 12, 12 _{NI are presented} , 13, 16. As can be seen from the values of {l _i }, the NLRP data is generated by one 4-bit shift register, because {l _i } ≤2 ⁿ , n = 4. Following rule (2) for constructing NLRP data of durations, UFKS NLRP generates various automorphisms (cyclic shifts) of the following non-inverse-isomorphic code forms of NLRP of the above durations (see Table 1) in the following 3 modes:

1) the mode of formation of one NLRP of a given code form and duration;

2) the mode of generating code dictionaries from NLRP of one fixed duration;

3) the mode of forming code dictionaries from NLRP of various forms and durations.

1. The mode of formation of one NLRP given code form and duration. At the first clock moment, the NLRP length code is supplied to the information inputs from the first to the fifth third register 52 of the control unit 46 (the length code is the initial state of the second counter 53, which, after the number of counting pulses equal to the length l of the NLRP, will give an overflow pulse, for example , for the duration of the NLRP l = 10 (Fig. 5) this is the code "10101"), the initial phase code for the shift register 11 is supplied to the information inputs of the initial phase code of the control unit 46. These codes are recorded in registers 52 and 47, respectively, according to the “write” clock initially about the state "supplied to the installation input to the initial state of the control unit 46 and then to the first synchronization input of the register 52 and the register 47. At the second clock moment, the“ start of operation "pulse is fed to the start input of block 46, which, passing to the generator start input 50 clock pulses, starts it, and also, passing to the second synchronization inputs of registers 52 and 47, ensures the reading of the NLRP length code from register 52 to counter 53, respectively, and the code of the initial phase from register 47 to shift register 11, and passing through OR 48 at the synchronization input of the counter 53 of block 46 and at the synchronization input of the shift register 11, respectively, records the NLRP length code in the counter 53 (as its initial state) and the initial phase code in the shift register 11, while the initial phase code is received at direct outputs first to fourth shift register 11.

At the same first clock moment, a code is supplied to the decryption inputs of the first multiplexer 1, specifying a signal to be connected to its output from a specific output of element 5 of the decryption node 4 corresponding to a certain duration l of the generated NLRP (for example, durations l = 8, l = 10, l = 11, l = 12, l = 13, l = 16 correspond to the elements And 5, 6, 7, 8, 9, 10). Thus, between the outputs of the shift register 11 and its input of mode V, a linear-nonlinear feedback chain (internal logic function) is formed, consisting of a certain element And 5, 6, 7, 8, 9, 10 of the decryption unit 4, the delay element 2 and adder 3 modulo two, which is responsible for the cyclic repetition of the states of the shifting register 11 through the number of ticks equal to a certain duration l NLRP. At the same first clock moment, an address code of the type NLRP corresponding to the connection to the output of this multiplexer, i.e. the output of the entire device, information from a specific input X _{to the} second multiplexer 45 of the block 12 forming the optimal sequence corresponding to a certain type of NLRP. The type of NLRP determines both its duration l and the noninverse-isomorphic (NLR) transformation of NLRP of a certain duration. As mentioned earlier, one NI conversion is characteristic of NLRP of durations l = 12 and l = 10.

Thus, between the outputs of the shift register 11 and the output of the second multiplexer 45, i.e. the output of the device, a chain of external logic (external logic functions) is formed, consisting of a certain set of elements of block 12 for generating the optimal sequence and responsible for the formation of a certain type of NLRP (X _в ) and a certain cyclic sequence of states of the shift register 11.

In subsequent clock moments, starting from the third, pulses from the clock generator 50 are fed to the input of the shift register 11 and provide a sequential change in its states in accordance with the established function of the internal logic corresponding to a certain duration l NLRP, so that starting from (3 + 1) -th beat of the status of the bits of the register 11 will be repeated. At the same time, the formation of the optimal NLRP of the established duration is ensured by using the corresponding elements of the optimal sequence generating unit 12 that defines the logical function of the external logic corresponding to the established type of NLRP. It should be noted that the functional diagram of block 12 for generating the optimal sequence is minimized, taking into account the repeating common elements of the logical function of external logic (implicant) common to certain types of NLRP. Therefore, the operation of this unit must be considered in light of this remark.

Starting from the 3rd cycle, the pulses from the clock generator 50 are fed to the counter input of the counter 53, and the synchronization of the count is provided by the pulses received at the clock input of the counter 53 from the output of the OR48 element. After l pulses arrive at the input of the counter 53, an overflow pulse will appear at its output, which will go to the output “end of the NLRP” of the control unit 46, signaling that the formation of one NLRP has ended.

This work cycle can be repeated starting from the “3 + l” th clock moment, which is ensured by supplying a “dictionary code code” to the inputs of the dictionary code code of the control unit 46.

2. The mode of formation of NLRP code dictionaries of one fixed duration. The volume of the NLRP dictionary of a certain duration l = const is determined by the number of its auto- and isomorphic transformations. As mentioned earlier, for NLRP with l = 8, l = 11, l = 13, l = 16, there is only one non-inverse isomorphism, the remaining transformations are automorphic and essentially represent cyclic shifts of the non-inverse isomorphism (the number of shifts is equal to l). For NLRP with l = 10 and l = 12, there are two noninverse-isomorphic (NI) transformations corresponding to a change in the fine internal structure of NLRP, namely X _B = {l _{10 NI} } and X _B = {l _{12 NI} }, i.e. . automorphic transformations for X _B = l ₁₀ and X _B = l _{10 NI} , as well as for X _B = l ₁₂ and X _B = l ₁₂ will not be different. Thus, the formation of an NLRP code dictionary of a certain duration will mean the formation of other automorphic transformations for NLRP: X _B = l ₈ , X _B = l ₁₀ , X _B = l _{10 NI} , X _B = l ₁₁ , X _B = l ₁₂ , X _B = l _{12 NI} X _B = l ₁₃ , X _B = l ₁₆ .

Following the truth tables (an example for l = 10 is shown in Fig. 5), for the formation of automorphic NLRPs of a certain duration, it is enough to ensure the beginning of the formation of this NLRP not from the initial initial phase of the shift register 11, which was set at the beginning of the device (i.e. not from the phase corresponding to measure 2 in Fig. 5), and from a phase that corresponds to any intermediate state of the shift register 11 (according to the truth table of Fig. 5, this corresponds to measures from 3rd to “l + 1”). The choice as the initial phase of any intermediate state of the shift register 11 does not violate the cyclicity (with period 1) of its operation, which does not depend on the initial phase selected from the set of values in the truth table for l.

The character of the NLRP dictionary of a certain duration (l = const) will depend on what initial phase is set in the shift register 11 after the formation of a certain (previous) NLRP of a given duration l. Thus, the order of alternation (selection) of the initial phases will determine the form of the generated NLRP dictionary of a certain duration. It can consist only of one constantly formed NLRP, only of 2 constantly formed NLRP, only of 3 constantly formed NLRP, etc. and finally from the "l" NLRP. The more complicated the order of the alternation of the initial phases, the higher the imitostability and cryptographic stability of the NLRP dictionary. Optimal in this sense will be a dictionary constructed on the principle of pseudo-random alternation of NLRP. However, in any particular case, it should be possible to change this order through the operator or an external software control device. This feature is implemented in the inventive device using the control unit 46, which incorporates the principle of storing in the register 47 the intermediate state of the shift register 11 in accordance with the code of the dictionary code. So, for example, at the 1st clock moment, the code of the digit 5 (“00101”) is written to the register 49 through the code input of the dictionary code of the control unit 46. This means that in register 47, after the start of the formation of the first NLRP, the “l-5th intermediate state of the shift register 11 will be stored (so, according to the truth table in Fig. 5 for l = 10 this will be the state“ 0011 ”). Then, after the formation of the first NLRP is completed, this memorized intermediate state will be read from register 47 again into shift register 11, but already as its initial phase. Then the process of forming another NLRP of a given duration will begin, and if by this moment the dictionary cipher code has not been changed, then in the subsequent each "l-5" -th intermediate state of the shift register 11 will be remembered and then read into it as initial phase. It is clear that after l cycles, this alternation order according to the principle “each l-5th phase” will sort through all possible initial phases, as well as any other order of the type “every nth phase”, where n = 1, 2 ..., l. Thus, the number n in the law “every nth phase” lays down the order of alternation of the initial phases, i.e. NLRP alternation order in a dictionary.

In this mode, the device operates as follows. At the first clock moment, a signal is input to the entry record of the initial state of the control unit 46, which is fed to the first synchronization input of register 49 and allows the dictionary cipher code to be written to this register as a binary key digit code (for example, “5” - “00101”) . The same signal, arriving at the first input of the key 51, closes it. At the second clock moment, the “start of operation” clock pulse is fed to the start input of block 46, which is fed to the second input of the key 51 and opens it, and also fed to the second synchronization input of the register 49 and through the OR element 48 to the synchronization input of the counter 54, this ensures reading from the register 49 into the counter 54 of the code of the digit "5" (00101). As described previously for the mode of formation of one NLRP, in this mode, in the 1st and 2nd clock moment, the first multiplexer 1 and the second multiplexer 45, register 52 and counter 53 are prepared in parallel. At the 3rd clock moment, together with by the beginning of the formation of the first NLRP, clock pulses from the clock generator 50 are supplied to the counter input of the counter 53, through the public key 51 to the counter input of the counter 54, and through the OR 48 element, to the synchronization input of the counter 54 and the counter 53. Since 54 was recorded in the counter state “5” (00101), then after (l-5) clock cycles an overflow pulse will appear at its output, which will go to the first input of the key 51 and close it, and will go to the first synchronization input of the register 49 and if the code of the dictionary is changed, it will write another code in the register 49, and when it arrives at the first synchronization input of the register 47, will provide a record of the (l-5) -th intermediate state of the shift register 11. In this case, the arrival of an overflow pulse to the first synchronization input of the register 52 will not change its state, since new information has not been received at the inputs of the NLRP length code of block 46. If the code for the dictionary cipher has not changed, then the state of register 49 at this clock moment will not change. After l clock pulses coming from the clock generator 50, at the (l + 2) th clock moment at the output of counter 53, an overflow pulse will appear, which will go to the second input of key 51 and open it, and also will go to the second synchronization input of register 49 and will ensure the receipt of the code of the dictionary cipher (in this case, the numbers 5) from the outputs of the register 49 to the inputs of the counter 54, and also will go to the second synchronization input of the register 47 and will provide the input from the register 47 of the initial phase code to the inputs of the shift register 11. Thus , in (l + 2) - clock time of forming a first NLRP ends and the entire device is prepared for the subsequent formation NLRP of this dictionary.

From the (3 + l) th clock moment, the formation of NLRP begins, which is determined by the initial phase, which in the (l-5 + 2) th clock moment was an intermediate state of the shift register 11 (as shown earlier in Fig. 5). So, for X _B = {l ₁₀ } it will be NLRP µ = 1001001110. That is, these NLRPs will represent the (l-5) -symbolic left shift of the original NLRP (non-inverse isomorphism) shown in column (X _n ) in FIG. 5.

Thus, the process of forming NLRP will continue according to the previously described principle so that every l cycles a new NLRP will be formed, shifted from the previous NLRP to the left by (l-5) characters.

At the discretion of the operator or at the command of the software of the device as a whole, at any time to the entries of the dictionary cipher code and then to register 49, a new dictionary cipher code (for example, any digit K <l) is submitted, which, after the end of the formation of the current NLRP, will ensure the formation of such an NLRP dictionary , in which each subsequent sequence will differ from the previous one by a shift to the left by (lk) ticks. The process of forming NLRP will be the same as described previously, except that the overflow pulse from the output of the counter 54 will appear after (lk) clock pulses, and accordingly, (lk) -e intermediate state of the shift register 11 will be stored in register 47 after the beginning of the formation of NLRP.

The nature of the generated NLRP dictionaries of fixed duration l = const can be determined during operation by the operator (or by the software of the device as a whole) by changing the code for the dictionary code (digit code k <1) supplied to the inputs of the code for the dictionary code of the control unit 46.

3. The mode of formation of NLRP code dictionaries of various forms and durations. This mode differs from the previous one in that the operator or the software of the device as a whole, according to some predetermined law, during the formation of any NLRP, the codes of new NLRP lengths other than the length of the generated sequence are sent to the inputs of the NLRP length code of register 52 of the control unit 46. In this case, recording synchronization can be carried out forcibly by applying a pulse to the installation input of the initial state of the control unit 46, which then goes to the first synchronization input of the register 52. However, in this case, an arbitrary phase of the state of the shift register 11 will be stored in the register 47, i.e. the law "every nth phase" will be violated, and to restore or change it is necessary to write the code for the dictionary cipher. The synchronization of writing to the register 52 a new code for the length of the NLRP can also be carried out by means of an overflow pulse from the output of the counter 54. The reading of a new code from the register 52 and its writing to the counter 53 is synchronized by the overflow pulse of the counter 53 that appears at its output after the end of the previous NLRP formation. The same overflow pulse, which also appears at the output “end of the NLRP” of the control unit 46, synchronizes the external control software supplying new codes of the NLRP type to the inputs of the second multiplexer 45 and the decryption address to the inputs of the first multiplexer 1. In accordance with the new duration l of the formed NLRP these codes change the structure of the linear-nonlinear feedback chain of the shift register 11 and the optimal sequence generating unit 12 (as described for mode 1). Thus, at the next clock moment, the formation of NLRP of a different duration begins and the continuous formation of NLRP of various lengths l is ensured, that is, the formation of a dictionary of NLRP of various lengths.

Description of the operation of the device as a whole

The device as a whole can operate in 3 modes, which in essence are ensured by the implementation of the corresponding operating modes of the UFKS NLRP:

1) The mode of formation of the same subspecies of the PNLRP recreation center (provided by the 1st mode of operation of both UFKS NLRP - the mode of formation of one NLRP, NLRP-1 and NLRP-2 of a given code form and duration corresponding to the 1st and 2nd UFKS NLRP );

2) The mode of formation of various subspecies of the same type of PNLRP (provided by the second mode of operation of both UFKS NLRP - the mode of formation corresponding to the 1st and 2nd UFKS NLRP, code dictionaries NLRP-1 and NLRP-2 of one fixed respectively l _i and l _j durations);

3) The mode of formation of various subspecies and types of DC PNLRP (provided by the 3rd mode of operation of both UFKS NLRP - the mode of formation corresponding to the 1st and 2nd UFKS NLRP, code dictionaries NLRP-1 and NLRP-2 of various shapes and durations).

The mode of formation of the same subspecies of the DC PNLRP.

In this mode, the 1st and 2nd UFKS NLRP work in their 1st mode - the formation of one NLRP of a given code form and duration, described above.

, отсюда число этих входов равно 12, так как 2¹²=4096>3439). The operation of the device as a whole begins with the submission to its respective inputs of a “PNLRP type code” (the number of these inputs is determined by the number of possible types of PNLRP DCs - V _B = 15, hence the number of these outputs is 4, since 2 ⁴ = 16> 15) and “ PNLRP subspecies code ”(the number of these inputs is determined by the number of possible PNLRP subspecies $$V_{P\mathrm{AT}}^{\Sigma }=3439$$

, hence the number of these inputs is 12, since 2 ¹² = 4096> 3439).

Based on these codes submitted:

1) the PNLRP subspecies system decoder 60 generates “NLRP-1 initial phase code”, “NLRP-1 dictionary cipher code” for the 1st UFKS NLRP and “NLRP-2 initial phase code”, “dictionary cipher code” at its respective outputs NLRP-2 ”- for the 2nd UFKS NLRP, and feeds these codes to the corresponding inputs of the 1st and 2nd UFKS NLRP.

2) system decoder 61 types PNLRP forms:

on their respective outputs “decryption address”, “NLRP-1 length code”, “NLRP-1 type code” for the 1st UFKS NLRP and “decryption address”, “NLRP-2 length code”, “NLRP-type code 2 ”- for the 2nd UFKS NLRP, and feeds these codes to the corresponding inputs of the 1st and 2nd UFKS NLRP;

at their outputs, the “code of the number of NLRP-1” and the “code of the number of NLRP-2”, which are fed to the inputs of the initial state record (p ₁ , p ₂ , p ₃ , p ₄ ), respectively, of the first 57 and second 62 counters. Since the number of “stacking” NLRP-1 and NLRP-2 in the length L of the PNLRP DC is determined by the PNLRP type, this number will be maximum for the PNLRP DC of type 15, duration L = 13 × 16 = 208, equal to 16, hence the number of installation inputs for counters 57 and 62 and is equal to 4, since 2 ⁴ = 16.

After that, the corresponding pulse is received at the input of the “initial state recording” of the device, which passes to the similar inputs of the 1st and 2nd UFKS NLRP.

Based on the received (above mentioned) codes and impulse for the 1st and 2nd UFKS NLRP, the latter carry out the preparatory operations described above (when describing the work of the UFKS NLRP).

At the next moment, a start pulse is received at the “start” input of the device, which passes to the similar “start” inputs of the 1st and 2nd UFKS NLRP, providing the start of the latter's work on generating NLRP-1 and NLRP-2, respectively, according to the above description, and (having passed the elements 48 OR of both UFKS NLRP) it goes to the sync outputs of the 1st and 2nd UFKS NLRP and, accordingly, to the sync inputs (s) of the counters 57, 62, ensuring at that moment writing to these counters respectively the “code of the number of NLRP-1 "And" NLRP-2 number code. " From this moment, the process of generating PNLRP of the corresponding species and subspecies begins, namely:

from the output of NLRP-1 of the 1st UFKS of NLRP and the output of NLRP-2 of the 2nd of UFKS NLRP arrive synchronously (which is provided by the generators 50 of both devices together with the clock pulses to the sync inputs (s) of counters 57, 62) the code sequences of NLRP-1 and NLRP- 2, which respectively arrive at the first and second inputs of the adder 59 modulo two, from the output of which (as the output of the device PNLRP), the PNLRP is output;

at the corresponding moments when the first NLRP-1 of duration l _i and the generation of the first NLRP-2 of duration l _j (together with the last character of these sequences) are finished, an impulse appears on the outputs “end of NLRP” of the 1st and 2nd UFKS NLRP counting inputs (+1), respectively, of counters 57 and 62; from the following, corresponding to l _i and l _j , moments, the generation of the second NLRP-1 and NLPR-2 begins; etc. - until the end of the formation (generation) of PNLRP;

the moment of the end of the PNLRP generation is fixed (coincides) with the moment of the appearance of simultaneously overflow (transfer) pulses from the outputs of the counters 57 and 62, these pulses are fed to the first and second inputs of the element 58 And then to the output “PNLP” of the device. This ends one cycle of the formation of PNLRP. This mode in the next cycle can be repeated from the (3 + L) clock moment when the operator or an external software device supplies the same “PNLRP type codes” and “PNLR subtype codes” to the corresponding inputs of the device and corresponding decoders 61, 60.

The mode of formation of various subspecies and the same type of PNLRP.

In this mode, the 1st and 2nd UFKS NLRP work in their 2nd mode - the formation of NLRP code dictionaries of one fixed duration described above. The operation of the device as a whole in this mode differs from the operation of the device in the previous mode only in that, with each new PNLRP generation cycle, another “PNLRP subspecies code” is supplied to the inputs of the PNLRP subsystem decoder 60 by the operator or an external software device while maintaining the same "Code type PNLRP" to the inputs of the system decoder 61 types PNLRP.

The mode of formation of various subspecies and types of PNLRP.

In this mode, the 1st and 2nd UFKS NLRP work in their 3rd mode - the formation of NLRP code dictionaries of various forms and durations described above. The operation of the device as a whole in this mode differs from the operation of the device in the previous mode only in that, with each new PNLRP formation cycle, the operator or an external software device sends (different from the previous cycle) other "PNLRP subspecies code" and "PNLRP type code" to the inputs system decoders 60 and 61, respectively.

System decoders 60 and 61 (and their circuit diagrams) are constructed, like any other decoders, as combinational circuits (based on compiling switching tables or Boolean truth functions) having (X ₀ , X ₁ , ..., X _n ) input and ( Y ₀ , Y ₁ , ..., Y _m ) output variables n ≠ m. The technical implementation of the decoders is carried out on either the simplest logical elements AND, OR, NOT as pulse parallel multi-stage (or 2-stage) rectangular circuits, or based on the use of read-only memory devices (ROM), or based on the use of a single integrated circuit using a programmable logic matrix (PLM) [13, 14]. The system decoders 60 and 61 are code converters that convert the binary (binary decimal) code generated on the input buses (X ₀ , X ₁ , ..., X _n ) to the binary code on the output buses (Y ₀ , Y ₁ , ..., For _m ), n ≠ m, and their circuit construction can be carried out according to the method described, for example, in [13, 14] on pages 318 ... 324 ([13]) or on pages 403 ... 407 ([14]) .

So, for the system decoder 60 of the PNLRP subspecies, 11 inputs (X ₀ , X ₁ , ..., X ₁₀ ) of the “PNLRP subspecies” that reflect binary codes are the input code buses (X ₀ , X ₁ , ..., X _n ) decimal numbers from 1 to 2 ¹¹ , which allows you to encode V = 3439 different subspecies PNLRP. And as output buses (U ₀ , U ₁ , ..., U _m ), there are two output bus systems (one system for the 1st UFKS NLRP, the other for the 2nd UFKS NLRP), each of these bus systems consists of 2 groups of tires, the first of which (U ₀ , .., U ₃ ), (U ₉ , .., U ₁₂ ) has 4 buses (outputs) and allows you to generate respectively 16 different codes for the initial phase of NLRP-1 and 16 different codes of the initial phase of NLRP-2 (these codes are taken from the truth tables of the NLRP generators shown in Fig. 5 ... 10), and the second of which (U ₄ , ..., U ₈ ), (U ₁₃ , ..., U ₁₇ ) have 5 buses (outputs), the number thereby corresponding 2 ⁵ = 32th possible types, each type is reflected by its code of dictionaries respectively NLRP-1, NLRP-2. Based on these data, a circuit diagram of a system decoder 60 is synthesized.

The system decoder 61 of the PNLRP type has 4 inputs (X ₀ , X ₁ , X ₂ , X ₃ ) as input buses (inputs), which allows us to represent 16 decimal numbers corresponding to 16 types of PNLRP in binary code. The output buses (outputs) are 2 bus systems (outputs) for the 1st and 2nd UFKS NLRP, respectively, each of which consists of 4 groups of output buses (outputs): the first group consists of 4 outputs ( At ₀ , .., At ₃ ) and 4 outputs (At ₂₂ , .., At ₂₅ ), reflecting 16 possible codes for the number of NLRP-1 and NLRP-2 in the PNLRP; the second group consists of 2 outputs (U ₄ , U ₅ ) and 2 outputs (U ₂₀ , U ₂₁ ), which allow generating 4 (by the number of different lengths of NLRP) codes of the form NLRP-1 and 4 codes of the form NLRP-2 ; the third group consists of 5 outputs (U ₆ , ..., U ₁₀ ) and 5 outputs (U ₁₄ , ..., U ₁₉ ), which allow generating 32 length codes, respectively, NLRP-1 and NLRP-2; the fourth group consists of 2 outputs (U ₁₁ , U ₁₂ ) and 2 outputs (U ₁₃ , U ₁₄ ), allowing you to generate 4 possible decryption addresses for the 1st and 2nd UFKS NLRP. Based on these data, the circuit diagram of the decoder 61 is synthesized.

Information sources

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Claims (1)

A device for generating systems of double derivatives of non-linear recurrence sequences (SDL PNRP), comprising a first device for generating code dictionaries of non-linear recurrence sequences (UFKS NLRP), consisting of a block for generating a cyclic sequence of characters (BFTSPS), an optimal sequence forming block (BFOP) and a control unit (BU ), and BFTSPS consists of a decryption node, including the first to sixth elements And, a delay element, an adder modulo two, the first multiplexer a and the shift register, and the information inputs from the first to the fourth BFTSPS are connected respectively to the information inputs from the first to the fourth shift register, the first to fourth direct outputs of which are connected respectively to the direct outputs of the BFTSPS, the synchronization input of which is connected to the synchronization input of the shift register, s the first to fourth inverse outputs of which are connected respectively to the inverse outputs from the first to the fourth BFTSPS, six outputs according to the number of lengths of the NLRP of six elements And the decryption node whose connections are connected to the inputs of the first multiplexer, while the “decryption address” is fed to the other inputs of the first multiplexer, the output of which is connected to the input of the delay element, the output of which is connected to the first input of the adder modulo two, the output of which is connected to the input of the “mode” of the shift register in this case, the control unit has an “start” input and an “initial state record” input, from the first to fifth inputs of the “dictionary code code”, from the first to fourth inputs of the “initial phase code”, and the inputs of the “initial phase code” are combined respectively only with direct outputs from the first to the fourth BFTSPS and connected respectively to the inputs of the mode from the first to fourth second groups of control units, while the control unit contains the first, second and third registers, first and second counters, clock, key and OR element, and inputs “Dictionary code” from the first to fifth of the first group of control units are connected respectively to the inputs of the mode from first to fifth of the first register, the outputs from first to fifth of which are connected respectively to the inputs from first to fifth of the first counter, the transfer output to which is combined with the input of the initial state recording and connected to the first synchronization inputs of the first and second registers, to the first information input of the key, the output of which is connected to the counting input of the first counter, and the input of the "start" of the control unit is also connected to the first input of the OR element, to the start input clock generator, the output of which is connected to the control third input of the key and the second input of the OR element, the output of which is connected to the synchronization input of the first counter and the output of the control unit, mode inputs from the first to the fourth the second second group of which is connected respectively to the inputs from the first to the fourth second register, the outputs from the first to fourth of which are connected respectively to the outputs from the first to the fourth control unit, the inputs of the “NLRP length code” from the first to fifth of which are connected to similar inputs of the “NLRP length code "From the first to the fifth of the third register, the first to fifth outputs of which are connected to the corresponding inputs of the second counter, the output of which is combined with the input of the" start "and connected to the second synchronization inputs of the first, second and of registers, to the second information input of the key, as well as to the output "end of the NLRP" of the control unit, and the input of the "start" of the control unit is also connected to the counting input of the second counter and the second input of the OR element, the output of which is connected to the synchronization input of the first and second counters, In this case, the BFOP consists of the first to eleventh OR elements, from the seventh to the twenty-seventh AND elements and the second multiplexer, and from the first to the fourth direct and inverse outputs of the BFTSPS are connected to the BFOP and the BU so that the first direct output of the BFTSPS is combined from the first m is the input of the "initial phase code" and is connected to the first input of the second register mode of the control unit, to the first input of the first and second elements And the decryption unit of the BFPSPS, to the first input of the seventh, eighth, tenth and twenty-seventh elements And, the third input of the twenty-third element And and the second input of the first element OR BFOP, and the first inverse output of the BFTSPS is connected to the first input of the third, fourth, fifth, sixth, eleventh and twenty-first elements And to the first input of the second element OR BFOP, and the second direct output of the BFPSS is combined with the second input of the "initial phase code" and is connected to the second input of the second register mode of the control unit, and is also connected to the first input of the ninth, twelfth and seventeenth AND elements, as well as the second input of the first, third, fifth, seventh and twenty-first elements AND BFOP, and the second inverse output of the BFTSPS is connected to the first inputs of the fourteenth, fifteenth and eighteenth elements And, as well as to the second inputs of the fourth and tenth elements And, the third direct output is combined with the third input of the initial phase code and connected to the third input the second register mode of the control unit, and is also connected to the second input of the second, twentieth, twenty-sixth AND elements, the first input of the thirteenth AND element, the second input of the ninth OR element, the third input of the third AND element and the third adder input modulo two BFCC, whose third inverse output is connected to the first input of the nineteenth, twenty-second and twenty-third elements of And, to the second input of the sixteenth, seventeenth, twenty-fourth and twenty-fifth elements of And, to the third input of the first, second, fourth and net elements AND BFOP, and the fourth direct output is combined with the fourth input of the "initial phase code" and connected to the fourth input of the second register mode of the control unit, and is also connected to the first input of the twenty-fourth element And, the second input of the eighth, eleventh, thirteenth and eighteenth elements And , the fourth input of the second, third and fourth elements AND BFOP and to the second input of the adder modulo two BFTSPS, the fourth inverse output of which is connected to the first input of the first element OR and the twentieth element And, to the second input the ninth, twelfth, and fourteenth AND elements, as well as the fourth input of the first, fifth, and sixth AND BFOP elements, wherein the output of the first OR element is connected to the second input of the sixteenth AND element, the output of which is connected to the first input of the third OR element, the output of which is connected to the first input of the second multiplexer, the output of the seventh AND element is connected to the second input of the fifth OR element, the output of which is connected to the third input of the second multiplexer, the output of the seventeenth AND element is connected to the first input of the OR element, the output of the twenty-fourth AND element is connected to the second input of the fourth OR element, the output of which is connected to the second input of the second multiplexer, the output of the eighth AND element is connected to the first input of the fourth OR element and to the second input of the fifth OR element, the output of the second OR element is connected to the first input of the twenty-fifth AND element, the output of which is connected to the first input of the sixth OR element, the output of which is connected to the fourth input of the second multiplexer, the output of the ninth AND element is connected to the second input of the third and sixth OR elements, as well as the second input of the twenty-third AND element, the output of the eighteenth AND element is connected to the second input of the second OR element, the output of the tenth OR element is connected to the first input of the twenty-sixth AND element and the seventh OR element, the output of which is connected to the fifth input of the second multiplexer, the output of the eleventh AND element is connected to the second input of the seventh OR element and the nineteenth AND element, the output of which is connected to the first input of the eighth OR element, the output of which connected to the sixth input of the second multiplexer, the output of the twentieth AND element is connected to the second input of the eighth OR element, the output of the twelfth element And is connected to the third input of the eighth OR element and to the first input of the ninth OR element, the output of which is connected to the second input of the twenty-seventh AND element, output of the twenty-first AND element connected to the first input of the tenth OR element, the output of which is connected to the seventh input of the second multiplexer, the output of the thirteenth AND element is connected to the second input of the tenth element nta OR and the fifteenth AND element, the output of the twenty second AND element is connected to the third input of the tenth OR element, the output of the fourteenth AND element is connected to the third input of the ninth OR element and to the second input of the twenty second AND element, the output of the twenty third element And is connected to the second input of the eleventh OR element, the output of the twenty-sixth AND element is connected to the third input of the fourth OR element, the output of the ninth OR element is connected to the second input of the twenty-seventh AND element, the output of which is connected to the first mu input of the eleventh OR element, the output of the fifteenth AND element is connected to the second input of the eleventh OR element, the output of which is connected to the eighth input of the second multiplexer, the other inputs of which receive an “NLRP type code”, and its output is connected to the “NLRP output” of the device, with which the generated simple nonlinear PSP is removed, characterized in that a second identical UFKS NLRP is introduced, a two-input element And, the output of which is the output “PNLRP end” of the device, a two-input adder modulo two, the output of which is the output of the PNLRP device, the system control unit (SBU), consisting of a system type “PNLRP decoder”, a system decoder “subspecies PNLRP” and the first and second counters, the output “NLRP” of the first and the output “NLRP” of the second UFKS NLRP are the corresponding outputs NLRP-1 and NLRP-2 of the first and second UFKS NLRP and are connected respectively to the first and second inputs of the two-input adder modulo two, and the input "start" and the input "record the initial state" of the first and similar inputs of the second UFKS NLRP respectively are connected and connected respectively to the “start” input and the “initial state recording” of the device, and the inputs from the first to the fourth “PNLRP type code” and the inputs from first to eleventh “PNLRP subspecies code” of the device are the corresponding inputs of the “PNLRP type system decoder, respectively "And the system decoder" subspecies PNLRP "and the corresponding inputs of the SBU, the first and second outputs" end PNLRP "which are connected respectively to the first and second inputs of the two-input element And, respectively, to the transfer output per of the second and transfer outputs of the second counters, the counting inputs of which are connected respectively to the inputs “end of NLRP-1” and “end of NLRP-2” of the SBU and to the outputs “end of NLRP” of the first and second UFKS NLRP, respectively, and the synchronizing inputs of the first and second counters are connected respectively, to the first and second synchronizing inputs of the SBU and are connected respectively to the synchronizing outputs of the first and second UFKS NLRP, and are connected respectively to the output of the element OR BU of the first and the output of the element OR BU of the second UFKS NLRP, inputs are “NLRP length code "From the first to the fifth, the inputs" code type NLRP "and the inputs" decryption addresses "which are respectively connected to the corresponding outputs" code length NLRP-1 "from first to fifth," code length NLRP-2 "first to fifth," code NLRP-1 type ”,“ NLRP-2 type code ”and“ NLRP-1 decryption addresses ”,“ NLRP-2 decryption addresses ”of the first“ PNLRP type ”decoder, outputs“ NLRP-1 number code ”from first to fourth and the outputs “NLRP-2 number code” from the first to the fourth of which are connected respectively to the installation inputs from the first to the fourth respectively of the first and the second counters, and the inputs of the “code of the initial phase” from the first to the fourth and the inputs of the “code of the dictionary code” from the first to the fifth of the first and second UFKS NLRP are connected respectively to the outputs “the code of the initial phase of the NLRP-1” from the first to the fourth, “code the initial phase of NLRP-2 "from the first to the fourth and the outputs" code for the dictionary code of the NLRP-1 "from the first to fifth," the code for the code of the dictionary NLRP-2 "from the first to fifth second system decoder of the" PNLRP subspecies ".

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