RU2427885C1 - Quick-acting generator of random shifts and combinations - Google Patents

Abstract

FIELD: information technologies. ^ SUBSTANCE: device comprises a unit of data registers arranged with the possibility of parallel and serial data loading, and a switching matrix with baseline topology. The device comprises n data outputs, formed by outputs of data registers unit, m binary inputs of control signals, to which random signals are supplied from external sources, input S of serial download of initial line of reinstalled data A1 - An, formed by an input of serial downloading of data registers unit, a binary unit to control serial and parallel recording of data into a unit of data registers PE, input of clock pulses of data registers unit clk. Parallel q digit outputs of data registers unit are electrically connected with q digit inputs of the switching matrix, outputs of the switching matrix are electrically connected to parallel q digit inputs of data registers unit. ^ EFFECT: improved device efficiency. ^ 4 dwg

Description

The device relates to computing, information and measuring radio engineering and can be used in information protection systems against unauthorized access.

A device for generating random sequences of bits (see US patent No. 07583155, IPC G06F 7/58). The device consists of an oscillating block, which generates a random sequence of bits when a noise signal is applied to it. The device also includes an integrated circuit for generating a random sequence of bits.

The disadvantage of this device is that in the output stream of random numbers the appearance of identical numbers is possible, which is unacceptable for a generator of permutations of numerical sequences. The device also cannot be used directly to generate random combinations of numerical sequences.

) и i-го разрядов первого регистра сдвига подключены соответственно к первому и второму входам первого сумматора по модулю два, выход k-го и (i+1)-го (где

)разрядов 1-го регистра сдвига подключены соответственно к первому и второму входам 1-го сумматора по модулю два, выход первого сумматора по модулю два соединен с информационным входом одноименного регистра сдвига и с одноименным выходом блока управления, выход каждого регистра сдвига подключен к второму входу одноименного элемента И, выходы элементов И являются выходами генератора.A known generator of an n-digit pseudo-random sequence (see Copyright certificate No. 2081450, IPC G06F 7/58), containing n AND elements, a control unit equipped with n outputs, the first inputs of which are connected to the corresponding outputs of the control unit, n adders modulo two and n shift registers, and the outputs of the jth (where

) and the i-th bits of the first shift register are connected respectively to the first and second inputs of the first adder modulo two, the output of the k-th and (i + 1) -th (where

) the bits of the 1st shift register are connected respectively to the first and second inputs of the 1st adder modulo two, the output of the first adder modulo two is connected to the information input of the same shift register and the same output of the control unit, the output of each shift register is connected to the second input element of the same name AND, the outputs of the elements AND are the outputs of the generator.

With the length of the shift register n, 2 ⁿ unique codes of length n can be obtained, however, they are not random, since, knowing the device of the generator and the current generated code, the remaining codes can be restored.

A known random number generator for electronic applications (see US patent No. 05871400, IPC A63F 9/21). The device contains a generator on shift registers, which uses coefficients of a primitive polynomial of order k to generate random numbers, and a second generator to generate an index of a random number stored in an array of random numbers received from the generator on shift registers.

This generator can be used to form random permutations and combinations with uniform distribution. The disadvantage of this device is the relatively low speed and the need to store random numbers in an array, the size of which can become unacceptably large with an increase in the number of possible permutations.

Known generators of random permutations and combinations described in the monograph Kureychik V.M. and others. “Combinatorial hardware models and algorithms in CAD” / M.: “Radio and communications”. 1990. C.185-203. The disadvantages of the described generators are the relatively slow decline of autocorrelation functions, generated combinations and permutations, low speed when generating uncorrelated random combinations and permutations, the possibility of generating erroneous combinations, a rather complicated design with a large length of generated combinations and permutations.

Closest to the proposed solution is a random number generator (see RF patent No. 2340931, IPC G06F 7/58), containing a pseudorandom sequence generator on a shift register of length n with linear feedback, the output of which is connected to the control unit, an analog noise generator and a shaper pulses, one shaper output is connected to the clock input of the pseudo-random sequence generator, and the second to the control unit, an additional shift register for storing permutations of numbers of length n, data output whose clock input and data input are connected to the control unit, the interface to the non-volatile memory controller, the input and output of which are connected to the control unit.

The disadvantage of this generator is its low speed, since at least 2 ⁿ shift operations and transpositions are required for high-quality data mixing in the shift register for storing permutations of numbers.

The objective of this solution is to create a high-speed generator of random permutations and combinations of numerical sequences to control the permutation in the information stream in order to ensure its confidentiality.

The technical result is a high-speed device that generates random combinations and permutations of the elements of the input set of 2 ^k numbers with a uniform distribution function.

бинарные входы управляющих сигналов переключателей матрицы образуют m бинарных входов управляющих сигналов генератора, каждый переключатель матрицы j-го уровня, где

, расположенный на линии с номером i, электрически соединен одним выходом с входом переключателя j+1 уровня, расположенного на линии с номеромThe problem is solved in that the high-speed generator of random permutations and combinations consists of a block of data registers made with the possibility of parallel and sequential loading of q-bit binary numbers, and a switching matrix, the generator has n q-bit data outputs formed by parallel outputs of the register block data, m binary inputs of control signals for supplying random signals from external sources, input of sequential loading of the initial line of resettable data formed by the serial boot input of the data register block, the binary control input of serial and parallel data recording into the data register block, the clock pulse input of the data register block, and the parallel q-bit outputs of the data register block are electrically connected to the q-bit inputs of the switching matrix, the outputs of the switching matrices are electrically connected to parallel q-bit inputs of the data register block, the switching matrix has n q-bit inputs, n q-bit outputs and with consists of switches arranged in a matrix order along n / 2 lines and k = log ₂ n levels, each switch has two q-bit inputs X1, X2, two q-bit outputs Y1, Y2 and a binary control signal input, the switches implement a logical the function

the binary inputs of the control signals of the matrix switches form m binary inputs of the control signals of the generator, each matrix switch of the jth level, where

located on the line with number i, is electrically connected by one output to the input of the level switch j + 1 located on the line with number

and another output with the input of the switch j + 1 of the matrix level located on the line with the number

,

,

where INT is the function of calculating the integer part of the argument, each input of each level switch j + 1 is connected to one output of the level switch j, the inputs of the first level switches are matrix inputs, the outputs of the kth level switches are matrix outputs.

The invention is illustrated by drawings, figure 1 shows a block diagram of a generator, figure 2 shows a diagram of the digraph of the switching matrix of the generator for the case n = 16, figure 3 shows the diagram of the generator for the case n = 16, figure 4 shows the block diagram generator data registers for the case n = 8, where

1 - block data registers;

2 - switching matrix with baseline topology;

- D ₁ - D _n - parallel q-bit inputs of the data register block and the outputs of the switching matrix;

- Q ₁ - Q _n - parallel q-bit outputs of the data register block and generator outputs;

- S ₁ - S _n - q-bit inputs of the switching matrix;

- C ₁ - C _m - binary inputs of the generator for supplying control signals from external sources of random signals;

- A ₁ - A _n - the initial line of q-bit data loaded into the block of data registers;

- переключатели коммутационной матрицы;-

- switches of the switching matrix;

- PE - binary input control serial and parallel data recording;

S - serial q-bit input of a block of data registers for writing elements of the initial data line A ₁ -A _n ;

- clk - clock input.

Входы управляющих сигналов переключателей матрицы образуют m бинарных входов управляющих сигналов генератора. Выходы переключателей предыдущего уровня соединены с входами переключателей следующего уровня в соответствии с топологией сети baseline. Данная топология описана, например, в патенте US №5175539, МПК H04J 3/00. В соответствии с этой топологией каждый переключатель матрицы j-го уровня, где

, расположенный на линии с номером i, электрически соединен одним выходом с входом переключателя j+1 уровня, расположенного на линии с номеромThe proposed generator consists of a block of data registers 1, configured for parallel and sequential data loading, and a switching matrix with a topology of baseline 2. The generator has n data outputs formed by the outputs of the block of data registers, m binary inputs of control signals to which random signals from external sources, the input S of successive loading initial permutated data line A ₁ -A _n, formed by sequential loading input data register block, the binary input is governed I the serial and parallel writing of data in the data register unit PE, the clock input of the data register block clk. The parallel q-bit outputs of the data register block are electrically connected to the q-bit inputs of the switching matrix, the outputs of the switching matrix are electrically connected to the parallel q-bit inputs of the data register block. Elements of the initial string A ₁ -A _n are binary strings of length q and can be considered as binary digits of q. The switching matrix has n q-bit inputs, n q-bit outputs and consists of switches arranged in a matrix order along n / 2 lines and k = log ₂ n levels. Each switch has 2 q-bit inputs X1, X2, 2 q-bit outputs Y1, Y2 and a binary input of the control signal C. The switches implement a logic function

The inputs of the control signals of the matrix switches form m binary inputs of the control signals of the generator. The outputs of the switches of the previous level are connected to the inputs of the switches of the next level in accordance with the topology of the baseline network. This topology is described, for example, in US patent No. 5175539, IPC H04J 3/00. In accordance with this topology, each j-level matrix switch, where

located on the line with number i, is electrically connected by one output to the input of the level switch j + 1 located on the line with number

and another output with the input of the switch j + 1 of the matrix level located on the line with the number

where INT is the function of computing the integer part of the argument. Each input of each level switch j + 1 is connected to one output of the level switch j. The inputs of the switches of the first level are inputs of the matrix, the outputs of the switches of the k-th level are outputs of the matrix.

The device operates as follows.

Before starting work, the external control computer sets a high logic level at the control input for parallel and sequential recording of the block of data registers PE and, based on the negative changes in clock pulses at the input clk, sequentially writes the elements of the initial data line A ₁ -A _n to the data registers. After that, the control computer sets a low logic level at the control input for parallel and sequential recording of the PE data register block and, based on negative clock pulses at the input clk of the data register block, the generator generates random permutations of the elements of the initial data line A ₁ -A _n at its outputs. Moreover, with the arrival of each new clock pulse at the input clk, new binary random numbers 0 or 1 are supplied to the inputs of the control signals of the generator C ₁ -C _m .

If there are repeating elements in line A ₁ -A _n , random combinations of elements of this line are formed at the generator outputs. If there are no repeating elements, random permutations of the elements of the string A ₁ -A _n are generated at the generator outputs. At the same time, the permutations and combinations formed by this generator have a uniform distribution function.

As a source of random binary signals supplied to the inputs of the control signals C ₁ -C _m , generators described in the book by Ivanov MA, Chugunkova IV can be used "Theory, application and quality assessment of pseudo-random sequence generators." For example, when using a pseudo-random sequence generator on a shift register with linear feedbacks, the data of the bits of the shift register is fed to the inputs C ₁ -C _m . In this case, clk clock pulses are used to clock the generator on the shift register, thus ensuring synchronization with the proposed generator of permutations and combinations.

The block of registers consists of q series-parallel registers of length n. In this case, for example, the K155IR1 registers described in the reference book of V.L.Shilo “Popular Digital Microcircuits” M .: Radio and communication can be used. 1989.S. 107-110. To obtain a register of the required length n, several registers K155IR1 are used. In this case, the parallel output of the last bit of the first register is connected to the serial input of the next register, etc. If the numbers A ₁ -A _n have several digits (q> 1), several n-bit registers are combined into a block in parallel. In this case, the clock inputs of these block registers are interconnected. The parallel load enable inputs PE of these registers are also interconnected. The first digit of the numbers A ₁ -A _n goes to the serial input of the first register, the second to the serial input of the second register, etc., the bit q goes to the serial input of the register with number q. Input S, outputs Q ₁ -Q _n , inputs D ₁ -D _n block of registers have q bits. In this case, the first digit is taken from the first register, the second - from the second, etc. Figure 4 shows a possible connection diagram of six registers K155IR1 block data registers for storing numbers A ₁ -A ₈ having q = 3 digits.

Thus, depending on the external sources of control signals, the proposed generator provides the formation of pseudo-random or random permutations and combinations of the original string from n = 2 ^k numbers A ₁ -A _n . Permutations and combinations at the generator output have a uniform distribution. The generator has high speed, since the transformations are performed in parallel. To obtain any random permutation or combination of the possible ones, it is enough to apply 2 pulses to the clk input, since the serial connection of two switching networks with the baseline topology provides the formation of any input data rearrangement at the output. The hardware complexity of the proposed generator grows almost linearly with increasing n, which makes it possible to obtain random permutations and combinations of long-string elements.

Claims (1)

A high-speed generator of random permutations and combinations, characterized in that it consists of a block of data registers made with the possibility of parallel and sequential loading of data of q-bit binary numbers, and a switching matrix, the generator has n q-bit data outputs formed by parallel outputs of a block of data registers , m binary inputs of control signals for supplying random signals from external sources, the input of sequential loading of the initial line of permutable data, forming input of the serial load of the data register block, a binary input for controlling serial and parallel data recording in the data register block, the clock pulse input of the data register block, and the parallel q-bit outputs of the data register block are electrically connected to the q-bit inputs of the switching matrix, the outputs of the switching matrix electrically connected to parallel q-bit inputs of the data register block, the switching matrix has n q-bit inputs, n q-bit outputs and consists of n reklyuchateley arranged in a matrix manner by n / 2 lines and k = log ₂ n levels, each switch has two q-bit input X1, X2, two q-bit output Y1, Y2, and binary input control signal switches implement the logic function

the binary inputs of the control signals of the matrix switches form m binary inputs of the control signals of the generator, each matrix switch of the jth level, where

located on line number i is electrically connected by one output to the input of the (j + 1) level switch located on line number

, and another output with the input of the switch of the (j + 1) -th level of the matrix located on the line with the number

where INT is the function of calculating the integer part of the argument, each input of each level switch j + 1 is connected to one output of the level switch j, the inputs of the first level switches are matrix inputs, the outputs of the kth level switches are matrix outputs.

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