RU2520390C1 - Apparatus for quantitative estimation of quality indicator - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: apparatus for quantitative estimation of a quality indicator comprises an array of m*n first 1_ij and second registers 6_ij (i=1, …, m, j=1, …, n), n third registers 2_j (j=1, …, n), n first multiplier units 5_j, n second multiplier units 9_j (j=1, …, n), first 10, second 11 and third 12 adders, fourth 15 and fifth 16 register, a clock-pulse generator 17, a third multiplier unit 14, a divider unit 13, first 22, second 23, third 24 and fourth 25 delay elements, first and second array of m*n first 3_ij and second 7_ij AND elements (i=1, …, m, j=1, …, n), n first 4_j and n second 8_j OR elements (j=1, …, n), a third AND element 18, a counter 19, a comparator circuit 20, a decoder 21.

EFFECT: high reliability of the device owing to considerable reduction of hardware costs.

1 dwg

Description

The invention relates to computer technology and can be used to quantify a qualitative indicator, consisting of individual components (factors), in various fields of science, technology and public life.

The technical result is to increase the reliability of the device due to a significant reduction in hardware costs.

This is achieved by the fact that the device contains groups of input registers, input registers, groups of multiplication blocks, groups of accumulative adders, groups of division blocks, accumulative adders, division blocks, an adder, a shift register, an output register, an indication block, a clock generator and a pulse distributor [ one].

Determination of quantitative values of quality will help to obtain objective assessments in solving a number of issues of science, technology and economics. Such a determination can be made as follows.

The quantitative value of the influence of each component (factor) on the qualitative indicator d _ij is determined by experts. The maximum value of one of the component parts (factor) is taken per unit, while it is proposed to use the verbal - numerical Harrington scale [2] as numerical values in each individual case (for orientation to the expert).

Verbal - Harrington Numeric Scale

No. p / p Meaningful Description of Graduations Numerical value one Very high 0.8-1.0 2 High 0.64-0.8 3 Average 0.37-0 64 four Low 0.2-0.37 5 Very low 0,0-02

A quantitative assessment of the values of a qualitative indicator is presented taking into account the competence of the expert. In this case, quantitative estimates of the quality indicator of the factor (fraction) d _{ij are} indicated as a range of values of the Harrington scale (minimum-maximum).

The competence of each expert is established a priori (prior to the survey). The expert estimates are independent random variables that can be added up taking into account correction factors B _j .

The average estimate Pd _{i of} all experts on the i-th factor is determined by the formula

Pd _i = (∑Pd _ij * B _j ) / n, i = 1, ..., m; j = 1, ..., n,

where P _dji is the assessment of the j-th expert of the probability of the influence of the i-th factor (share) on the quality indicator;

B _j - coefficient taking into account the qualification (competence) of the j-th expert.

The average estimate of Pd ₀ for all factors will be equal to

Pd ₀ = (∑Pd _i ) / m, i = 1, ..., m.

It is necessary to determine the maximum and minimum estimates, and then find the average value.

по всем факторам вычисляется по следующей формуле:Maximum average rating $$P{d}_0^{\max }$$

for all factors is calculated by the following formula:

$$P{d}_0^{\max }=\left(\sum \sum P{d}_{ij}^{\max }*Bj\right)/\left(m*n\right)\left(\text{one}\right)$$

- максимальная оценка j-го эксперта вероятности влияния i-го фактора (доли) на качественный показатель.Where $$P{d}_{ij}^{\max }$$

- the maximum score of the j-th expert is the probability of the influence of the i-th factor (share) on the quality indicator.

всех экспертов по всем факторам определяется по следующей формуле:Minimum Averaged Score $$P{d}_{ij}^{\min }$$

All experts on all factors are determined by the following formula:

$$P{d}_0^{\min }=\left(\sum \sum P{d}_{ij}^{\min }*Bj\right)/\left(m*n\right)\left(\text{2}\right)$$

- минимальная оценка j-го эксперта вероятности влияния i-го фактора (доли) на качественный показатель.Where $$P{d}_{ij}^{\min }$$

- the minimum assessment of the j-th expert of the probability of the influence of the i-th factor (share) on the quality indicator.

и $$P{d}_{ij}^{\min }$$

:The final estimate of Pd ₀ value of a quality indicator is defined as the arithmetic mean value $$P{d}_0^{\max }$$

and $$P{d}_{ij}^{\min }$$

:

$$P{d}_0=\left(P{d}_0^{\max }+P{d}_{ij}^{\min }\right)/2\left(\text{3}\right)$$

и $$P{d}_{ij}^{\min }$$

, характеризующие соответственно максимальную и минимальную оценки j-го эксперта по i-му фактору (доле), информационные входы третьей группы входных регистров являются задания входом задания исходной информации, на которые поступают значения b_j, характеризующие коэффициенты квалификации (компетентности) j-го эксперта, информационные входы первого и второго входных регистров являются входами задания исходной информации, на которые поступают соответственно значение k, характеризующее число экспертов, и величина n, характеризующая количество факторов (долей) качественного показателя, выходы первой и второй групп входных регистров соединены с первыми входами соответствующих элементов соответственно первой и второй групп блоков умножения, вторые каждого столбца которых, с первого по k-й, подключены к выходам соответствующих элементов, с первого по k-й, третьей группы входных регистров, выходы каждой строки, с первой по n-ю, первой и второй групп блоков умножения соединены с первым по k-й входами с первого по n-й элементами соответственно первой и второй групп накопительных сумматоров, выходы каждого их которых подключены к входам делимого соответствующих элементов соответственно первой и второй групп блоков деления, входы делителя которых соединены с выходом первого входного регистра, а выходы, с первого по n-й, со входами соответственно первого и второго накопительных сумматоров, выходы которых подключены к входам делимого соответственно первого и второго блоков деления, входы делителя которых соединены с выходом второго входного регистра, а выходы - соответственно с первым и вторым входами сумматора, выход которого через регистр сдвига подключен к информационному входу выходного регистра, выход которого соединен со входом блока индикации.The technical result is achieved by the fact that the device for quantifying a qualitative indicator contains the first and second groups of input registers, each of which consists of k × n elements, the third group of input registers consisting of n elements, the first and second input registers, the first and second groups multiplication blocks, each of which consists of k × n elements, the first and second groups of accumulative adders, each of which consists of n elements, the first and second groups of division blocks, each of which consists of n elements c, the first and second accumulative adders, the first and second division blocks, the adder, the shift register, the output register, the display unit, the clock generator and pulse distributor (RI), the clock input of which is connected to the output of the clock generator, the first output of RI - with the recording inputs of the first, second and third groups of input registers, the first and second input registers, the second output is from reading the first, second and third groups of input registers, the third and fourth outputs are with reading inputs of the first and torogo input registers, fifth and sixth outputs - to the inputs of respectively writing and reading of the output register data inputs of the first and second input registers task groups are inputs initial information values which are supplied respectively $$P{d}_{ij}^{\max }$$

and $$P{d}_{ij}^{\min }$$

, characterizing respectively the maximum and minimum estimates of the j-th expert on the i-th factor (share), the information inputs of the third group of input registers are the job input input job information, which receives the values of b _j characterizing the qualification (competency) of the j-th expert , the information inputs of the first and second input registers are inputs of the initial information, which receive respectively the value of k, which characterizes the number of experts, and the value of n, which characterizes the number of your factors (shares) of a qualitative indicator, the outputs of the first and second groups of input registers are connected to the first inputs of the corresponding elements of the first and second groups of multiplication blocks, the second of each column of which, from the first to the kth, are connected to the outputs of the corresponding elements, from the first to of the k-th, third group of input registers, the outputs of each row, from the first to the n-th, first and second groups of multiplication blocks are connected to the first by the k-th inputs from the first to the n-th elements, respectively, of the first and second groups of cumulative sums tori, the outputs of each of which are connected to the inputs of the dividend of the corresponding elements of the first and second groups of division blocks, the inputs of the divider of which are connected to the output of the first input register, and the outputs, from the first to the n-th, with the inputs of the first and second accumulative adders, respectively, the outputs which are connected to the inputs of the dividend, respectively, of the first and second division blocks, the inputs of the divider of which are connected to the output of the second input register, and the outputs, respectively, with the first and second inputs of the adder, the output to through the shift register it is connected to the information input of the output register, the output of which is connected to the input of the display unit.

A device for quantifying a qualitative indicator (see Fig. 1) contains a group of m ∗ n registers 1 _ij (i = 1, ..., m, j = 1, ..., n), a group of n registers 2 _j (j = 1 , ..., n), a group of elements AND 3 _ij (i = 1, ..., m, j = 1, ..., n), a group of n elements OR 4 _j (j = 1, ..., n), a group of n blocks multiplications 5 _j (j = 1, ..., n), a group of m ∗ n registers 6 _ij (i = 1, ..., m, j = 1, ..., n), a group of elements And 7 _ij (i = 1, ... , m, j = 1, ..., n), a group of n elements OR 8 _j (j = 1, ..., n), a group of n blocks of multiplication 9 _j (j = 1, ..., n), adders 10, 11 and 12, division block 13, multiplication block 14, registers 15 and 16, clock generator (GTI) 17, element 18, counter 19, Hem comparison 20, decoder 21, delay elements 22, 23, 24 and 25, the outputs of devices 26 and 27, the input device 28.

, на регистрах 6_ij хранятся коды значений $$P_{ij}^{\min }$$

, на регистрах 2_j хранятся коды значений b_j, (i=1, …, m, j=1, …, n) (Установочные входы на чертеже из-за его громоздкости не показаны). В результате на выходе блока умножения 14 будет значение кода (2∗m∗n) - это может быть реализовано в известном блоке умножения путем снятия результата с выхода блока 14, сдвинутым на один разряд в сторону старших разрядов.In the initial state, all adders 10, 11 and 12 are in the zero state, the code number m (the number of factors) is written on the register 15, the code number n (the number of experts) is written on the register 16. On registers 1 _ij are stored codes of values $$P_{ij}^{\max }$$

, on registers 6 _ij value codes are stored $$P_{ij}^{\min }$$

, A register 2 _j codes stored values b _j, (i = 1, ..., m, j = 1, ..., n) (Setting inputs in the drawing because of its bulkiness is not shown). As a result, at the output of the multiplication block 14 there will be a code value (2 ∗ m ∗ n) - this can be implemented in the well-known multiplication block by taking the result from the output of the block 14, shifted by one bit towards the higher digits.

A device for quantifying a quality indicator operates as follows (see Fig. 1). The input signal 28 of the device receives a start signal, which is fed to the control input of the element And 18, after which the counting pulses from the output of the generator 17 through the open element And 18 are fed to the counting input of the counter 19. The contents of the counter 19 are then fed to the input of the comparison circuit 20 and the decoder 21.

At the output of the decoder 21, a single signal appears on only one i-th (i = 1, ..., m) from its outputs, corresponding to the code on the counter 19, as well as on the (m + 1) -m output of the decoder 21 after changing the code on the counter 19 for subsequent synchronization of the operation of the device blocks.

с выхода регистра 1_ij и $$P_{dij}^{\min }$$

с выхода регистра 6_ij соответственно. С выходов элемента И 3_ij и элемента И 7_ij коды поступают через элементы ИЛИ 4_j (j=1, …, n) и элементы ИЛИ 8_j на первые входы блоков умножения 5_j и 9_j соответственно. На вторые входы блоков умножения 5_j и 9_j поступает код поправочного коэффициента b_j с выхода регистра 2_j, а на третьи входы - единичный сигнал с (m+1)-го выхода дешифратора 21. Выходы блоков умножения 5_j и 9_j подсоединены к одноименным входам сумматоров 10 и 11 соответственно. На управляющий вход сумматоров 10 и 11 поступает сигнал с выхода элемента задержки 22, который задерживает входной сигнал с (m+1)-го выхода на время надежного срабатывания блока элементов И 3_ij, элемента ИЛИ 4_j и блока умножения 5_j.With the arrival of the next i-th pulse to the input of the counter 19 at the i-th (i = 1, ..., m) output of the decoder 21, a single signal appears, which is fed to the control inputs of the elements And 3 _ij and And 7 _ij (i = 1, ... , m, j = 1, ..., n), the second inputs of which receive values $$P_{ij}^{\max }$$

from the output of register 1 _ij and $$P_{dij}^{\min }$$

from the output of register 6 _ij, respectively. From the outputs of the element And 3 _ij and the element And 7 _{ij, the} codes come through the elements OR 4 _j (j = 1, ..., n) and the elements OR 8 _j to the first inputs of the multiplication blocks 5 _j and 9 _j, respectively. The second inputs of the multiplication blocks 5 _j and 9 _j receive the correction coefficient code b _j from the output of the register 2 _j , and the third inputs receive a single signal from the (m + 1) -th output of the decoder 21. The outputs of the multiplication blocks 5 _j and 9 _{j are} connected to the inputs of the same name adders 10 and 11, respectively. The control input of the adders 10 and 11 receives a signal from the output of the delay element 22, which delays the input signal from the (m + 1) -th output for the period of reliable operation of the block of elements And 3 _ij , element OR 4 _j and multiplication block 5 _j .

When counter 19 reaches the number m, a single signal appears at the output of the comparison circuit 20, which resets the counter 19 to zero, and a second signal appears at the second output of the comparison circuit 20, which is fed to the third input of the And 18 element, thereby stopping the flow of pulses from the output of the generator 17 through the closed element And 18 to the counting input of the counter 19.

In addition, the signal from the mth output of the decoder 21 is fed to the input of the delay element 23, which delays the signal during the reliable operation of the elements 3, 4, 5 and the adders 10 and 11. The signal from the output of the delay element 23 is fed to the input of the delay element 24 and to the control input of the adder 12, to the information inputs of which codes from the outputs of the adders 10 and 11. The code from the output of the adder 12 is supplied as a dividend to the first input of the division unit 13, the divider to the second input of the division unit 13 comes from the output of the multiplication unit 14, and to manager input d arrives delayed signal for the period of reliable switching adder 12 from the output of the delay element 24.

The output of the delay element 24 is also connected to the input of the delay element 25, which delays the input signal for the duration of the reliable operation of the division unit 13, after which the output signal of the device 27 appears at the output of the delay element 25.

The result of the operation of the device is a code from the output 26 of block 13 after the appearance of the signal to end the operation of device 27.

Thus, the technical result of the claimed invention is achieved by technical means (blocks and elements) together with the connections mentioned in the description of the operation of the device. The described device allows you to eliminate bias in solving a number of complex issues of science, technology and economics.

The industrial applicability of the invention is justified by the fact that it can be used in different areas (industries) of production in the quantitative assessment of a qualitative indicator consisting of individual components (factors).

Used sources

1. Patent No. 2448364, cl. G06F 17/00, 2012.

2. Troyanovsky V.M. Mathematical modeling in management. -M .: Russian business literature, 1996.

Claims (1)

A device for quantifying a qualitative indicator, containing matrices of m ∗ n first 1 _ij and second registers 6 _ij (i = 1, ..., m, j = 1, ..., n), n third registers 2 _j (j = 1, ... , n), n first multiplication blocks 5 _j , n second multiplication blocks 9 _j (j = 1, ..., n), first adder 10, second adder 11, third adder 12, fourth register 15, fifth register 16, clock (GTI) 17, a third multiplying unit 14, dividing unit 13, the third register output 2 _j (j = 1, ..., n) is connected to the first input of the first multiplication unit 5 and _j to the first input of the second multiplying unit 9 _j, to yield orogo connected to the same name input of the adder 11, the output of the first multiplication unit 5, _j is connected to the same name input of the adder 10, characterized in that it further includes first delay element 22, a second delay element 23, a third delay element 24 and the fourth delay 25, the first element and the second matrix of m ∗ n first 3 _ij and second elements AND 7 _ij (i = 1, ..., m, j = 1, ..., n), n first elements OR 4 _j (j = 1, ..., n), n of the second elements OR 8 _j (j = 1, ..., n), the third element And 18, the counter 19, the comparison circuit 20, the decoder 21, the output of the GTI 17 is connected to the first input t the second element And 18, the second input of which is connected to the first output of the comparison circuit 20, the second output of which is connected to the first input of the counter 19, the second input of which is connected to the output of the third element And 18, and the output - to the first input of the comparison circuit 20 and to the input of the decoder 21, i-th (i = 1, ..., m) the output of which is connected to the first inputs of the i-th (i = 1, ..., m) of the first elements And 3 _ij and to the first inputs of the second elements And 7 _ij (i = 1 , ..., m, j = 1, ..., n), the output of the fourth register 15 is connected to the second input of the comparison circuit 20 and to the first input of the third block of multiplication 14, you od first register 1 _ij (i = 1, ..., m, j = 1, ..., n) is connected to the second input of first AND 3 _ij, (i = 1, ..., m) the output of first AND 3 _ij connected to the same name the input of the OR element 4 _j (j = 1, ..., n), the output of which is connected to the second input of the first multiplication block 5 _j (j = 1, ..., n), the third input of which is connected to the (m + 1) -th output of the decoder 21, the output of the second register 6 _ij (i = 1, ..., m, j = 1, ..., n) is connected to the second input of the second element And 7 _ij (i = 1, ..., m), the output of which is connected to the input of the same name OR 8 _{j (j} = 1, ..., n), the output of which is connected to a second input orogo multiplying unit 9 _{j (j} = 1, ..., n), the third input of which is connected to the (m + 1) th output of the decoder 21, the control input of the adder 11 is connected via a delay element 22 to the (m + 1) th output of the decoder 21, and the output is to the first input of the adder 12, the control input of which is connected through the delay element 23 to the mth output of the decoder 21, the control input of the adder 10 is connected through the delay element 22 to the (m + 1) -th output of the decoder 21, and the output - to the second input of the adder 12, the output of which is connected to the first input of the division 13, the control input of which connected through the delay element 24 to the output of the delay element 23, and the second input to the output of the third multiplication unit 14, the second input of which is connected to the output of the fifth register 16, the input of the delay element 25 is connected to the output of the delay element 24, and the output of the delay element 25 is the output 27 the end of the device.