RU2249914C2 - Communication system - Google Patents

Abstract

FIELD: communications engineering; broadband systems using serial multifrequency signals.

SUBSTANCE: proposed communication system that can be used for receiving and transmitting digital information functions to transfer message by items of serial multifrequency signals and not by these signals proper; result of reception of message as a whole is not lost from cycle to cycle, rather it is stored so that message decoding conditions are improved with each next cycle. Moreover, counters, switches, AND and OR gates, coders, decoders, comparison unit, threshold signal shaper, flip-flop, delay units, buffer units, distributors, integrators, and majority storages used on receiving and transmitting ends also enable reception and transmission of formalized message in variable delivery time.

EFFECT: reduced message delivery time to point characterized in favorable reception conditions.

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Description

The invention relates to communication systems, in particular, can be used for transmitting and receiving discrete information by broadband systems with sequential multi-frequency signals.

Communication systems with sequential multi-frequency (PMF) signals are also known, also called discrete frequency-modulated (manipulated) signals (see, for example, Okunev Yu.B., Yakovlev L.A. Broadband communication systems with composite signals. - M .: Communication , 1968, p.13, Fig. 1.6; Varakin LE Communication systems with noise-like signals. -M .: Radio and communications, 1985, p.19, 20, Fig. 1.11, 1.12. Zhuravlev VI and synchronization in broadband systems. - M .: Radio and communications, 1986, p.6, fig. 1.3).

The disadvantage of these communication systems is the low speed of information transfer through the use of on-off or M-position information signals of fixed duration.

Of the known communication systems, the closest in terms of the combination of implemented features and the effect achieved by using it is the system described in RF patent No. 2167495, claimed. 12/23/99, registered May 20, 2001

This communication system (prototype) contains on the transmitting side an information sensor, an encoder, information and clock inputs connected respectively to the output and clock input of the information sensor, a series-connected switch, the address inputs of which are connected to the encoder outputs, a serial multi-frequency (PMP) signal generator and an output block, clock generator (TI), pseudo-random permutation generator (PSPER), the first clock input connected to the first output of the TI generator, reference frequency sensor (OCH), M- a channel multiplexer, the address and information inputs of which are connected respectively to the outputs of the PSPPER generator and the outputs of the OCh sensor, while the information inputs of the switch are connected to the outputs of the M-channel multiplexer, the second clock input of the PSPER generator, the clock inputs of the M-channel multiplexer and the OCh sensor are combined and connected to the second output of the generator TI, the third output of which is connected to the clock input of the information sensor, and on the receiving side is an input unit, a filter unit, the information inputs of which are combined are connected and connected to the output of the input unit, a deciding unit whose information inputs are connected to the outputs of the filters, a decoder whose input is connected to the output of the deciding unit, and the output is the output of the system, a TI generator, a PSPER generator, the first clock input connected to the first output of the TI generator , OCh sensor, M-channel multiplexer, the address and information inputs of which are connected respectively to the outputs of the PSPER generator and the outputs of the OCh sensor, while the filter clock inputs, the clock input of the deciding unit and the clock input decoder combined and connected to the third output TI of the generator, the control inputs of the filters are connected to outputs of the M-channel multiplexer, the second input PSPER clock generator, the clock inputs of the M-channel multiplexer and OCH sensor coupled and connected to the second output TI of the generator.

In this communication system, complex (broadband) IF signals are used to increase the noise immunity from intentional interference.

The structural diagram of the prototype is presented in figure 1 (transmitting part) and figure 2 (receiving part), where

1 - information sensor,

2 - encoder

3 - switch

4 - generator of sequential multi-frequency (PMF) signals,

5 - output block,

6, 14 - generators of clock pulses (TI),

7, 15 - generators of pseudo-random permutations (PSPER),

8, 16 - M-channel multiplexers,

9, 17 - reference frequency sensors (OCH),

10 - input unit, 11-1, ..., 11-M filters,

12 is a crucial unit,

13 - decoder.

Reception and transmission in the communication system of the prototype is as follows.

On the transmitting side (Fig. 1), a pseudo-random permutation generator (PPSER) 7, identical to the receiving side generator 15, generates a column of M different K-bit (2 ^k = M) numbers (pseudo-random) over the duration τ of the element of the sequential multi-frequency (PMP) signal permutation of M numbers), which is fed to the address input of the M-channel multiplexer 8, to the information input of which a grid of M reference frequencies from the sensor 9 is fed, for example, by dividing one reference frequency F _op . Depending on the values of M signals (addresses) at the address inputs of the M-channel multiplexer 8 consisting of MK circuits, the signals from the output of the reference frequency sensor 9 are switched to the output of the M-channel multiplexer 8 consisting of M circuits and fed to the information inputs of the switch 3 from M to 1, controlled by address inputs by signals from the output of encoder 2, which, in turn, is controlled by signals from the information sensor 1. In accordance with the reference signal received from the switch 3 to the input of the PMP generator 4, the latter generates an elementary oscillation, which is amplified by power and emitted by the antenna in the output unit 5.

In the next τ -tact, the PPSER generator 7 generates another column of M different numbers at the address inputs of the M-channel multiplexer 8, which again controls the switching of the reference frequencies of the sensor 9 in the M-channel multiplexer 8 and, consequently, the choice of the radiation frequency of the second element of the PMF signal etc. to H (H is the number of elements of the PMP signal), and for the duration of the PMP signal (N cycles), the choice of the reference frequency in the switch 3 is carried out by the same control signal from the output of the encoder 2, which is equivalent to choosing from each current column a pseudo-random permutation of one same line. In other words, the transmission of one of M consecutive multi-frequency (PMF) signals, say the j-th PMF signal, consisting of H elements, is equivalent to the formation of pseudorandom K-bit numbers on the transmitting side of the matrix from MxH:

and selecting from it the jth row defining a sequence of changing frequencies (H values) of the PMP signal. In the literature, matrix (1), which determines the law of frequency change, is called the time-frequency (FW) matrix.

In order to form a binary element of the PMF signal MK for a duration τ of a binary number (pseudo-random permutation of M K-bit numbers), clock pulses from the first output of generator 6, clocking of generator 7 of the PSPER, multiplexer 8 and the reference frequency sensor 9 with a period τ is carried out from the second output of the generator 6, and the start of the information sensor 1 and encoder 2 with a period T = Нτ equal to the duration of the PMP signal is performed by clock pulses from the third output of the generator 6.

A matrix similar to (1) is formed on the receiving side, and since the information symbol (the transmitted row of the FW matrix) is unknown, on each τ-cycle (element) of the PMP signal as reference for filters 11-1, ..., 11-M all M values of the current column are used: for filter 11-1 - the value of a _1D , filter 11-2 - the value of a _2D , ..., filter 11-M - the value of a _MD , D = 1,2 ..., H. In our example (the PMP signal is transmitted, the frequencies of the elements of which are determined by the jth row of the matrix (1)), the filter is 11-j, to which the frequency reference oscillations corresponding to the values of the line a _j1 , and _j2 , ..., a _jH , for H-cycles (the duration of the PMP signal) will accumulate the maximum voltage and the decision block 12, where the filter with the largest signal is determined, will highlight the transmitted information symbol (for example, the number of the j-th line), which after decoding in the decoder 13 will go to the recipient of information .

To synchronize the generator 15 pseudo-random permutations, the M-channel multiplexer 16 and the reference frequency sensor 17, clock pulses from the first and second outputs of the generator 14 are used, as well as on the transmitting side, and the voltage drops of the filters 11-1, ..., 11-M , the output voltage of the decisive unit 12, with a period T = Hτ, is carried out by clock signals from the third output of the generator 14.

A disadvantage of the known communication systems - the prototype and analogues - is the fixed time for message delivery regardless of the diversity in the transmitting and receiving sides of the communication system. In real conditions, the objects on which the receiving devices are installed can be placed (maneuver) from the transmitting center (device) in a wide range of distances and for objects that are located at a relatively close distance from the transmitting side, the reception conditions can be much better than for objects at extreme ranges.

This issue is especially relevant for communication systems in which the transmission (reception) of a message takes a fairly long time; for example, in the UHF range, a standard (formalized) 50-bit message is transmitted within 15 minutes / Jones D.H. Sending signals to submarines. New Scientist, 1985, July, No. 4, pp. 37-41 /.

The aim of the invention is to reduce the time to bring a message to an object in favorable reception conditions (range, weather conditions, etc.).

The structural diagram of the inventive communication system is presented in figure 3 (transmitting part) and figure 4 (receiving part), where

1 - information sensor,

2 - encoder

3 - switch

4 - generator of sequential multi-frequency (PMF) signals,

5 - output block,

6, 14 - generators of clock pulses (TI),

7, 15 - generators of pseudo-random permutations (PSPER),

8, 16 - M-channel multiplexers,

9, 17 - reference frequency sensors (OCH),

10 - input unit

11-1, ..., 11-M - filters,

12 is a crucial unit,

13 - decoder

18, 22, 36, 37 - counter, first, third, second counters,

19 - element And,

20, 21, 39 - first, second keys, key,

23, 38 - the first, second delay blocks,

24 - trigger

25, 34 - the first, second valves,

26, 33 - the first, second buffer blocks,

27 - decoder,

28-1, 28-2, ..., 28-P - integrators,

29-1, 29-2, ..., 29-P - majority drives,

30 is a block comparison

31 is an OR element,

32 - encoder,

35 - threshold signal conditioner.

In the proposed communication system on the transmitting side, the counter 18 installation input connected to the output of the element 19 And; the first key 20 with an information input is connected to a power source, and a control input and output is connected respectively to an output and a control input of an AND element 19; the second key 21 by the control input and output is connected respectively to the output of the counter 18 and the trigger input of the information sensor 1; the combined clock inputs of the counter 18, the element 19 And and the second key 21 are connected to the third output of the generator 6 TI; encoder 2 information input connected to the output of the sensor 1 information; the switch 3, the address inputs connected to the outputs of the encoder 2, through a series-connected generator 4 of sequential multi-frequency (PMF) signals connected to the output unit 5; a pseudo-random permutation generator 7 (PSPER) is connected to the first output of the generator 6 by the first clock input; the address and information inputs of the M-channel multiplexer 8 are connected respectively to the outputs of the generator 7 SSR and the outputs of the sensor 9 reference frequencies (OCH); wherein the information inputs of the switch 3 are connected to the outputs of the M-channel multiplexer 8, the clock inputs of the information sensor 1 and encoder 2, the second clock input of the PSPN generator 7, the clock inputs of the M-channel multiplexer 8 and the RF sensor 9 are combined and connected to the second output of the generator 6 TI; on the receiving side, the information inputs of the filter block 11-1, ..., 11-M are combined and connected to the output of the input block 10, and the outputs of the filters 11-1, ..., 11-M are connected to the information inputs of the decision block 12; the generator 15 PSPER first clock input connected to the first output of the generator 6 TI; M-channel multiplexer 16 address and information inputs are connected respectively to the outputs of the generator 15 SSR and the outputs of the sensor 17 OCh; the control inputs of the filters 11-1, ..., 11-M are connected to the outputs of the M-channel multiplexer 16, the clock inputs of the filters 11-1, ..., 11-M, the clock input of the deciding unit, the second clock input of the generator 15 PSPER, the clock inputs of the M-channel multiplexer 16 and the sensor 17 OCH combined and connected to the second output of the generator 14 TI; the first distributor 25 by the control input is connected to the output of the first counter 22; the first buffer unit 26 signal and code inputs are connected respectively to the signal and code outputs of the first distributor 25; the decoder 27 is connected by a code input and output to the code output of the first buffer block 26 and the input of the decoder 13, the output of which is the system output; the encoder 32 code input connected to the code output of the decisive unit 12; the second buffer unit 33 signal and code inputs are connected respectively to the signal output of the deciding unit 12 and the output of the encoder 32; the second distributor 34 signal, code and control inputs are connected respectively to the signal, code outputs of the second buffer unit 33 and the output of the second counter 37, and the signal and code outputs through the respective integrators 28-1, ..., 28-P and majority drives 29- 1, ..., 29-P is connected to the signal and code inputs of the first distributor 25; block 30 comparison signal input connected to the signal output of the first buffer block 26; a threshold signal driver 35 is connected to the control input of the comparison unit 30 by an output; the third counter 36 clock input combined with the control input of the decoder 27 and connected to the output of block 30 comparison; the second block 38 delay output connected to the installation inputs of the first and third counters 22 and 36; the OR element 31 with the first and second inputs is connected respectively to the output of the third counter 36 and the second output of the decoder 13, and the output is connected to the combined installation inputs of the integrators 28-1, ..., 28-P and the majority drives 29-1, ..., 29-P; key 39 input connected to a power source, and the output connected to the third input of the element 31 OR; the read inputs of the integrators 28-1, ..., 28-P and majority drives 29-1, ..., 29-P are combined and connected to the output of the trigger 24; the first clock input of the trigger 24, the clock inputs of the first counter 22, the first distributor 25, the first buffer unit 26, the decoder 27 and the decoder 13 are combined and connected to the output of the first delay unit 23, the input of which is combined with the second clock input of the trigger 24 and connected to the second output generator 14 TI, which is also connected to the combined clock inputs of the encoder 32, the second buffer unit 33, the second distributor 34 and the second counter 37, while the combined installation input of the second counter 37 and the input of the second delay unit 38 and connected to the third output of the generator 14 TI.

The principle of operation of the proposed communication system is illustrated by cyclograms (cyclogr.) In figure 5 and in General terms is as follows.

Suppose a formalized message (FS) is transmitted with a volume of P characters.

FS transmission in the prototype communication system is carried out during the time T _FS = RT _zn (cyclogram 3), where T _zn = T = Hτ is the transmission time of one sign, τ is the duration of the PMP signal element, N is their number (cyclograms 1, 2). For example, a formalized message (A _k A _j ... A _T ) is transmitted by PMP signals whose element frequencies are set by a set of strings (a _k1 , a _k2 , ..., a _kH ) (a _j1 , a _j2 , ..., a _jH ) ... (a _T1 , and _T2 , ..., a _TH ) from the CV matrices of type (1) (cyclo-group 3), i.e. To transmit one character (s), N elements of the PMP signal are used.

The formalized message is transmitted in the proposed communication system during the time T ′ _FS = Pτ (cyclo. 4), where τ is the same duration of the PMP signal, P is the volume of the FS, i.e. To transmit one character (s), one element of the PMP signal is used. For example, a formalized message (A _k A _j ... A _T ) is transmitted by signals whose frequencies are set by the values (a _k1 , a _j1 , ..., and _T1 ). In the next time interval T ′ _{FS, the FS} is retransmitted, but other frequencies (a _k2 , a _j2 , ..., a _T2 ) and t are used to transmit the same FS (A _k A _j ... A _T ) .d. up to N retransmissions of the FS, and on the receiving side, the reception results of each FS are not destroyed, but stored with subsequent accumulation and attempts to decode the accumulated signals.

Thus, a receiving device located in favorable conditions (for example, at a small distance from the transmitter, no interference, etc.) can correctly receive a message after one or several repetitions, i.e. much earlier than the end of the N cycles of FS transfers.

In more detail, the transmission and reception of signals in the proposed communication system is as follows.

On the transmitting side, the generator 6 generates clock pulses from the second output with a period τ equal to the duration of the signal, and the third output with a period T ′ _FS = Pτ equal to the duration of a formalized message (FS) consisting of P characters. In the initial state, the second key 21 is open and the clock pulses from the third output of the generator 6 are not received to start the sensor 1 information. When the first key 20 is closed (automatically or manually), the voltage of the power source E is supplied to the control input of the 19 And element and the clock pulse from the third output of the generator 6, passing through the 19 And element, opens the first key 20 and resets the counter 18, putting it into account mode clock pulses on the clock input. The signal from the output of the counter 18 closes the second key 21, and the clock pulses from the third output of the generator 6 start the sensor 1, the information from which is transmitted to the encoder 2 and then, after encoding (adding check marks), to the switch 3 with a period τ specified by the clock pulses from the second output of the generator 6, also supplied to the clock inputs of the generator 7 of pseudo-random (PS) permutations, the M-channel multiplexer 8 and the reference frequency sensor 9. On each τ-cycle, the generator 7 substitution permutations generates a column of M different K-bit pseudorandom numbers (pseudo-random permutation), which is fed to the address inputs of the M-channel multiplexer 8 through the parallel outputs MK. To generate 7 MK binary numbers over the duration τ, the generator PS permutation of M K-bit numbers) clock pulses with a period μ << τ are supplied to its first input from the first output of generator 6. The M-channel multiplexer 8 is, for example, M multiplexers (switches) from M to 1, each of which is supplied with K-bit addresses (pseudo-random permutation) from the generator 7, and along the M information inputs, a grid of M reference frequencies is formed in the sensor 9, for example by dividing one reference frequency F _op. Depending on the state of the MK address inputs, the signals from the output of the reference frequency sensor 9 are switched to certain outputs of the M-channel multiplexer 8 and fed to the switch 3 from M to 1, controlled by the K address inputs by signals from the output of the encoder 2. Selection of the reference frequency in the switch 3 depending on the value of the information symbol (modulation rule) is determined by the rule for selecting numbers from the column of permutation PS generated by the generator 7, for example, information sign 1 (or A) corresponds to the first row of the permutation PS, information character 2 (or B) - the second line of the permutation PS, etc. In accordance with the reference signal received at the input of the generator 4, the latter generates an oscillation that is amplified by power and emitted by the antenna in the output unit 5. The information sensor 1 is started by clock pulses from the third output of the generator 6 until the counter 18 counts out the necessary the number of repetitions of the formalized message (in our example H, see cyclogr. 4) and the second key 21 will not open its output signal at the control input. At this, the FS transmission cycle ends before the next closure of the first Lyucha 20.

On the receiving side, generators of 14 clock pulses, 15 substitution substitutions, an M-channel multiplexer 16 and a reference frequency sensor 17, as well as operations of forming a substitution substation column by an oscillator 15 and a reference frequency network at the output of an M-channel multiplexer 16, are identical to the same blocks 6-9 and operations on the transmitting side. The signal received by the antenna is amplified, pre-filtered in the input unit 10 and fed to the information inputs of the tunable filters 11-1, ..., 11-M signals, the control inputs of which are synchronized with the control inputs from the output of the M-channel multiplexer 16 with the output reference signals of the M-channel multiplexer 8 on the transmitting side. In this case, the first filter 11-1 is tuned exactly to that frequency, which is determined, for example, by the first row of the pseudo-random permutation column generated by the generator 15 (7), the second filter 11-2 is tuned to the frequency determined by the second row of the column of permutation PS, etc. d. Thus, the deciding unit 12, to the information inputs of which the signals from the outputs of all tunable filters 11-1, ..., 11-M, receive, selects a signal, for example, the largest signal of that filter whose reference frequency (row of the column of permutation PS) coincides with the reference frequency (column row PS permutation) on the transmitting side. The maximum signal from the signal output of the decision block 12 is fed to the signal input of the second buffer unit 33, the code input of which after encryption in block 32 is supplied with the channel code (number) with the maximum signal. In the simplest case, the M output circuits connecting the deciding unit 12 and the encoder 32 are connected in parallel with the input signal circuits of the deciding unit 12, and the code (channel number), in which the maximum signal value is reached, is determined by the position of this signal, which is encrypted in the encoder 32 in a convenient for further use of the form (for example, in binary or M-ary code). The second buffer unit 33 consists, for example, of two registers, the contents of which - the maximum signal and its code (number) - are synchronously fed via the signal and code output through the second distributor 34, respectively, to integrators 28 and majority drives 29; the first character of the formalized message is in blocks 28-1 and 29-1, the second character is in blocks 28-2 and 29-2, etc. to the Pth character - the last character of the FS. The operation of the second distributor 34 is controlled by the second counter 37 at P positions, and its clocking, like the encoder 32 and the second buffer unit 33, with a period τ equal to the signal duration, is carried out by clock pulses from the second output of the generator 14. The second distributor 34 consists of essentially, from two distributors with common clock and control circuits (from the generator 14 and the second counter 37) and separate inputs and outputs; one of them (signal input) receives maximum signals with their subsequent distribution to integrators 28-1, ..., 28-P, to the other (code input) - codes (numbers) of channels with maximum signals and their distribution to majority drives 29-1, ..., 29-P. Majority drives 29 of the codes arriving at their inputs in D cycles (= 1, 2, ..., Н) - repeats of a formalized message, choose a code that repeats the greatest number of times, or if these codes are different (for example, at the initial repeat steps or in the absence of a signal) - the last code received at the input of the majority drive. For example, in the simplest case, the encoder circuit 32 - the second buffer unit 33 - the second distributor 34 - the j-th majority drive 29-j (j = 1, 2, ..., P) is a continuation of the decider block 12 - the encoder 32, those. consists of M parallel branches, at the outputs of which in the drives 29-j signal counters from 1 to H are installed; the maximum reading of one of the counters on each D cycle (D = 1, 2, ..., N) will be the output signal of the 29-j majority drive. The signals accumulated in the integrators 28 and majority drives 29 through the first distributor 25 are supplied respectively to the inputs of the first buffer block 26, which, for example, like the second buffer block 33, consists of two registers, the contents of which are the maximum signal and its code (number) - is synchronously fed respectively to the signal and code outputs to comparator 30 and decoder 27. In block 30, the maximum signal is compared with the threshold signal generated by driver 35, and if it exceeds A decryptor 27 and a third counter 36 start up. In the decoder 27, the code received from the code output of the first buffer unit 26 is decrypted and fed to the input of the decoder 13, from where the decoded message is transmitted to the output of the system (receiver) to the information recipient. After decoding the message, a reset signal is generated at the second output of decoder 13, which is fed through the 31 element OR to the installation inputs of integrators 28-1, ..., 28-P and majoritarian drives 29-1, ..., 29-P. The reset of the integrators 28 and drives 29 can also be carried out by supplying voltage E to their installation inputs through a closed (manually or automatically, for example, when the receiving device is switched on) key 39 and OR element 31, as well as the output signal of the third counter 36 supplied to the first input of element 31 OR. The voltage drops of the integrators 28 and majority drives 29 by the signal of the decoder 13 are carried out with a period DPτ (D = 1, 2, ..., N) that is a multiple of the duration of transmission (reception) of the entire message, and a signal of the third counter 36 with a period qτ, where q , P is the number of message characters (codograms) providing guaranteed decoding (of signals exceeding the threshold voltage in the comparison unit 30); it can be less than the volume of the codogram P and is determined by a specific method (de) coding. The operation of the integrators 28 and majority drives 29 is clocked by pulses from the second output of the generator 14 supplied to the inputs of the trigger 24 directly and with a delay of half the τ-tact (τ / 2) in block 23. On each τ-tact, the trigger generates an information recording pulse, and in case of reverse transfer (with a delay of τ / 2) - read pulses supplied to the second inputs of integrators 28-1, ..., 28-Р and majority drives 29-1, ..., 29-Р. Pulses delayed in block 23 by a (τ / 2) -tact are also used to clock the first counter 22 at the P positions, the first distributor 25 controlled by the output signal of the counter 22, the first buffer block 26, the decoder 27 and the decoder 13. Reset the second and first, the third counters 37 and 22, 36 with a period Рτ is carried out by applying to their installation inputs clock pulses from the third output of the generator 14, directly and delayed by half of the τ-period (τ / 2) in block 38.

Thus, the use of new units on the transmitting and receiving sides of the proposed communication system — counters, keys, AND, OR elements, an encoder, a decoder, a comparison unit, a threshold signal conditioner, a trigger, delay units, buffer units, distributors, integrators, and majority drives — allows, unlike the prototype, to transmit and receive a formalized message (FS) with a variable message delivery time. By receiving devices installed at objects located at a short distance from the transmitting device or under favorable interference conditions, the FS can be received and correctly decoded after the first transmission, for objects in worse conditions, after several transmissions and, finally, for remote objects, or objects in a severe interference environment, the FS can be taken after the maximum number of repetitions - the same time that is required for the delivery of the FS by the prototype communication system.

A significant difference of the claimed communication system is that the message is transmitted not by successive multi-frequency (PMF) signals, but by its elements, and the result of the transmission (reception) of the entire message from cycle to cycle is not lost, but accumulated, improving the reception (decoding) condition with each subsequent cycle ) messages.

Due to the change of frequencies according to the pseudo-random law, the same information symbol is transmitted from cycle to cycle at a new frequency and the effect of the transmission duration, say, focused on a fixed frequency of the interference, is evenly distributed over the entire message. That is, with a maximum number of message repeats, the reception noise immunity becomes equivalent to the signal reception noise immunity by the prototype system (a system with PMP signals). But under favorable conditions, as already noted, message delivery can be reduced to H times (H is the number of elements of the PMP signal).

The technical implementation of the proposed communication system does not cause fundamental difficulties; since all the blocks introduced into the system can be made on the domestic element base.

Claims (1)

A communication system comprising, on the transmitting side, an information sensor, an encoder, information and clock inputs connected respectively to an output and a clock input of an information sensor, a switch connected in series, address inputs of which are connected to the encoder outputs, a serial multi-frequency (PMP) signal generator and an output unit, a generator clock pulses (TI), a pseudo-random permutation generator (PSPER), the first clock input connected to the first output of the TI generator, a reference frequency sensor (OCH), M-channel m an ultiplexer whose address and information inputs are connected respectively to the outputs of the PSPPER generator and the outputs of the OCh sensor, while the information inputs of the switch are connected to the outputs of the M-channel multiplexer, the second clock input of the PSPER generator, the clock inputs of the M-channel multiplexer and the OCh sensor are combined and connected to the second output of the generator TI, and on the receiving side the input block, filter block, the information inputs of which are combined and connected to the output of the input block, the decisive block, the information inputs to connected to the outputs of the filters, a decoder whose output is the output of the system, a TI generator, a PSPER generator, a first clock input connected to the first output of a TI generator, an OFP sensor, an M-channel multiplexer, whose address and information inputs are connected respectively to the outputs of the PSPER generator and OCH sensor outputs, while the filter clock inputs are combined and connected to the clock input of the deciding unit, the filter control inputs are connected to the outputs of the M-channel multiplexer, the second clock input of the generator PSPER, the clock inputs of the M-channel multiplexer and the OCh sensor are combined and connected to the second output of the TI generator, characterized in that a counter, an And element, a first key connected to the power source by an information input, and a second control input and the output of which is connected respectively with the output of the counter and the trigger input of the information sensor, while the combined installation input of the counter and the control input of the first key are connected to the output of the element And, the control input of which is connected to the output of the first key, and the combined clock inputs of the counter, the And element, and the second key are connected to the third output of the TI generator, the second output of which is connected to the clock input of the information sensor, and on the receiving side the first counter, the first delay unit, trigger, the first distributor, the control input connected to the output of the first counter, the first buffer unit, the signal and code inputs of which are connected respectively to the signal and code outputs of the first distributor, a decoder, code input and output of which is connected respectively, with the code output of the first buffer block and the decoder input, an encoder, the code input of which is connected to the code output of the decision block, a second buffer block, the signal and code inputs of which are connected respectively to the signal output of the decision block and the encoder output, the second distributor, signal, code and the control inputs of which are connected respectively to the signal, code outputs of the second buffer block and the output of the second counter, and the signal and code outputs of the second distributor through the corresponding integrators and majority drives are connected to the signal and code inputs of the first distributor, a comparison unit, a signal input connected to the signal output of the first buffer unit, a threshold signal generator whose output is connected to the control input of the comparison unit, the third counter, the clock input of which is combined with the control input the decoder and is connected to the output of the comparison unit, the second delay unit, the output of which is connected to the installation inputs of the first and third counters, the element IL , the first and second inputs of which are connected respectively to the output of the third counter and the second output of the decoder, and the output is connected to the combined installation inputs of integrators and majority drives, the key connected to the power source by the input, and the output connected to the third input of the OR element, and the integrator read inputs and majority drives are combined and connected to the trigger output, the first trigger input of the trigger, the clock inputs of the first counter, first allocator, first buffer block, decoder and the decoder are combined and connected to the output of the first delay block, the input of which is combined with the second clock input of the trigger and connected to the second output of the TI generator, to which the combined clock inputs of the encoder, the second buffer block, the second distributor and the second counter are also connected, while the combined installation the input of the second counter and the input of the second delay unit are connected to the third output of the generator TI.

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