RU2115162C1 - Message routing network - Google Patents

Abstract

FIELD: multiprocessor computer systems with processors operating synchronously and asynchronously. SUBSTANCE: network has at least three switching centers with adjacent ones interconnected through communication channels; at least one switching center is connected with at least one distant switching center. EFFECT: reduced mean time required for message to pass through network. 4 cl, 33 dwg

Description

 The invention relates to the field of computer engineering, in particular to parallel computer information processing systems and can find application in the construction of multiprocessor computing systems with synchronous and asynchronous operation of processors.

 A known computing system for parallel processing of information (see UK patent 2227341, CL G 06 F 13/38, NKI G 4 A, publ. 25.07.90, N 30), containing at least three nodes, each of which is used for processing the data stream and contains means for routing information between nodes, which makes it possible to reserve a specific data transmission path over a network of nodes. Messages can be transmitted from one source node to a destination node on a reserved path. The use of a path reservation device allows one to reduce the requirements for buffering information in intermediate nodes, reduce the waiting time when transmitting information over a network, and increase the overall speed of information transfer between nodes. This ensures synchronous transmission of messages between nodes.

 Signs of an analogue that coincide with those of the claimed technical solution are as follows: channels, a switching node, which, in particular, contains a router, buffers, a backup device (channel switch).

 The reasons hindering the achievement of the required technical result are that the analogue does not provide a search for data transmission paths and a direct connection between remote nodes, and the routing tools do not imply a search for workarounds when transferring from the source node to the destination node if the necessary main channel is unavailable and reserved data paths. Moreover, remote sites are nodes, at least one of whose coordinates differs by more than one.

 Also known is a parallel computing system for exchanging information between nodes (UK patent 2249243, CL H 04 L 12/56, 12/42, NKI H 4 P, publ. 04.29.92, N 18), which has an improved architecture compared to the system , claimed in British patent N 2227341. This computing system combines at least three nodes. Each node in such a system serves to process information and to route and transfer information between nodes. Host routing tools allow you to reserve a route on the network. In this way, messages can be transmitted from the source node to the destination node along a reserved route. The use of a route reservation system reduces the requirements for buffering information in intermediate route nodes, reduces the waiting time for messages to pass, and increases the inter-node throughput. The exchange of messages between nodes in synchronous mode is carried out using a gating signal, which is modified in nodes by restoring the signal edges in order to reduce the compression of the pulse of the strobe signal.

 The invention of British patent N 2249243 covers a computing system having a plurality of processing nodes interconnected in a binary n-cube. Each node has means for processing information and routing it between nodes of the n-cube. The router receives address information from the processing means and sends it from node to node to build a communication route of information from the source node to the destination node. After the communication route is established, the destination node sends a response along the same route, in the reverse order, confirming readiness for receiving information. Then the transmission of information on the reserved route begins. Upon completion of the transmission of information, the route is released and the channels used by the route become open for communication between other nodes. Each routing facility combines two channels for transmitting information. The first channel is used to transmit information from a node to an adjacent node, and the second one is for receiving from a neighboring node. The transmission of information between nodes is carried out using synchronizing signals transmitted along with the information. Each channel includes means for transmitting information (actual message data and state control information), as well as means for transmitting synchronizing signals to control the sending and receiving of information.

 Signs of an analogue that coincide with those of the claimed technical solution are as follows: channels and a switching node, containing, in particular, a router, buffers, a backup device (channel switch).

 The reasons hindering the achievement of the required technical result are that the analogue does not provide a search for data transmission paths and a direct connection between remote nodes, and routing tools provide the ability to route messages only for a binary N - cube.

 The closest technical solution to the claimed is a network for routing messages (see UK patent 2251356, CL H 04 L 12/56, NKI H 4 K, publ. 30.08.91), including the first network having many nodes, each of which has a routing device, interconnected channels of the first network for routing messages between nodes, and a second network with many nodes, each of which has a routing device, and nodes are connected using channels of the second network for routing messages between nodes. Each router in the second network is connected to at least one of the routers of the first network using Z-channels for routing messages between nodes of each network; the first and second networks are the same size. Means of routing messages are located inside each router of these two networks, while message routing occurs from the source node to the destination node through the channels of the first network and the channels of the second network. If the necessary channel of the first network or the second network is unavailable, routing occurs using the means of routing messages between the first and second network over Z channels.

 In a preferred embodiment of this solution, patent specification 2251356 describes a first multidimensional routing network, denoted A, including a plurality of processing nodes. Each node includes information processing facilities and a route block for routing information (i.e. messages) between network nodes. In order to improve the routing efficiency of messages passing through the circuit in network A, the second multidimensional routing network of route blocks, denoted by B, is connected to network A. Networks A and B have the same topology and dimension. The route block has an X-coordinate and a Y-coordinate in the corresponding network. A route laying unit in specific coordinates in network A is connected to a route laying unit in corresponding coordinates in network B through channels designated Z.

 Networks A and B are two-dimensional dual lattices of nodes. Each node includes a route block, which includes four types of channels for transmitting information.

 The first channel is used to transmit information between the route block and the processor connected to the route block.

 The second channel is used to transmit information between route blocks in the X direction.

 The third channel is used to transmit information between route blocks in the Y direction.

 The fourth channel is used to transmit information between route blocks in the Z direction.

 Messages are transmitted on networks A and B by using the routing information contained in each message.

 Moreover, routing information is used only for the purpose of determining a single route in the X and Y dimensions. Routing in the Z dimension is variable and depends on the invalid channels taking place on the network. Invalid channels are those that are in a busy state, do not exist, or are in a state of failure.

 During the transmission of the message in the X and Y dimensions, if the channel is not immediately provided, a request is made for the Z channel. The request for the X or Y channel and the request for the Z channel are supported until one channel is presented. The message is transmitted to the provided channel, and another request is canceled. If both the requested channels (X or Y) and the Z channel are in a busy state, then the message is blocked and not transmitted to the Z channel.

 The route block is not fixed for routing on the channel until the channel is presented. The normal address routing header does not change when going through the Z dimension. When a message arrives at the route node of the destination node, the message is transmitted to the channel associated with the processor. This adaptive routing method requires the routing unit to check the routing address to determine if a message has arrived at the destination. Such a check is performed whenever a message passes the Z dimension. If there is a transition from the first network to the second and all the desired channels of the second network are invalid, the message will be blocked and will not be transmitted to the Z channel.

 The signs of the prototype, coinciding with the signs of the proposed technical solution, are as follows: channels, a switching node, which, in particular, contains a router.

 The reasons that impede the achievement of the required technical result are that the prototype does not provide a search for data transmission paths and a direct connection between remote nodes, and the routing tools provide a search for workarounds when transferring from the source node to the destination node and, accordingly, adaptive routing only in one coordinate Z-direction.

 The problem to which the claimed technical solution is directed is to reduce the time spent on sending messages while maintaining the functional and technical characteristics of networks of various configurations with automatic routing (both along a given and adaptive route) through the use of both adjacent and remote communications.

 The technical result achieved by using the invention is to reduce the average transit time of messages in the network by introducing connections between remote nodes and to reduce hardware costs by using one router on several channels.

 The invention is illustrated by drawings, where in FIG. 1 shows an example implementation for a four-dimensional network; FIG. 2-4, a network switching unit, in FIG. 5 - router, FIG. 6 is a diagram for determining optimal routes; FIG. 7 - block laying adaptive routes, in FIG. 8 - block laying non-adaptive routes, in FIG. 9 is a programming unit, in FIG. 10 - channel switch, in FIG. 11 - buffer switch, in FIG. 12 is a buffer, in FIG. 13 - output machine, in FIG. 14 - input machine, in FIG. 15 - receiver, in FIG. 16-17 — transmitter, FIG. 18 is a buffer arbiter; FIG. 19 - the arbiter of the router, in FIG. 20 is a comparison diagram, in FIG. 21 is a coding diagram of responses of the adaptive route laying unit, in FIG. 22 is a correspondence table of input and output signals of a response coding scheme; FIG. 23 is a diagram of an encoder, in FIG. 24 is a correspondence table of the input and output signals of the encoder, in FIG. 25 - decoder block laying non-adaptive routes, in FIG. 26 is a coding diagram of responses of a non-adaptive route laying unit, in FIG. 27 - 31 is a flowchart of a router operation algorithm, in FIG. 32 - 33 is an example of message routing on a network.

 Network operation is possible both in synchronous and in asynchronous mode.

An example implementation of the invention is given for a synchronous network built on the basis of a linear N-dimensional lattice with remote connections, which is constructed as follows:
- the required network dimension is set;
- each node of the network is assigned a designation in the form of a sequence of coordinates in the network;
- all adjacent nodes are interconnected;
- Connections between remote nodes are added.

 The number of nodes in the network should be equal to the product of the length of the lattice for each coordinate of the network. Adjacent nodes are nodes that differ by no more than one coordinate and no more than 1. Moreover, the maximum distance between the nodes of the lattice will be equal to the sum of the length of the lattice in each coordinate minus N. Connections between remote nodes of the network can reduce this distance when laying route.

 Each channel of the network consists of two bidirectional channels that operate independently and ensure the transmission of information in the forward and reverse directions. Sources of information are the input and injection channels. All switching nodes operate from one clock frequency (from one synchronization bus).

 The given example of a four-dimensional network for message routing (see Fig. 1) contains many switching nodes, for example, 1.0, 1.1, ..., 1.P,. . . , 1R, etc. Switching nodes are interconnected via communication channels, for example, 2 (1.0, 1.2), 2 (1.2, 1.5), etc.

 In accordance with the measurements of the four-dimensional lattice, four directions are allocated in the network (coordinates X1, X2, X3, and X4), which determine the network dimension and the coordinates of all switching nodes. So, for the reduced network, the dimension is: in the direction X1 - F, where F> 5; in the direction of X2 - 2; in the direction of X3 - 2; in the direction of X4 - 2. The basis of the topology is determined by the communication channels between adjacent switching nodes. So, for example, for switching node 1.0, communication with four adjacent nodes 1.1, 1.2, 1.3, 1.4 in all four directions X. 1, X. 2, X. 3, X.4 is carried out through communication channels 2 (1.0,1.1), 2 (1.0, 1.2), 2 (1.0, 1.3) 2 (1.0, 1.4), respectively.

 The complete topology of the presented network is determined in addition to the described communications by additional communication channels between remote switching nodes. So, for example, communication channel 2 (1.0, 1.P) connects two remote switching nodes 1.1 and 1.P, whose coordinates in the X1 direction differ by more than one.

 In the switching node 1, the input channels 2.1.1, ..., 2.N.1 are connected to the channel inputs and outputs of the adapters of the input channels 3.1, ..., 3.N, respectively (see Figs. 2-4). The inputs of the adapters of the input channels 3.1, ..., Z.N are connected to the outputs of the DO responses of the input automata 4.1, ..., 4.N, respectively. Injection channels 5.1, ..., 5.M are connected to the channel inputs and outputs of the transmitters 6.1,. . ., 6.M, respectively. The RQ request outputs of input automata 4.1, ..., 4.N and transmitters 6.1, ..., 6.M are connected to the buffer arbiter request input group 7, whose EN permission output group is connected to the permission inputs of input automata 4.1, ... , 4.N and transmitters 6.1, ..., 6.M. The group of outputs of the source number NI of the buffer arbiter 7 is connected to the group of inputs of the source number of the buffer switch 8, the group of outputs of the DO response of which is connected to the first inputs of the response of input automata 4.1, ..., 4.N and transmitters 6.1, ..., 6. M The group of outputs of the CS selection of the buffer arbiter 7 is connected to the group of inputs of the choice of the buffer switch 8 and to the inputs of the selection of buffers 9.1, ..., 9.K, the information inputs DI of which are connected to the group of the information outputs of the buffer switch 8, the group of response inputs DO of which is connected with outputs of buffer responses 9.1, .., 9.K, busy outputs WS of which are connected to the input groups of the busy arbiter of buffers 7 and the buffer switch 8. The request outputs RQ of the buffers 9.1, ..., 9.K are connected to the input group of the request of the arbiter of the router 10, the output permission group of which EN is connected to the buffer enable inputs 9.1 , ..., 9.K and a group of buffer switch enable entries 8. The information outputs of the DI buffers are combined and connected to the group of information inputs of the router 11, the group of response outputs DO of which is connected to the groups of response input inputs of the buffers 9.1, ..., 9.K . The acknowledgment information ED of the arbiter of the router 10 is connected to the input of the router 11 of the same name, the lock output LK of which is connected to the lock input of the buffers 10. The outputs of the channel adapters 3.1, ..., Z.N are connected to the information inputs of the input automata 4.1, ..., 4.N respectively. Groups of information inputs of the buffer switch 8 and channel switch 12 are combined and connected to the outputs of the channel adapters 3.1, ..., 3.N and the information outputs of the transmitters 6.1, ..., 6.M. The second inputs of answers DO input automata 4.1,. .., 4.N and transmitters 6.1, ..., 6.N are connected to the group of outputs of the responses of the channel switch 12, the group of inputs of the source number NI of which is combined with the group of inputs of the router 11 of the same name and connected to the group of outputs of the source number of the buffer switch 8. The group of CS selection outputs of the router 11 is connected to the group of channel switch selection inputs 12 and the selection inputs of output automata 13.1, ..., 13.N and receivers 14.1, ..., 14.L. Busy outputs WS of output machines 13.1, ..., 13.N and receivers 14.1, ..., 14. L are connected to the busy input groups of the router 11 and channel switch 12, the group of DO response inputs of which is connected to the outputs of the output channel adapters 15, 1, ..., 15.N and the outputs of the responses of the receivers 14.1, ..., 14.L. The outputs of the adapters of the output channels 15.1 ..., 15.N are connected to the inputs of the DO responses of the output machines 13.1, ..., 13.N. The group of information outputs DI of the channel switch 12 is connected to the inputs of the adapters of the output channels 15.1, ..., 15. N and the information inputs of the receivers 14.1, ..., 14.L, the channel inputs and outputs of which are connected to the recipient channels 16.1, ... , 16.L. The channel inputs and outputs of the adapters of the output channels 15.1, ..., 15.N are connected to the output channels 2.1.2, ..., 2.N.2.

 The network channel is formed by connecting the input channel 2.n.1 of the switching node, for example, 1.0, with the output channel 2.s.2 of the switching node, for example, 1.1, and connecting the output channel 2.s.2 of the switching node 1.0 with the input channel 2. s.1 switching node 1.1.

 In the router (see Fig. 5), the group of information inputs is connected to the groups of information inputs of the comparison circuit 17, the scheme for determining optimal routes 18, the block for laying non-adaptive routes 19 and the block for laying adaptive routes 20, the group of inputs of the optimal routes of which is connected to the group of outputs of the determination circuit optimal routes 18. The output of the comparison circuit 17 is connected to the equality input of the adaptive route routing unit 20, the response output groups of which are combined with the output groups of the same name settings of non-adaptive routes 19, and also are the corresponding outputs of the router 11, the group of inputs of the source number of which is connected to the group of inputs of the source number of the unit for laying adaptive routes 20. The data readiness input of router 11 is connected to the resolution inputs of the blocks for laying non-adaptive 19 and adaptive routes 20 and the programming unit 22, the group of programming outputs of which is connected to the groups of programming inputs of the block for laying adaptive routes 20, comparison schemes 17 and determining the optimum routes 18. The group of busy inputs of the router 11 is connected to the groups of busy inputs of the non-adaptive 19 and adaptive 20 routes, the interlock inputs of which are combined with the interlock output of the router 11 and the interlock output of the programming unit 22, the start input of which is connected to the programming output of the non-adaptive pad routes 19. The first group of outputs for selecting a block for laying non-adaptive routes is connected to the first inputs of the group of elements 21 OR, the second inputs of which are connected to the group Sing out the outputs of the adaptive routing block selection. The outputs of the group of elements 21 OR and the second group of outputs of the choice of block laying non-adaptive routes are outputs of the choice of the router.

 In the scheme for determining optimal routes 18 (see Fig. 6), a group of information inputs is connected to groups of information inputs of mask registers 23.1, ..., 23.N, coordinates 24.1, ..., 24.N, conditions 25.1, ... , 25.N, communications 26.1 ,. .., 26.N and the first inputs of the groups of elements 27.1, ..., 27.N, the second inputs of which are connected to the groups of outputs of the mask registers 23.1, ..., 23.N. The group of programming inputs of the optimal route determination circuit 18 is connected to the recording register entries of the mask 23.1, ..., 23.N, coordinates 24.1, ..., 24.N, conditions 25.1, ..., 25.N, communications 26.1 ,. .., 26.N. The outputs of the groups of elements 2I 27.1,. . ., 27.N are connected to the first groups of inputs of the comparison circuits 28.1, .., 28.N, the second groups of inputs of which are connected to the groups of outputs of the coordinate registers 24.1, .., 24.N. The outputs of the comparison circuits 28.1, ..., 28.N are connected to the first inputs of the elements 29.1, .., 29.N, 2-2-2-I-ZILI whose second inputs are connected to the outputs of the condition registers 25.1, ..., 25 .N. The outputs of the elements 29.1, ..., 29.N are connected to the first inputs of the group of elements OR 30.1, .., З..N, the second inputs of which are connected to the outputs of the communication registers 26.1, .., 26.N. The outputs of the groups of elements 30.1,. ., 30.N OR connected to the inputs of the elements 31.1, .., 31.N, And the outputs of which are the outputs of the circuit for determining optimal routes.

 In the adaptive route laying unit 20 (see Fig. 7), the group of inputs of the optimal routes is connected to the direct inputs of the group of elements 33 AND and the information inputs of the multiplexer 39, the address inputs of which are combined with the inputs of the decoder 32 and connected to the group of inputs of the source number. The group of information inputs of the adaptive route routing unit is connected to the information inputs of the number register 34 and the communications register 35 and with the first input of the AND element 36, the second and inverse inputs of which are connected to the enable and disable inputs of the adaptive route routing unit, the programming input group of which is connected to the inputs register entries 34 numbers and 35 links. The outputs of the group of elements 33 And are connected to the direct inputs of the group of elements 37 And and the inputs of the adder 38. The outputs of the decoder 32 are connected to the inverse inputs of the group of elements 33 I. The outputs of the adder 38 are connected to the first inputs of the comparison circuit 40, the second inputs of which are connected to the outputs of the 34 number register . The outputs of the group of elements 37 AND are connected to the first inputs of the group of elements 41 AND, with the direct inputs of the group of elements 42 AND and the inputs of the element 45 OR.

 The group of employment inputs of the adaptive route laying unit is connected to the inverse inputs of the group of elements 37 AND and the first inverse inputs of the group of elements 43 AND, the second inverse inputs of which are combined with the inverse inputs of the group of elements 42 AND and the second inputs of the group of elements 41 AND and are connected to the outputs of the register 35 links . The outputs of the group of elements 41 AND are connected to the inputs of the priority encoder 47 and the inputs of the element 44 OR. The outputs of the group of elements 42 AND are connected to the inputs of the priority encoder 48. The equality input of the adaptive route laying unit is connected to the third input of the response coding circuit 49, the output group of which is the group of responses of the adaptive route laying unit responses. The outputs of the group of AND elements 43 are connected to the inputs of the OR element 46 and the priority encoder 50. The output of the AND element 36 is connected to the fifth input of the response encoding circuit 49, the first input of which is combined with the direct enable input of the priority encoder 48, the inverse enable input of the priority encoder 50 and connected to output element 45 OR. The output of the multiplexer 39 is connected to the second input of the response encoding circuit 49, the fourth input of which is connected to the output of the comparison circuit 40. The output of the OR circuit 46 is connected to the sixth input of the response encoding circuit 49, the resolution output of which is connected to the resolution input of the decoder 51, the group of outputs of which is a group outputs selection block laying adaptive routes. The outputs of the priority encoders 47, 48 and 50 are combined with the inputs of the decoder 51. The output of the OR element 44 is connected to the resolution input of the priority encoder 47 and the inverse of the resolution input of the priority encoder 48.

 In the non-adaptive route routing block 19 (see Fig. 8), the group of information inputs is connected to the inputs of the decoder 52, the outputs of which are connected to the direct inputs of the group of 53 I elements, the inverse inputs of which are connected to the occupancy group of the non-adaptive route laying block, the blocking input of which is connected with an inverse input of the decoder 52. The outputs of the group of elements 53 And are connected to the inputs of the encoder 54, the readiness output of which is connected to the second input of the response encoding circuit 55 and the resolution enable input of the decoder 56, the outputs of the cat There are two groups of outputs for selecting a non-adaptive route laying unit, the response output group of which is the outputs of the response encoding circuit 55, the first input of which is connected to the ready output of the decoder 52. The output group of the decoder 54 is connected to the input group of the decoder 56. The data ready input of block 19 is connected to the second input of the decoder 52, the programming output of which is connected to the programming output of block 19, the blocking input of which is connected to the third input of the response encoding circuit 55.

 9 In the programming unit 22 (Fig. 9), the start input is connected to the installation input of the trigger 57, the output of which is connected to the inverse reset input of the counter 58 and is the lockout output of the programming unit, the readiness input of which is connected to the counting input of the counter 58 and the enable input of the decoder 59, the remaining inputs of which are connected to the outputs of the counter 58. The outputs of the decoder 59 are a group of programming outputs of the programming unit. The reset input of the trigger 57 is connected to the last output of the decoder 59.

 In the channel switch 12 (see Fig. 10) the group of inputs of the source number is connected to the information inputs of the registers 60.1, ..., 60.N + L, the recording inputs of which are connected to the group of inputs of the choice of the channel switch, the group of information inputs of which are connected to the information inputs of multiplexers 61.1,. .., 61.N + L. The group of channel switch response inputs is connected to the information inputs of demultiplexers 62.1, ..., 62.N + L; The nth busy input of the channel switch busy input group is connected to the resolution inputs of multiplexer 61. n and demultiplexer 62.n, the address inputs of which are connected to the outputs of register 60.n. The outputs of the multiplexers 61.1, ..., 61.N + L are the group of information outputs of the channel switch, the group of outputs of the responses of which are the outputs of the elements OR 63.1, .., 63.N + L, the k-th input of the element 6З.n OR is connected to nth demultiplexer output 62.k.

 In the buffer switch 8 (see Fig. 11), the group of inputs of the source number is connected to the information inputs of the registers 64.1, ..., 64.K, the recording entries of which are connected to the group of inputs of the selection of the buffer switch, the group of information inputs of which are connected to the information inputs of multiplexers 65.1, ..., 65.K. The group of buffer switch response inputs is connected to the information inputs of demultiplexers 66.1, .., 66.K; The k-th busy input of the group of busy inputs of the buffer switch is connected to the resolution inputs of the multiplexer 65.k and the demultiplexer 66.k, the address inputs of which are connected to the outputs of the register 64.k. The outputs of the multiplexers 65.1, ..., 65.K are the group of information outputs of the buffer switch, the group of outputs of the responses of which are the outputs of the elements OR 67.1, ..., 67.N; The k-th input of the OR element 67.n is connected to the nth output of the demultiplexer 66.k. The permissions of the buffer switch are connected to the inputs of the resolution of the buffer elements 68.1, ..., 68. K, the combined outputs of which are the outputs of the source number of the buffer switch. The information inputs of the buffer element 68.k are connected to the outputs of the registers 64.k.

 In the buffer 9 (see Fig. 12), the selection input is connected to the installation input J of the buffer busy trigger 69, the output of which is the output of the buffer 9 busy. The buffer enable input is connected to the installation input J of the reset enable trigger 70 and to the register write permission E response, the information inputs of which are a group of inputs of the response of buffer 9. The inputs of the OR element 72 are connected to the outputs of the response register 71 and the reset enable trigger 70, the output of the OR element 72 is connected to the reset inputs To the buffer busy triggers 69 and the reset enable 70. The clock inputs of the triggers 69 for buffer occupancy and 70 for reset enable, registers 71 for response and 73 for information are connected to the synchronization bus. The information input DI of the buffer 9 is connected to the information input of the information register 73, the reset input R of which is connected to the enable input of the buffer 9, which is also connected to the enable input E of the buffer element 74, the information inputs D of which are connected to the outputs of the information register 73, the high-order output of which is connected with its shift resolution input E, it is the output of the buffer request 9, the information outputs of which are connected to the outputs of the buffer element 74. The response output of the buffer 9 is connected to the output of the highest order register 71 response.

 In the output automaton 13 (Fig. 13), the selection input is connected to the installation input J of the trigger 75, the output of which is the output of the output automaton 13, the response input of which is connected to the input D of the shift register 76, the clock input C of which, as well as the clock input of the trigger 75 connected to the network synchronization bus. The outputs of the shift register 76 are connected to the inputs of the response decoder 77, the output of which is connected to the reset input K of the trigger 75 and the reset input R of the shift register 76.

 The information input of the input machine 4 is connected to the input of the installation J of the trigger 78 of the request (see Fig. 14), the output of which is the output of the request of the input machine, the input of which is connected to the input of the installation J of the trigger 79 of employment, the output of which is connected to the reset input R of the trigger 78 request. The first input of the response of the input automaton 4 is connected to the input D of the register 80, as well as to the first input of the buffer response decoder 81, the remaining inputs of which are connected to the outputs of the register 80, the reset input R of which is connected to the second output of the buffer response decoder 81. The second input of the response of the input automaton is connected to the input D of the register 82, as well as to the first input (of the channel response decoder 83, the remaining inputs of which are connected to the outputs of the register 82, the reset input R of which is connected to the second output of the channel response decoder 83. Clock inputs C of triggers 78 and 79 and registers 80 and 82 are connected to the network synchronization bus.The first outputs of the decoders 81 of the buffer responses and 83 of the channel responses are connected to the inputs of the OR element 84, the output of which is connected to the reset input R of the trigger 79 of the employment. S THE an output of OR 85, whose inputs are connected to the enable input of the input machine 4 and the first outputs of the registers 80 and 82.

 In the receiver 14.l (see Fig. 15), the information input is connected to the input D of the data register 86, the outputs of which are connected to the inputs of the buffer element 87, the outputs of which are the information outputs of the recipient channel 16. l. 1. The senior bit of the data register 86 is connected to the input E of the data register 86 and the input S of the trigger request 88 of the channel, the output of which is the output of the requirements of the recipient channel 16. l.2. The input 16.l.3 of the recipient channel is connected to the inputs E of the recording permission and D2 of the information register 89 of the response, with the reset input R of the trigger 88, the input E of the output of the buffer element 87. The input 16.l.4 of the last cycle of the recipient channel is connected to the input D0 the response register 89 and the installation input J of the channel reset trigger 90, whose inverse output is connected to the input of the OR-NOT element 91, the remaining inputs of which are connected to the outputs of the response register 89, the oldest of which is connected to the reset enable input R of the data register 86, and is also out m of the response of the receiver 14.l, the selection input of which is connected to the installation input J of the busy trigger 92, the output of which is the busy output of the receiver 14. l, and the inverse output is connected to the reset input K of the channel reset trigger 90. The output of the element 91 is OR NOT connected to the reset input K of the busy trigger 92. At the inputs D1 and D3 of the register 89 of the response is the level of logical zero. The clock inputs of the data registers 86 and 89 response and triggers 90 reset channel and 92 busy connected to the synchronization bus of the switch.

 In the transmitter 6.m (see FIGS. 16 and 17), the information inputs 5.m.1 of the injection channel 5.m are connected to the information inputs of the data register 93, the recording permission input C of which is connected to the injection channel 5.m.2 of the injection channel 5.m. The logic zero level is supplied to the input D0 of the multiplexer 94, the logic unit level is to the input D1, the remaining D inputs of the multiplexer 94 are connected to the outputs of the data register 93. The outputs of the counter 95 are connected to the address inputs of the multiplexer 94 and the inputs of the decoder 96, the output of which is connected to the inverse input E1 of the resolution of the counter 95 and the inputs E of the resolution of the register 97 of responses and decoder 98 of the responses. The first and second inputs of the responses of the transmitter 6.m are connected to the inputs of the OR element 99, the output of which is connected to the D input of the response register 97, the outputs of which are connected to the inputs of the response decoder 98. The reset inputs R of the counter 95 and the register 97 of the responses are connected to the output of the OR element 100, the first, second, third, fourth and fifth inputs of which are connected to the first, second, third, fourth and fifth outputs of the decoder 98 of the responses, respectively. The information output of the transmitter 6. m is connected to the output of the OR element 101, the first input of which is connected to the output of the multiplexer 94, the second, third and fourth inputs to the third, fourth and fifth outputs of the response decoder 98, respectively, and the fifth input to the output of the AND element 102 the first input of which is connected to the input of the recording 5.m.2 injection channel 5.m.

 The inputs of the OR element 103 are connected to the second, third, and fifth outputs of the response decoder 98, and the output is connected to the input of the J trigger 104, whose inverse output is connected to the second input of the 105 AND gate, the output of which is connected to the input of the J trigger 106, whose output is 6.m transmitter request output The reset inputs K of the flip-flops 104 and 106 are connected to the enable input of the transmitter 6.m. The first input of the AND element 105 is connected to the output of the OR element 101. The inputs of the OR element 107 are connected to the first and second outputs of the response decoder 98, and the output to the input of the installation J of the trigger 108, the reset input K of which is connected to the input of the recording 5.m.2 of the injection channel 5. m, output 5.m.3 of the requirement the channel of which is the trigger output 108. The inputs of the OR element 109 are connected to the enable input of the 6.m transmitter and the output of the 99 OR element, and the output is to the zero input of the multiplexer 110, the first input of which is connected to the recording input 5.m.2 of the injection channel, and output - with installation input J of trigger 111, the reset input of which is connected n with the output of the decoder 96, and the output with the input E2 of the resolution of the counter counter 95. The inputs of the element 112 are connected to the first output of the decoder 98 of the responses and the outputs D0 and D1 of the data register 93, and the output is connected to the installation input J of the trigger 113, the reset input K which is connected to the second output of the decoder 98 responses. The output of trigger 113 is connected to the address input of multiplexer 110, and the inverse output is connected to the second input of element 102 I. The clock inputs from counter 95, register 97 of responses and triggers 104, 106, 108, 111, and 113 are connected to the network synchronization bus.

 In the arbiter 7 buffers (see Fig. 18), the request inputs are connected to the inputs of the encoder 114 and the OR element 115. The busy inputs of the arbiter 7 buffers are connected to the inputs of the encoder 116 and the OR element 117. The outputs of the OR elements 115 and 117 are connected to the inputs of the AND element 118, the output of which is connected to the resolution inputs of the decoders 119 and 120. The outputs of the encoder 114 are the outputs of the source number of the arbiter 7 buffers; in addition, they are connected to the inputs of the decoder 119, the outputs of which are the outputs of the permission of the arbiter 7 buffers. The outputs of the encoder 116 are connected to the inputs of the decoder 120, the outputs of which are the outputs of the selection of the arbiter 27 buffers.

 In the arbiter 10 of the router, the request inputs are connected to the inputs of the encoder 121 and to the information inputs of the multiplexer 122 (see Fig. 19), the output of which is the confirmation output of the information of the arbiter 10 of the router, and is also connected to the enable input of the decoder 124. The lock input of the arbiter 10 of the router is connected with the input permission entries register-latch 123, the inputs of which are connected to the outputs of the encoder 121. The outputs of the register-latch 123 are connected to the inputs of the decoder 124, the outputs of which are the outputs of the permission of the arbiter 10 route isator. The address inputs of the multiplexer 122 are connected to the outputs of the latch register 123.

 The information inputs of the comparison circuit 17 of the router 11 are connected to the inputs of the register 125 (see Fig. 20) and the inputs A of the comparison element 126. The outputs of the register 125 are connected to the inputs B of the comparison element 126, the output A = B of which is the output of the comparison circuit 17 of the router 11. The programming input of the comparison circuit 17 is connected to the write input of the register 125.

 The inputs of the inverters 127, 128, 129, 130 and 131 (see Fig. 21) are connected to the first, second, third, fourth and fifth inputs of the response encoding circuit 49, respectively. The inputs of the And element 132 are connected to the outputs of the inverters 127, 128, 129 and the fourth input of the response encoding circuit 49. The inputs of the And element 133 are connected to the first input of the response encoding circuit 49 and the output of the inverter 129. The inputs of the And element 134 are connected to the outputs of the inverters 127, 128, 129 and 130 and the sixth input of the response encoding circuit. The inputs of the element 135 are NOT connected to the outputs of the inverter 129 and the elements 132, 133 and 134 I. The fifth input of the response encoding circuit 49 is connected to the second inputs of the elements 136, 137 AND, the first inputs of which are connected to the outputs of the elements 133, 134 AND, respectively. The output of the resolution of the response encoding circuit 49 is the output of the OR element 138, the inputs of which are connected to the outputs of the elements 136, 137 I. The inverse input of the resolution of the buffer element 139 is connected to the output of the inverter 131. Logical "1" is applied to the first input of the buffer element 139. The second, third, and fourth inputs of the buffer element are connected to the outputs of the inverter 129, the And element 132, and the OR-NOT element 135. The outputs of the buffer element 139 are the outputs of the response of the response encoding circuit 49.

 One embodiment of the encoders 114, 116 used in the arbiter 7 buffers, priority encoders 47, 48 and 50 used in the adaptive route routing unit 20, the encoder 54 of the non-adaptive route routing unit 19 and the encoder 121 used in the arbiter 10 of the router are shown in FIG. . 23 for the case when the number of inputs of the encoder is seven. The fourth, fifth, sixth and seventh inputs of the encoder are connected to the inputs of the element 140 OR. The first, second and third inputs of the encoder are connected to the first group of inputs of the multiplexer 141, the second group of inputs of which are connected to the fifth, sixth and seventh inputs of the encoder. The inputs of the OR element 142 are connected to the second and third outputs of the multiplexer 141, the address input of which is connected to the output of the OR element 140. The first and third outputs of the multiplexer 141 are connected to the first and second inputs of the multiplexer 143, the address input of which is connected to the output of the OR element 142. The inverse and direct inputs of the encoder enable are connected to the inverse and direct inputs of the AND element 144, respectively, the output of which is connected to the enable input of the buffer element 145, the inputs of which are connected to the outputs of the multiplexer 143 and the OR elements 142 and 140. The outputs of the encoder are the outputs of the buffer element 145.

 The ready output, which is used to construct the encoder 54 of the non-adaptive route laying unit 19, is the output of the OR element 146, the inputs of which are connected to the outputs of the multiplexer 143 and the OR elements 142 and 140.

 The decoder 52 of the block 19 laying non-adaptive routes (see Fig. 25) contains, for example, an inverter 147 connected to one of the information inputs of the decoder 52, an element 148 And, the inputs of which are connected to the output of the inverter 147 and the readiness inputs and lock of the decoder 52, and a decoder 149, the resolution input of which is connected to the output of the element 148 I. The inputs of the decoder 149 are connected to the information inputs of the decoder 52, the readiness output of which is connected to the output of the inverter 147. The first N outputs of the decoder 52 are the first M outputs of the decoder torus 149. (N + 1) th output of the decoder 149 is connected with the rest of M outputs of the decoder 52. (N + 2) th output of the decoder 149 is the output of programming decoder 52.

 The response encoding circuit 55 of the non-adaptive route laying unit 19 contains an OR element 150 (see FIG. 26) whose inputs are connected to the first and third inputs of the response encoding circuit 55 of the OR-NOT element 151, the inputs of which are connected to the second and third inputs of the encoding circuit 55 responses, and a buffer element 152, the outputs of which are the outputs of the response of the response encoding circuit 55. The output of the OR element 150 is connected to the enable input of the buffer element 152, the second and third inputs of which are connected to the output of the OR element 151. Logic “1” and “0”, respectively, are supplied to the first and fourth inputs of the buffer element 152.

 In FIG. 32 and 33 show routing networks constructed respectively on the basis of the prototype and on the basis of the claimed invention and having the same dimensions. In both networks, the dotted lines show the communication channels that are in a busy state when setting the task of routing messages from the source node to the destination node.

To plot a route on the network (see Fig. 1), the control information contained in the first words of the message (packet) is used. There are two possible ways to control network switching:
- non-adaptive, when each word that controls information clearly indicates the direction of further transmission of the packet at each node;
- adaptive, in which the control information contains only the destination address of the message (the transmission direction in each intermediate node is selected based on the destination address and the availability of free channels in the node).

 A special case of control information is the programming of the router 11 (Fig. 2-4).

 Consider the operation of the router 11 in accordance with its algorithm of operation (see Fig. 27 - 31).

 In the initial state, the router 11 expects information about the availability of data (steps 153 and 154).

 When the data is ready (step 155), the control information is analyzed (steps 156, 157, 158).

The resulting code may contain:
- adaptive address (step 159);
- non-adaptive address (step 160) or
- router programming command (step 161).

 If a programming command is received (step 161), the router 11 sets the lock signal (see Fig. 5), sets the counter 58 (see Fig. 9) to "1", and the response "Send the next word" is generated (step 162). After that, data is expected to arrive (steps 163 and 164).

 Upon receipt of the next data code (step 165), one or more registers 23, 24, 25, 26 (see Fig. 6), 34, 35 (see Fig. 7), 125 (Fig. 20) are programmed in accordance with counter state 58 (see FIG. 9).

 In this case, the counter 58 (Fig. 9) is incremented by "1" and the response "Transfer the next word" is formed (step 166).

 After that, it is checked (by the new value of counter 58) whether all registers 23, 24, 25, 26 (see Fig. 6), 34, 35 (see Fig. 7), 125 (Fig. 20) are programmed (step 167 )

 If all the registers are programmed (step 169), then the lock signal is canceled (step 170), and the router 11 enters the initial state (step 153). Otherwise, programming continues from step 163.

 If a non-adaptive address is received (step 160), then the need for routing to the nth output channel is checked (step 195) (Fig. 4).

 If yes (step 197), then it is checked whether the required output channel 2.n.2 is free (Fig. 4) (step 198).

 If the required output channel 2. n.2 (Fig. 4) is free (step 199), then the router 11 paves the requested route and generates the answer "Send the next word" (step 200); otherwise (step 201), the response “Repeat routing in this node” is generated (step 202). If the non-adaptive address sets the route to the recipient channel 16.l (Fig. 4) (step 196), then it is checked whether there is at least one free recipient channel (step 203). If there is a positive answer to this question (step 204), the router 11 paves the requested non-adaptive route and generates the answer "Send the next word" (step 205). Otherwise (step 206), the response “Repeat routing in this node” is generated (step 207).

 If an adaptive address is received (step 159), it is checked whether the destination node of the message has been reached (step 171), and if yes, the response "Send the next word" is generated (step 174), and if no, an adaptive routing is attempted (step 172).

 The presence of a free optimal channel associated with a remote node is checked (step 175). If there is one (step 176), the message is switched to this channel and the response "Repeat word transmission" is generated (step 177).

 If there is no such free channel associated with the remote node, the presence of the free optimal channel associated with the adjacent node is checked (step 178) and switching to this channel is carried out and the response “Repeat word transmission” is generated (steps 179 and 180).

 If there are no optimal free channels (step 181), it is checked whether the channel through which the message arrived is optimal (step 182). If the channel through which the message arrived is optimal (step 183), the response “Repeat routing in the previous node” is generated (step 184).

 If the channel through which the message arrived is not optimal (step 185), then the number of measurements on which the coordinates of the destination node are not reached is checked (step 186). If there are more such coordinates, the specified number in the preferred application is more than one (step 187), the response “Repeat routing in this node” is generated (step 188), i.e. the expectation of the release of one of the optimal channels is realized.

 If none of the conditions of steps 175, 178, 182, 186 is fulfilled (step 189), the presence of at least one free channel associated with the adjacent node is checked (step 190). If such a channel is located (step 191), an attempt is made to lay a non-optimal route: a message is switched to this channel and "Repeat word transmission" is formed (step 192).

 If it is impossible to lay a non-optimal route (step 193), the response “Repeat routing in the previous node” is generated (step 194).

 After the responses are generated in steps 174, 177, 180, 184, 188, 192, 192, 194, 200, 202, 204 and 207, the router 11 returns to its initial state (step 153).

 Consider sending a message from node 1.2 to node 1.P.

 Node 1.2 has coordinates (0,1,0,0), node 1.P has coordinates (P, 0,0,0). Accordingly, to transmit a message, it is necessary to go through one channel in the direction of X2 and P channels in the direction of X1. However, there are communication networks with remote nodes that can reduce the number of channels used to transmit a message. In our example, to send a message from node 1.2 to node 1.P, you can use channels 2 (1.0, 1.2), 2 (1.0, 1.1) and 2 (1.1, 1. P) in series. Laying such a route can be carried out by non-adaptive routing, setting the direction of message transmission for each node in a predetermined direction, i.e. defining both intermediate nodes and channels.

 When a lot of messages are transmitted in the network, determining the route in a preselected direction is not possible, since the workload of the intermediate nodes in the network is unknown. In this case, adaptive routing is applied. Then, channel 2 (1.0, 1.2) or 2 (1.2, 1.5) can be selected in node 1.2, since both of these channels transmit messages to a node whose distance from node 1.P is less than from node 1.2. Thus, in each node, the transmission direction is selected via free channels to the node that is closer to the destination node. If a node has channels associated with remote nodes that meet the minimization criteria, then these channels are used in the first place. So, the message sent from node 1.2. to node 1. P on channel 2 (1.2, 1.5) in node 1.5 will be directed to channel 2 (1.5, 1.6), if this channel is free.

 Thus, a message from node 1.2 to node 1.P in adaptive routing can be transmitted on channels 2 (1.0, 1.2), 2 (1.0, 1.1), 2 (1.1, 1. P), or 2 (1.2, 1.5) , 2 (1.5, 1.6), 2 (1.P, 1.6) or 2 (1.2, 1.5), 2 (1.1, 1.5), 2 (1.1, 1.P).

 However, if the message reaches node 1.1 and channel 2 (1.1, 1.P) is busy, then channel 2 (1.1, 1.7) will be used for further transmission.

In the switching node (see. Fig. 2 - 4) the transmission of information is possible:
- from the injection channel 5.m - to the output 2.n.2;
- from the input channel 2.n.1 - to the recipient channel 16.l;
- from the input channel 2.R.1 - to the output 2.S.2, moreover, R ≠ S, R = 1, ..., N, S = 1, ..., N.

 The direction of transmission of information is determined by the router 11, which sets the switch channel 12 in the corresponding state.

 Information is transmitted from the injection channel 5.m to the output channel 2.n.2 using a 6.m transmitter. Routing from the 6.m transmitter to the output channel 2.n.2 is carried out as well as from the input channel 2. R.1 to the output channel 2.S.2. The 6.m transmitter negotiates the information transfer protocols of the injection channel 5.m, which can be used, for example, a standard direct memory access channel (DMA), and a protocol for transmitting data over communication channels.

When the first word is written to the 6.m transmitter from the injection channel 5.m, the transmitter goes into route mode. In this mode, before data is transmitted, the transmitter 6.m provides an activating package to the information output DI and waits for a response to arrive at one of the response inputs to start data transfer. Since in the initial state the information output of the transmitter DI 6. m is not yet connected to any of the adapters of the output channel 15.1, ..., 15. N, then the activation information is not used either in the switching node or in the network, and the 6.m transmitter sets the request signal, upon receipt of which the arbiter of 7 buffers checks for the presence of at least one free 9.k buffer according to the state of its busy inputs. If any, then the 7 buffer arbiter sets the source code assigned to the 6.m transmitter in the 7 buffer arbiter at the output of the NI source number. The arbiter of 7 buffers writes the source number code to the switch 8 of the buffers with the selection signal from the kth output of the group of selection outputs and transfers the buffer 9.k to the busy state and transfers the 6.m transmitter into the active state with the signal from the (N + m) -th output of the selection and allows him to send the word control information to buffer 9.k. At the same time, the buffer switch 8 connects the information output of the transmitter DI 6.m with the information DI input of the buffer 9. k and the response output DO of the buffer 9.k - with the second input of the DO response of the transmitter 6.m. The control information is received by the buffer 9.k and at the output of the request of the buffer 9. k, the RQ request signal appears, which is fed to the input RQ of the arbiter of the router 10. The arbiter of the router 10, if the router 11 is not busy processing information with another buffer, sets the k-th output EN permission signal, which, having entered the kth input EN of the buffer switch 8 and the EN input of the resolution buffer 9.k, allows you to set the source code connected to the 9.k buffer and control information on the inputs of the router 11. At the same time, the arbiter of the buffers 7 sets the output signal confirmation information. Router 11, having analyzed the state of its inputs, determines the output channel 2.n.2, to which the message will be transmitted. The response code selected by router 11 is transmitted from the router DO output to buffer 9. k by a parallel code, which is transmitted in subsequent cycles through the buffer switch 8 to the second input DO of the transmitter 6.m response. The following options are possible:
1. The control information word contained a forced routing code and switching was performed.

 In this case, the response code allows the transmission of the next word. The transmitter 6. m requests the next word from the injection channel 5.m and, having received it, transmits the activation information through the channel switch 12 and the adapter 15. n of the output channel to the output channel 2.n.2.

 2. The control information word contained a forced routing code and switching was not performed (since the output channel 15.n is busy).

 The response code requires that routing be repeated on this node. 6.m transmitter goes into an inactive state and sets a request signal at its output. After that, the process of providing the 9.k buffer, transferring control information and routing words to it is repeated.

 This mechanism allows the release of buffers for servicing other input and injection channels while waiting for the release of output channel 2.n.2.

 3. The control information word contained an adaptive routing code and switching was performed.

In this case, the response code allows the retransmission of the control information word. The transmitter 6.m transmits the activation information through the channel switch 12 to the output channel adapter 15.n to the output channel 2.n.2 and waits for a response DO to the first input via the channel 12 switch and the adapter 15.n of the output channel of the response code from the next node switching, allowing the transfer of the word control information. Further, the routing process occurs in the next switching node, and the 6.m transmitter can receive three response options:
- “repeat the transmission of the word” - and the process is repeated from the moment (see paragraph 3);
- "repeat routing in the previous node" - the 6.m transmitter goes into an inactive state and sets a request signal at its output, after which the process of providing a buffer 9.k, transmitting control words and routing words to it is repeated;
- "transmit the next word" - the transmitter 6.m requests the next word from the injection channel 5.m and, having received it, transmits the activation information through the switch of 12 channels and the adapter 15.n of the output channel to the output channel 2.n.2.

 The last word of the control information contains the command switching input channel 2. n. 1 to the destination node receiver 14.l. 6.m transmitter, having received the response code - "transmit the next word", after transmitting this command goes into data transfer mode. In this mode, as the route is laid, activating information is not transmitted. Having received the next word of information from the injection channel, the 6.m transmitter transmits it to the information output and awaits the arrival of a response code. The process continues until a response code arrives to reset the channel, after which the 6.m transmitter returns to its original state.

 The route from the input channel 2.n.1 to the recipient channel 16.l is laid out similarly to the route from the input channel 2.R.1 to the output channel 2. S.2 and differs only in the control word code. Router 11 connects the first of the free receivers 14.1, ..., 14.L. If all the receivers 14.1, ..., 14.L are busy, then the routing in this switching node is repeated until one of the receivers 14.1, ..., 14.L is released.

 A special case of routing is router programming.

 Having received from the buffer 9. k the control information word specifying the start of programming, the router 11 sets a blocking signal at its output, which prohibits the arbiter 10 of the router from connecting information from other buffers 9.1, ..., 9.K to the input of the router 11 until all control information words necessary for programming the router will not be received through 9.k buffer.

 When programming router 11, the 9.k buffer is not freed after each word is received.

 When programming router 11, the information necessary for laying adaptive routes is recorded, i.e. determines the coordinates of the switching node in the network and links the channels 2.1, ..., 2.N to the directions in the coordinate system in the network (X1, X2, ...).

 In the initial state of the switching unit, input automata 4.1, ..., 4.N and transmitters 6.1, ..., 6.M are in an inactive state, output automata 13.1,. . . , 13.N and receivers 14.1, ..., 14.L are also inactive and the status “free” is set at their busy outputs. Information from the output of the channel adapters 3.1, ..., 3.N comes only to the information inputs of the input automata 4.1, ..., 4.N.

 Consider laying a route for a message arriving at input channel 2.R.1.

 The input machine 4.R, which is in an inactive state, analyzes the state of its information DI input and, when activating information appears on it, sets a request signal at the output of the RQ request. The buffer arbiter 7, having received the RQ request signal from the input automaton 4.R, checks for the presence of at least one free buffer 9.k by the state of its busy WS inputs. If there is one, then the buffer arbiter 7 sets the source number NI on the output of the source number 4.R, selects the source number code NI in the buffer switch 8 at the k-th output of the group of outputs CS, and transfers the buffer 9.k in a busy state and, by a signal on the Rth output of the EN resolution, puts the input machine 4.R in the active state. Upon transition to the active state, the input automaton 4.R transmits a response code to the input adapter 3.R of the input channel, informing that a free buffer 9.k is connected to the input channel 2.R.1 and control information can be received. In this case, the buffer switch 8 connects the output of the adapter 3.R of the input channel with the information input DI of the buffer 9.k and the output of the DO response of the buffer 9.k with the first input of the DO response of the input automaton 4.R.

 The control information is received by the buffer 9.k and at the output of the RQ request of the buffer 9.k, the signal RQ of the request appears, which is input to the RQ of the arbiter of the router 10. The arbiter of the router 10, if the router 11 is not busy processing information with another buffer, sets to the kth the output is the enable signal EN, which, upon entering the kth input EN of the enable switch of the buffers 8 and the input EN of the enable buffer 9.k, allows the input of the router 11 to set the code of the source number NI connected to the buffer 9.k and the control information DI . At the same time, the arbiter of the buffers 10 sets the output signal confirmation information. Router 11, having analyzed the state of its inputs, determines the output channel 2.S.2, to which the message will be transmitted. In this case, the response code from the DO output of the router 11 is transferred to the buffer 9. k, which is then transmitted through the buffer switch 8 and the input automaton 4.R and the adapter of the channel 3.R to the input channel 2.R.1. Simultaneously with the response code, router 11 sets the select signal CS to the Sth output, which will put the output machine 13.S into a busy state and write the source number to the channel switch 12. The channel switch will connect the output of the channel 3.R adapter to the input of the channel adapter 15 .S, and the output of the channel adapter 15.S - with the second input DO of the input automaton 4.R.

 After buffer 9. k transmits a response, it goes into the "free" state and can be used to lay other routes.

 Further control information and data are transmitted from input channel 2.R.1 to output channel 2.S.2 without changes. The response codes during transmission from the output channel 2.S.2 to the input channel 2.R.1 are analyzed by the output automaton 13. S. When passing the response codes that control the reset of the channels, the output automaton 13. S goes into the “free” state and can be used to lay other routes. The signal is "free" from the output WS of the busy state machine 13.S interrupts the switching circuit of the channel 15.S adapter in the channel switcher 12. The input machine 4.R also analyzes the response codes and goes into an inactive state when it detects responses that reset the channel. In this case, the input automaton 4.R can modify the response codes so that the route section to the input channel 2.R.1 is not reset. This mechanism allows re-routing in the same switching node if further routing in the switching node selected at the previous routing step is not possible.

The router (see Fig. 5) operates in two modes:
- programming;
- routing.

 Depending on the code word of the control information, the choice of the direction of further transmission of information and the determination of the response code is carried out by block 19 for laying non-adaptive routes or block 20 for laying adaptive routes if there is a data ready signal on their inputs. Block 19 laying non-adaptive routes makes decisions based on the analysis of the word control information and the status of the inputs of employment. The non-adaptive route laying unit 19 also puts the router 11 into programming mode by supplying a programming signal to the start input of the programming unit 22, after which the programming unit 22 sets the blocking signal LK at its output, which blocks the operation of the non-adaptive route building blocks 19 and the adaptive route laying 20. The codes received at the information input of the router 11, each of which is accompanied by a ready signal at the ready input of the programming unit 22, will be sequentially written into the comparison circuit 17, the optimal route determination circuit 18, and the adaptive route laying unit 20 by the pulses generated by the programming unit 22 at the programming outputs .

 The comparison circuit 17 compares the address of the switching node with the address of the destination node of the message in adaptive routing.

 The optimal route determination circuit 18 determines the output channels associated with network nodes located closer to the destination node than this node in adaptive routing.

 The adaptive route routing unit 20 makes decisions as a result of the analysis of the control information word, source number, status of the busy inputs and output status of the comparison circuit 17 and the optimal route determination circuit 18.

 Group 21 of OR circuits passes to the outputs of the choice of the router 11 signals of the choice of output channels 2.n.2 generated by the block laying non-adaptive or adaptive routes.

 When programming the circuit 18 for determining the optimal routes, codes from the information inputs (see Fig. 6) by programming pulses are recorded in the registers. The programming circuit 18 determine the optimal routes is carried out once before the start of laying adaptive routes in the network.

 The destination node address contained in the control information word, by schemes 27.1, ..., 27.N, is divided into coordinate values corresponding to the destination node. The mask register 23.n contains "1" in bits corresponding to one of the network coordinates, because the number of coordinates in the network can be less than or equal to N. From the outputs of circuits 27.1, ..., 27.N And the coordinate values go to circuits 28.1,. .., 28.N comparisons on which are compared with the coordinate values specified in registers 24.1, ..., 24.N coordinates. Schemes 29.1, ..., 29.N choose one of the results of the comparison: "more", "equal" or "less", depending on the values of the codes recorded in registers 25.1, ..., 25.N of the condition. The signals from the outputs of circuits 29.1, ..., 29.N are fed to the first inputs of the elements 30.1,. . . , 30.N OR, to the second inputs of which signals from communication registers 26.1, ..., 26.N are received. The results of the logical addition of signals from the outputs of circuits 29.1, ..., 29.N and communication registers 26.1, ..., 26.N go to the inputs of circuits 31.1 ,. . . , 31.N And, at the outputs of which logical 1 signals are generated for channels that can be used to lay optimal routes.

 Every three registers 23.n, 24.n and 25.n, the masks, coordinates and conditions respectively specify the coordinates of the destination nodes in the network for which at least one output channel 2.S.2 can be used. Communication registers 26.1, ..., 26.N define the correspondence between the output channel 2.S.2 and the coordinates of the destination nodes. Communication register 26.S contains logical "0" only in those positions that correspond to the conditions that must be met in order for output channel 2.S.2 to be selected as optimal.

For example, for node 1.1 (see Fig. 1), you must specify the conditions:
1) X1 = 0;
2) X1>1;
3) X1>P;
4) X2 = 1;
5) X3 = 1;
6) X4 = 1.

 Output channel 2 (1.0, 1.1) can be used when the first condition is met, output channel 2 (1.1, 1.7) can be used when the second condition is met, output channel 2 (1.1, 1. P) can be used when the third condition is met, output channel 2 ( 1.1, 1.5) - when the fourth condition is fulfilled, output channel 2 (1.1, 1.8) - when the fifth condition is fulfilled and output channel 2 (1.1, 1.9) - when the sixth condition is fulfilled.

 Each communication channel in the network connecting the switching nodes to each other, for example, channel 2 (1.0, 1.1) between the nodes 1.0 and 1.1 can be formed, for example, by connecting the output channel 2.1.2 of the switching node 1.0 with the input channel 2.2.1 of the switching node 1.1 and 'the connection of the output channel 2.2.2 of the switching node 1.1 and the input channel 2.1.1 of the switching node 1.0.

For example, in node 1.1:
communication channel 2 (1.0.1.1) is formed by channels 2.1.1 and 2.1.2;
communication channel 2 (1.1,1.7) is formed by channels 2.2.1 and 2.2.2;
communication channel 2 (1.1,1.5) is formed by channels 2.3.1 and 2.3.2;
communication channel 2 (1.1,1.8) is formed by channels 2.4.1 and 2.4.2;
communication channel 2 (1.1,1.9) is formed by channels 2.5.1 and 2.5.2;
communication channel 2 (1.1.1.P) is formed by channels 2.6.1 and 2.6.2.

 In this case, communication registers 26.1, ..., 26.6 will contain the codes: 011111, 101111, 111011, 111101, 111110 and 110111, respectively.

 In block 20, laying adaptive routes (see Fig. 7) during programming, codes from information inputs by programming pulses are recorded in the register 34 of the number and the register 35 of communications. The register 34 of the number contains a condition under which the block laying adaptive routes can select a non-optimal route. The comparison circuit 40 allows you to select a non-optimal route if the number of possible optimal routes calculated by the adder 38 is less than the number recorded in the register 34 numbers. Communication register 35 contains units in those bits whose numbers correspond to the numbers of communication channels connected to remote switching nodes. These channels have the highest priority when choosing the optimal routes and cannot be used when choosing non-optimal routes.

 The signals from the inputs of the optimal routes are fed to a group of AND circuits 33, which exclude the directions of message arrival from the optimal routes, and to the information inputs of the multiplexer 39, which allocates this direction. Decoder 32 converts the binary code of the source number into a positional code. If the message came from the optimal direction, then the logic 1 will appear at the output of the multiplexer 39, which will go to the second input of the response encoding circuit 49 and prohibit the selection of a non-optimal channel. The signals from the outputs of circuits AND 33 are fed to the input of the adder 38, which counts the number of logical “1” at the inputs, which is then compared in the comparison circuit 40 with the number stored in the register 34 of the number. If the number in the register 34 of the number is greater, then the output of the comparison circuit 40 is set to logical "1", which is fed to the fourth input of the response encoding circuit 49. The first inputs of the group of circuits 37 AND receive signals from the outputs of the circuits 33 AND containing "1" at the outputs of the corresponding channels, which can be selected as optimal routes; the second inputs of the group of circuits AND 37 receive signals from the inputs of employment containing "0" at the inputs corresponding to free channels; at the outputs of the group of circuits And 37 are set to "1" in positions corresponding to free channels, which can be used as optimal. The OR circuit 45 forms a logical “1”, if any, are present. In this case, the priority encoder 48 is allowed to work and the priority encoder 50 is prohibited, the logical “1” is sent to the first input of the response encoding circuit 49. The groups of circuits And 41 and 42 share the free optimal channels associated with remote nodes and adjacent, respectively. If there is at least one free channel associated with a remote node, the OR element 44 prohibits the operation of the priority encoder 48 and allows the operation of the priority encoder 47, which generates at its outputs a number corresponding to this channel.

 If there are no channels associated with remote nodes, then the code corresponding to the channel number forms a priority encoder 48. Circuit group 43 AND allocates free channels associated with adjacent nodes. The OR circuit 46 determines the presence of dedicated channels. The signal from the output of the OR element 46 is supplied to the sixth input of the response encoding circuit 49. If there are no optimal free channels, a logical “0” is present at the inverse input of the priority encoder 50 resolution and the priority encoder 50 generates a free non-optimal channel number that can be used for further routing.

 A decision on the choice of a further route is made if there is a permission signal, no blocking signal, and if one of the information inputs of the adaptive route routing unit 20 has a logical “1”, confirming that an adaptive address is set at the input of the adaptive route routing unit 20. In this case, the AND element 36 generates a permission signal to the response encoding circuit 49. If a decision is made to route to one of the free channels, the response encoding circuit 49 generates an enable signal to the decoder 51.

 The decoder 51 decodes the channel number generated by one of the priority encoders 47, 48, 50 into a selection signal. Priority encoders 47, 48, 50 operate on a ring priority scheme to select a different channel if no further routing is possible in the switching node to which the message was sent, and routing is repeated in this switching node.

The response encoding circuit 49 generates the following response codes, depending on the state of the inputs:
- “transmit the next word”, if the message has reached the destination node, a logical unit is present at the third input;
- “repeat the word transmission” if the optimal or non-optimal route (channel) was chosen for further route planning;
- “repeat routing in this node”, if there are more optimal channels than the number recorded in the 34th register, but they are busy, and the message did not come from the optimal direction, the optimal route was selected in the switching node that sent the message to this node:
- "repeat routing in the previous node" - in other cases.

 In block 19 of laying non-adaptive routes (see Fig. 8) in the absence of a blocking signal and the presence of a data ready signal at the inputs, as well as in the presence of a logical "0" at one of the information inputs, confirming that the non-adaptive address and decoder 52 are installed at the input forms a logical "1" at the nth output, if the control word contains the command "Code for forced routing to the nth channel", or logical "1" to (N + 1),. . . (N + L) outputs, if the control word contains the command “Forced routing code to the recipient channel”, or logical “1” at the programming output, if the control word contains the “Programming” command, and logical “1” at the ready output. The group of elements 53 And passes to the input of the encoder 54 logical "1" from the output of the decoder 52, corresponding to unoccupied channels. If there are any, the encoder 54 at the ready output generates a logical “1” that enables the operation of the decoder 56 and the formation of the “Send the next word” response code by the response encoding circuit 55, as well as the number of the nth output channel or the free recipient channel on the output group, which decoded by the decoder 56 into a selection signal at the corresponding output. If there is no free, the response encoding circuit 55 generates a response "Repeat routing in this node".

 In the initial state, the trigger 57 (see Fig. 9) of the programming unit 22 is reset, the logical "0" from the output of the trigger 57 sets the counter 58 to the zero state.

 The start pulse cockes the trigger 57 and the blocking signal is set at the output of the programming unit 22. The ready signal enables the operation of the decoder 59 and by its end transfers the counter 58 to the next state. Thus, the sequence of ready signals is converted into a sequence of programming pulses at the outputs of the programming unit 22. At the same time, the output of the decoder 59, corresponding to the zero state of the counter 58 is not used, because at this time the router programming command is present on the information inputs of the router 11. The end of the last programming pulse resets trigger 57.

 In the 12-channel switch, the signal at the s-th input of the CS selection (see Fig. 10) records the number r corresponding to the number of the input 2.n.1 or injection 5. m channel from which the route-laying message arrived in register 60. s. The busy signal WS at the s-th busy input allows the multiplexer 61.s to switch the rth information input DI to the s-th information output DI of the 12 channel switch, and the demultiplexer 62.s to switch the s-th input DO of responses to its r exit. Next, the response code through the circuit 63.r OR enters the r-th output of the answers DO switch 12 channels. When the route laid through the switching node is reset, the output machine 13.s (see Figs. 2-4) or the receiver 14.l resets the busy signal WS and the switching stops.

 The switch 8 buffers works similarly to the switch 12 channels with the only difference being that switching is not done with output channels or receivers, but with buffers. In addition, when the enable signal appears at the kth input of the enable EN, the source number recorded in the register 64.k (see Fig. 11) through the buffer element 68. k is transmitted to the output NI of the source number of the switch 8 buffers.

 In the initial state, the triggers 69 and 70 (see Fig. 12) of the buffer 9 are reset, and the registers 71 and 73 are set to zero. The signal at the input CS of the selection sets the trigger 69 busy, and at the output WS of the busy signal appears busy. The serial code from the information input DI enters the register 73. When the start bit of the code reaches the high order, the shift of information in the register 73 is stopped and the signal RQ request appears at the output of the buffer 9. Upon receipt of a permission signal 9 at the input of the buffer 9, information from the register 73 is transmitted through the buffer element 74 to the output of the buffer 9. The response code generated by the router 11 is recorded in the response register 71 and the reset enable trigger 70 is cocked. The response code from the response register 71 is transmitted by a sequential code to the output of the response from the highest order, the lower digits are filled with zeros. When the response is transmitted and all the bits of the response register 71 contain zeros, the OR circuit 72 generates a signal that resets the busy triggers 69 and the reset enable 70. The information register 73 is reset by the enable signal at the same time as the response is recorded in the response register 71.

 The output machine 13 is put into a busy state by a selection signal (see FIG. 13). The response code is sent by a sequential code to register 76. The decoder 77 resets the busy trigger 75 and register 76 if the response code "Reset Channel" or "Repeat routing in the previous node" is in register 76.

 In the initial state, the triggers 78 of the request and 79 busy input machine 4 (see Fig. 14) are reset. Upon receipt of the activating information at the information input, the request trigger 78 is installed and the request signal RQ appears at the output of the input automaton 4. When the buffer 9 is connected, the signal at the enable input EN sets the busy trigger 79, which resets the request trigger 78. The enable signal through the OR element 85 is transmitted to the response output, as a response to the transmitting switching node allowing the transmitter 6 to transmit control information. The busy trigger 79 holds the trigger of the request 78 in the reset state and the receipt of information at the information input of the input machine 4 does not cause the installation of the request signal. The response codes with a sequential code are entered into register 80 from buffer 9 or into register 82 from the adapter of the output channel 15. The decoder 81 generates a signal at the first output that resets through the element 84 OR trigger 79 when the response codes "Reset channel" are received in register 82, " Repeat routing in this node ", or" Repeat routing in the previous node ". The response code "Repeat routing in this node" causes a signal to appear on the second output of the decoder 81, resetting the response register 80. Since the first input of the decoder 81 is connected directly to the first input of the response of the input automaton 4, and the information from the first output of the register 80 is transmitted to the output of the response, the last “1” in the code “Repeat routing in this node” will not be transmitted. Thus, the answer "Repeat routing in this node" is converted to the answer "Repeat the transmission of the word". Register 82 and decoder 83 operate similarly to register 80 and decoder 81, but with different response codes coming from the output channels. Reset channel or Retry routing in the previous node response codes reset the busy trigger 79, and Retry routing in the previous node code is converted to the Repeat word response code.

 In the initial state in the receiver 14, the triggers 88, 90 and 92 are reset, the registers 89 and 86 are set to zero (see Fig. 15). The selection signal at the input of the CS of the receiver 14 cocking the trigger 92 busy. Information with a serial code from the information DI input is entered into the data register 86 until the start bit reaches the high bit of the data register 86, which prohibits further shift and cockes the trigger 88 of the channel request. At input 16.l.2, the active level appears. The channel grant signal 16.l.4 enables the output of data from the data register 86 through the buffer 87 to the outputs 16.l.1 to the recipient channel, recording the response code in the response register 89 and resets the channel request trigger 88. If the last word of the message has been received, the signal of the last cycle cocks the trigger to reset the channel, and the response code 89 writes the response code "Reset Channel", otherwise the response code 89 writes the response code "Send the next word". The response code is transmitted by a sequential code from the register 89 of the response to the output DO of the response of the receiver 14, thereby resetting the data register 86, thereby allowing the reception of the next word in the data register 86. When the channel reset trigger 90 is set, after transmitting the response, the busy trigger 92 is reset via the OR-NOT circuit 91 and resets the channel reset trigger 90 with its inverse output.

In the initial state in the 6.m transmitter, the triggers 104, 106, 108, 111, 113 are reset (see Figs. 16-17). At the inverted output of trigger 108, a signal of channel demand 5.m.3 is installed. When the channel is provided, data from the injection channel 5.m is recorded in the data register 93 and the trigger 108 is installed and removes the signal of the request channel 5.m.3. At the same time, since the trigger 113 is reset, the write pulse from the input 5.m.2 through the circuits 102 AND and 101 OR is transmitted to the information output of the transmitter 6.m as activating information. The reset trigger 104 allows during the recording of data through the circuit 105 And install the trigger 106 and, accordingly, the request signal at the output of the transmitter 6.m. When 8 buffers are connected through the switch 8 to the transmitter 6. m of the buffer 9.k, the enable signal EN resets trigger 106 and sets trigger 104. Thus, the RQ request signal will not be set in transmitter 6.m until trigger 104 is reset by one from the Reset Channel, Retry Routing At This Host, or Retry Routing At Previous Host answers. The enable signal, having passed through the OR circuit 109 and the multiplexer 110 cocks the trigger 111, which enables the counter 95 to work. The counter 95 controls the serial transmission of the multiplexer 94 through the OR circuit 101 to the information output of the 6.m transmitter, the start bit, and the data stored in register 93. After completion of the transfer, the decoder 96 inhibits the operation of the counter 95 and resets the trigger 111. The transmitter 6.m receives the response code from one of the DO response inputs to the register 97. The decoder 98 decodes the response received in the register 97. The OR circuit 100 resets the counter 95 and the register 97 of responses when the decoder 98 detects one of the answers:
"Convey the next word";
"Reset Channel";
"Repeat routing in this node."

"Repeat the word";
"Repeat routing in the previous node."

 The last three answers are possible only when plotting the route and require retransmission of the word stored in register 93. The decryption signals of these answers are transmitted through the OR circuit 101 to the information output of the 6. m transmitter as activating information. If the response code requires rerouting, then trigger 104 will be reset and trigger 106 is set.

 Trigger 108 will be reset with the responses “Send the next word”, or “Reset channel” and, accordingly, will set the demand signal of channel 5.m.3 at the output of the transmitter 6. m. The trigger 113 is set if the zero and first bits of the control information stored in register 93 contain "1", which is a sign of a router programming command or a non-adaptive address of the recipient channel, and the answer "Send the next word" is received. Installed trigger 113 indicates the end of the route. After the route has been laid, the data recording signals 5.m.2 are not transmitted through the And circuit 102 as activating information, but a trigger 111 is cocked through the multiplexer 110, which allows data transmission to the information output. Trigger 113 is reset with the Reset Channel response.

 The arbiter 7 buffers works as follows (see Fig. 18). Upon receipt of a request signal at one of the RQ inputs of the request, the encoder 114 sets the code corresponding to the input number on which the request signal is present. If several request signals appear simultaneously, the encoder 114 generates the NI number of one of them having the highest priority. The lower priority request signals will be processed after the highest priority request is removed. The encoder 116 forms the number of one of the free buffers. If there is at least one request signal and one free buffer, the OR elements 115 and 117 form a logical “1”, which through the AND element 118 allows the operation of decoders 119 and 120, which generate the EN enable and CS select signals, respectively.

 When one of the inputs of the request of the arbiter 10 of the router receives a request signal, the encoder 121 (see Fig. 19) generates the number of the buffer 9 that established the request. The latch register 123, in the absence of a lock signal at the lock input, passes the code of the buffer number 9 to the inputs of the decoder 124 and the address inputs of the multiplexer 122. The request signal, passing through the multiplexer 122, allows the decoder 124 to set the output at the output corresponding to the buffer number, and confirms that the control information word is transmitted to the information inputs of the router 11.

 When several requests are received at the inputs of the arbiter 10 of the router at the same time, the latter are served with time sharing in accordance with the priorities implemented by the encoder 121.

 If buffer 9.k passed to the router 11 a control information word that sets the programming of router 11 to begin, router 11 will set a blocking signal at the k-th input until the request signal ends, which will fix the number k in latch register 123. Thus, requests from other buffers 9 will not be serviced until the lock signal is released.

 When programming the router 11 in the register 125 (see Fig. 20) of the comparison circuit 17, the address of the switching node 1 in the network is recorded. When the router 11 is operating, the control word codes are compared with the address recorded in the register 125, and the logical 1 will appear at the output of the comparison circuit 17 if the control word code matches the address of switching node 1 on the network.

The response encoding circuit 49 (see FIG. 21) converts the input signals to output signals in accordance with the table in FIG. 22, where all possible states of the inputs and outputs of the response coding scheme 49 are indicated, wherein "
"0" is a logical zero;
"1" is a logical unit;
X is “0” or “1”;
Z is the third state (or state of high impedance).

The encoder (see FIG. 20) converts the input signals to the output in accordance with the table in FIG. 24, which shows all possible options for the status of the inputs and outputs of the encoder, and
"0" is a logical zero;
"1" is a logical unit;
X is “0” or “1”;
Z is the third state (or state of high impedance).

 To the unused enable inputs of the encoder, a enable signal is supplied during the implementation of circuits 114, 117, 119 and 120.

 The functions implemented by the decoder 52 (see Fig. 25) are given above when describing the operation of the non-adaptive route laying unit 19.

 The response encoding circuit 55 (see FIG. 26) generates a response during non-adaptive routing and programming, and can generate code 0001 "Send the next word" or 0111 "Repeat routing in this node". With adaptive routing, the outputs of response encoding circuit 55 are disabled.

 In the case of the implementation of the network on the elements of computer technology, the switching node 1 (see Fig. 1) is made in the form of a microcircuit, for example, 1578XM8 series.

 Channels 2, both input and output, can be made in the form of wired communication lines, such as cables, twisted pairs, etc. Injection 5 and recipient 16 channels provide communication with equipment connected to the switching unit. For example, when the network is operating in a multiprocessor computing system, injection 5 and recipient 16 channels are channels of direct access to the processor (s) memory and can be implemented on integrated circuits (ICs) of both domestic and foreign production, for example: KR580IK57.

 Adapters 3 and 15, both input and output channels, are a pair of transmitter and receiver, for example, buffer elements of the 1578XM8 chip. And also external adapters of input and output channels can be used. When using cable communication lines, external adapters can be made according to the scheme shown in Fig. 9.40 (see P. Horowitz, W. Hill "The Art of Circuit Engineering", M., Mir, 1993, v. 2, p. 231).

 Consider the example of achieving a technical result (see Fig. 32 - 33) when using the invention.

Taking for τ the message transit time at the end of communication between two switching nodes connected by this channel, we obtain the total message transit time between the source node and the destination node:
- for FIG. 32 - T1 = 10 τ - for the prototype;
- for FIG. 33 - T2 = 6 τ - for the proposed network.

 Thus, the transit time of the message in the proposed network decreased by 1.7 times.

 In the general case, the technological result can be significantly higher depending on the network dimension and the number of communication channels between individual switching nodes.

Claims (4)

 1. A network for routing messages, consisting of at least three switching nodes, each of which contains a router, and adjacent switching nodes are connected to each other by communication channels, characterized in that at least one switching node is connected by an additional communication channel at least with one remote switching node, and a remote switching node is understood as a switching node, at least one of the coordinates of which differs by more than one, and N input, N output, M injection are introduced into the switching node n (M = 1, ..., N) and L recipient (L = 1, ..., N) channels, N input and T output automata, K buffers (K = 1, ..., N-1) , L receivers, M transmitters, buffer and router arbiters, buffer and channel switches, 2N input and output channel adapters, the nth input channel being connected to the channel input-output group of the nth input channel adapter, whose input is connected to the response output nth input automaton, the information input of which is connected to the output of the nth adapter of the input channel, which is connected to the n-th inputs of the groups of information inputs of the switch channel and buffer switch, the first input of the responses of the nth input automaton is connected to the nth output of the group of outputs of the response of the buffer switch, and the second input of the responses of the nth input automaton is connected to the nth output of the group of outputs of the response of the channel switch, query output n the input automaton is connected to the nth input of the buffer arbiter query input group, the permission input of the nth input automaton is connected to the nth output of the buffer arbiter permission output group, the mth injection channel is connected to the mth channel input-output group gears ka, whose information output is connected to the (N + m) -th inputs of the groups of information inputs of the channel switch and the buffer switch, the first input of the responses of the mth transmitter is connected to the (N + m) -th output of the output group of the answers of the buffer switch, and the second input of the responses of the mth transmitter is connected to the (N + m) -th output of the channel switch response output group, the request output of the m-th transmitter is connected to the (N + m) -th input of the buffer arbiter request input group, the permission input of the m-th transmitter is connected with (N + m) -th output of the group of outputs of the arbiter permission buffer c, the information input of the Kth buffer is connected to the Kth output of the group of information outputs of the buffer switch, the response output of the Kth buffer is connected to the Kth input of the group of inputs of the responses of the buffer switch, the busy output of the Kth buffer is connected to the Kth inputs of the group of inputs the busyness of the buffer arbiter and the buffer switch, the Kth output of the group of outputs for selecting the buffer arbiter is connected to the input of the selection of the Kth buffer and with the Kth input of the group of inputs for selecting the buffer switch, the group of outputs of the source number of the buffer arbiter is connected to the group of inputs of the number of of the buffer switch, groups of information outputs of the buffers are combined and connected to the group of information inputs of the router, groups of inputs of the responses of buffers are connected to the group of outputs of the responses of the router, the request output of the Kth buffer is connected to the Kth input of the group of inputs of the request of the router arbiter, group of outputs of the router arbiter connected to the group of permissions of the switch of the buffers and with the inputs of the permission of the buffers, the group of outputs of the number of the source of the buffer switch is connected to the groups of inputs of the number of the source and a switch of channels and a router, the input of which confirms the information is connected to the confirmation output of the information of the arbiter of the router, the blocking input of which is connected to the blocking output of the router, the group of selection outputs of which is connected to the group of inputs of the choice of channel switch, as well as the inputs of the selection of output machines and receivers, outputs busy output machines and busy outputs of receivers connected to a group of inputs of the busy router and a group of inputs of busy switch channels the data outputs of which are connected to the inputs of the adapters of the output channels and the inputs of the receivers, the output of the nth adapter of the output channel is connected to the input of the responses of the nth output automaton and to the nth input of the group of inputs of the response of the channel switch, the output of the response of the lth receiver is connected to ( N + l) -th input of the group of inputs of the responses of the channel switch, the nth output channel is connected to the group of channel inputs and outputs of the nth adapter of the output channel, the l-th recipient channel is connected to the group of channel inputs and outputs of the l-th receiver.  2. The network according to claim 1, characterized in that the router contains blocks for laying adaptive and non-adaptive routes, N OR circuits, a programming block, a comparison circuit, and a circuit for determining optimal routes, and the group of information inputs of the router is connected to groups of information inputs of the comparison circuit, circuit determine the optimal routes and blocks of laying adaptive and non-adaptive routes, the group of inputs of the source number of the router is connected to the group of inputs of the number of the source of the block of laying adaptive routes tov, the router busy input group is connected to the busy input groups of non-adaptive and adaptive route laying blocks, the response output groups of which are combined and connected to the router response output group, the router data ready output is connected to the programming block resolution inputs, adaptive and non-adaptive route laying blocks, group the outputs of the programming unit is connected to the groups of inputs of the programming unit for laying adaptive routes, schemes for determining the optimal march Route and comparison circuit, the output of which is connected to the equality input of the adaptive route routing unit, the group of inputs of the optimal routes of which is connected to the group of outputs of the optimal route determination circuit, the first output group of the selection of the non-adaptive routing unit is connected to the first inputs of the OR group of elements, the second inputs of which are connected with outputs for selecting a block for laying adaptive routes, the programming output of a block for laying non-adaptive routes is connected to the start input of the block I, which locks an output coupled to the inputs of the lock blocks gasket adaptive and maladaptive routes and router lock outputs group select router outputs connected to the outputs of OR elements and a second group gasket nonadaptive route selection outputs.  3. The network according to claim 2, characterized in that the optimal route determination scheme contains N mask registers, N condition registers, N coordinate registers, N communication registers, N comparison schemes, N elements 2-2-2I-3OR, N groups of elements OR for N elements in each, N groups of elements 2I for (S-1) elements in each and N elements AND, and the group of information inputs of the optimal route determination circuit is connected to the groups of information inputs of the registers and to the first inputs of the groups of elements 2I, the second inputs of which connected to groups of mask register outputs, the group of programming inputs of the optimal route determination circuit is connected to the inputs of the register entries, the outputs of the groups of elements 2I are connected to the first groups of inputs of the comparison circuits, the second groups of inputs of which are connected to the groups of outputs of the coordinate registers, the outputs of the comparison circuit are connected to the first inputs of the elements 2-2-2I- 3 OR, the second inputs of which are connected to the outputs of the condition registers, the outputs of the elements 2-2-2I-3 OR are connected to the first inputs of the groups of OR elements, the second inputs of which are connected to the outputs of the communication registers, the outputs RUPP OR elements are connected to inputs of AND gates whose outputs are the outputs of circuits and determining optimal routes.  4. The network according to claim 2, characterized in that the adaptive route laying unit contains five groups of AND elements with N elements each, a multiplexer, three N-input OR elements, an adder, registers, a comparison circuit, three priority encoders, a response encoding scheme , two decoders, element And, moreover, the group of information inputs of the adaptive routes routing unit is connected to the information inputs of the registers, the recording inputs of which are connected to the group of programming inputs of the adaptive routes routing unit, whose equality input is inen with the third input of the response coding scheme, the group of outputs of which is the group of response outputs of the adaptive route laying unit, the optimal route input group of which is connected to the information inputs of the multiplexer and the fifth inputs of the first group of AND elements, the employment input group of the adaptive route laying unit is connected to the inverse inputs of the second groups of elements AND and the first inverse inputs of the fifth group of elements AND, the second inverse inputs of which are combined with the second inputs of the third group of elements s and the inverse inputs of the fourth group of elements And and are connected to the outputs of the connection register, the group of inputs of the source number of the adaptive routing unit is connected to the address inputs of the multiplexer and the group of inputs of the first decoder, the group of outputs of which is connected to the inverse inputs of the first group of elements, the output of the multiplexer is connected with the second input of the response coding circuit, the fifth input of which is connected to the output of the And element, the first input of which is connected to one of the inputs of the group of information inputs of the block Adapts of adaptive routes, the resolution and blocking inputs of which are connected to the second and inverse inputs of the AND element, respectively, the outputs of the first group of elements AND are connected to the direct inputs of the second group of elements AND and the inputs of the adder, the outputs of which are connected to the first inputs of the comparison circuit, the second inputs of which are connected to the outputs of the number register, the output of the comparison circuit is connected to the fourth input of the response coding scheme, the first input of which is combined with the resolution input of the second priority encoder and the inverse input of solutions of the third priority encoder and connected to the output of the second OR element, the inputs of which are combined with the first inputs of the third group of elements AND and the direct inputs of the fourth group of elements AND and connected to the outputs of the second group of elements AND, the outputs of the third group of elements AND are connected to the inputs of the first priority encoder and the inputs of the first OR element, the output of which is connected to the resolution input of the first priority encoder and the inverse resolution input of the second priority encoder, whose inputs are connected to by the fourth group of AND elements, the outputs of the fifth group of AND elements are connected to the inputs of the third priority encoder and the inputs of the third OR element, the output of which is connected to the sixth input of the response coding circuit, the resolution output of which is connected to the resolution input of the decoder whose inputs are connected to the combined outputs of the priority encoders , the outputs of the choice of the block laying adaptive routes are connected to the outputs of the decoder.

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