GB2223867A

GB2223867A - Multiprocessor data processing system

Info

Publication number: GB2223867A
Application number: GB8821163A
Authority: GB
Inventors: Rofessor Peter Edwin Osmon; Philip Steven Winterbottom
Original assignee: City University of London
Current assignee: City University of London
Priority date: 1988-09-09
Filing date: 1988-09-09
Publication date: 1990-04-18
Also published as: GB8821163D0

Abstract

A multiprocessor data processing system comprises a network of communications devices connected to respective associated processing devices, which communications devices transfer messages among the processors without the involvement of the processors, unless a processor is the source or the destination of a message. Each device includes a communications unit housing input and output multiplexers 2231, 2232, 2237, 2238 with byte-wide ports for connection to ports of neighbouring units. Each device has two channels capable of simultaneous operation and housing a respective controller 2234, 2235. <IMAGE>

Description

A multiprocessor data processing system The present invention relates to a multiprocessor data processing system in which the processors are close together.

There exist multiprocessor data processing systems in which the processors are widely separated and communicate by means of one or more forms of transmission line. The design of multiprocessor data processing systems in which the processors are widely separated is dictated by the cost and the characteristics of the transmission lines that link the processors but those considerations relevant to the design of systems with widely separated processors are of little or no consequence to the design of systems in which the processors are close together. For example, a system in which the processors are close together is required to operate with a higher level of traffic and requires a wider bandwidth than a system with widely separated processors. Also, a system with the processors close together is less able to tolerate delays than a system with widely spaced processors.

A proposed multiprocessor data processing system in which the processors are close together requires that the processors be arranged in a regular array, or matrix, and connected together by communications paths forming a cartesian grid with the processors occupying the nodes of the grid. Communication among the processors forming the proposed system involves the generation of data for transfer by a source processor and the passage of the data through one or more intermediate processors to a destination processor.

Each processor, when acting as an intermediate processor in the passing of data, absorbs the data, inspects its destination address, makes a decision as regards the further routing of the data, and transfers the data to a neighbouring processor according to the routing decision that has been made. All processor activity relating to communication occurs under software control.

In accordance with the present invention, a multiprocessor data processing system comprises a network of communications devices connected to respective associated processing devices, the communications devices being capable of transferring, among the processing devices, messages containing information generated by the processing devices, wherein each communications device, in operation, transfers messages without the participation of its associated processing device unless its associated processing device is the addressing processing device providing the message or is the addressed processing device receiving the message.

Thus, it is not necessary for every communications device to have a processing device connected to it for the system to operate.

In one form of the multiprocessor date processing system, each communications device has transfer ports for transferring messages between adjacent devices and each communications device has a terminal port for connection to an associated processing device.

In a multiprocessor data processing system that includes communications devices with transfer and terminal ports, each communications device has a structure such that, when operating as a source device, it generates messages from information accepted through its terminal port and, when operating as a destination device, it delivers, through its terminal port, information contained in messages accepted through one of its transfer ports and addressed to its associated processing device.

The network may be in the form of a chain of communica tions devices in which each communications device is connected to a neighbouring communications device. The chain of communications devices may be a closed loop. A processing device connected to a communications device in a first chain of communications devices may be connected also to a communications device belonging to a second chain of communications devices.

Alternatively, the network may be in the form of a multi-dimensional structure in which each communications device is connected to each of its neighbouring communications devices. The multi-dimensional structure may be wrapped around to provide a plurality of interconnected closed loops. A processing device connected to a communications device in a first multi-dimensional structure may be connected also to a communications device belonging to a second network of communications devices, which second network may be a second multi-dimensional structure. Also, a communications device may belong to more than one multidimensional structure.

A preferred multi-dimensional network structure has the form of a regular cartesian grid in which the network communications devices occupy the intersection points of the grid and are identified by the coordinates of the points they occupy. Other suitable multi-dimensional networks are those in which the communications devices occupy the corners of polygons, such as, for example triangles and hexagons.

A communications device for a chain network requires two transfer ports, a communications device for a two-dimensional network requires four transfer ports, a communications device for a three-dimensional network requires six transfer ports, and so on. In general, the number of transfer ports required for a communications device is 2n where the network is n- dimensional (in electrical terms) The structure of each communications device is such that a message is generally moved in a direction taking it closer to the destination communications device, that is, by one of the shortest possible routes. Where several routes of equal length are available, one route is selected at random.The direction in which a message leaves a communications device is determined by fixed logic elements in the communications device, the address carried by the message, and the availability of transfer ports from the communications device in directions that would take the message closer to the destination communications device. The communications devices include no software for message routing.

The decisions relating to message routing and the routing of messages through the network are carried out by the hardware contained in the communications devices. Routing is performed by fixed logic elements which consider the current state of the communications device holding the message header, the header of the message to be routed, and the state of the neighbouring communications devices. The simplest case of a routing algorithm which is sufficient for regular cartesian topologies where all elements of the network are functioning is one which always moves a message in a direction taking it closer to its destination. However, a routing algorithm which allows a communications device to consider the state of its neighbours could operate in the presence of faulty communications devices so as to avoid their inclusion in a route. Such an algorithm could also be utilised in irregular topologies. A regular network of communications devices will be extensible up to the limit imposed by the number of addressing bits used for message routing.

A message comprises a train of characters that provide a destination address and information for the addressed processing device, and may include error detection and correction characters. The destination address indicates, initially, the position of the destination or addressed communications device relative to the source or addressing communications device, and, as the message passes through intermediate communications devices between the addressing and addressed communications devices the destination address is so altered by the intermediate communications devices that, at each intermediate communications device, the address characters represent the displacement of the message from the addressed communications device. The address characters form the head or front of the message.

Each communications device has fixed logic elements that carry out the functions of accepting a message, examining the destination address characters, altering the destination address characters, and passing the message on.

The communications devices are capable of operation at rates that are limited only by the maximum clock operating speeds of the logic elements from which they are constructed since they include no software decision-making components.

The operations involving the transfer of information between source and destination communications devices and their respective associated processing devices are likely to occur at lower rates than message transfer between intermediate communications devices. The intermediate communications devices, therefore, are capable of operation at high speeds, for message transfers, and the overall transmission rate is limited by the speed at which source and destination processing devices can perform.

The transfer of a message requires the establishing, by the head characters of a message, of a route extending from the source or addressing communications device to the destination or addressed communications device, the drawing along of the remainder of the message by the head characters as they move and, finally, the delivery of the remainder of the message to the destination or addressed communications device, following the arrival there of the head characters.

The transfer of a message includes the reservation of a transfer route through the communications devices situated between the addressing, or source, processing device and the addressed, or destination, processing device.

The communications devices are capable of operating cooperatively to transfer address characters of a message from communications device to communications device, and, at each transfer, to allocate registers for the storage of parts of the message to effect the transfer of the message, through a chain of linked registers, from the source or addressing processing device to the destination or addressed processing device.

The source or addressing communications device is involved in drawing each message out of its associated processing device and the destination or addressed communications device is involved in directing each message to its associated processing device, but each of the intermediate communications devices on each route involved in a message transfer plays its part in the establishing of the route and the transfer of the message without involving its associated processing device.

Each communications device includes a first storage means capable of storing a message and, in operation, the communications device associated with the addressing processing device stores, in the first storage means, a message being transferred from the communications device associated with the addressing processing device.

Each communications device includes a second storage means capable of storing a message and, in operation, the communications device associated with the addressed processing device stores, in the second storage means, a message being transferred to the communications device associated with the addressed processing device.

When the head characters of a message cannot be allocated a suitable transfer port by a host intermediate communications device, the attempt at establishing a transfer route between the source or addressing communications device and the destination or addressed communications device is judged to have failed, and the part transfer route established at the time is abandoned. A suitable transfer route would be one on a direct route between the source and destination communications devices, in order to meet the requirement that a message is never routed in a direction taking it away from the destination communications device. A message transfer is abandoned by the dissolution of the reserved transfer route and failure occurs when the communications device furthest along the route from the addressing processing device is unable to extend the route.The failure to establish a transfer route leaves the message stored at the source or addressing communications device.

A message cannot be lost because it remains stored at the source or addressing communications device while the head characters are establishing a transfer route and is transferred without interruption to the destination or addressed communications device once the head characters reach the destination or addressed communications device. The fact that a message remains stored at the source or addressing communications device until a route to the destination or addressed communications device is established, means that there need be no delay in abandoning a partly established route that is blocked. There is no tendency for the system to become deadlocked as would occur if incomplete routes are not abandoned immediately blocking occurs.Messages cannot be transferred out of sequence as the source or addressing communications device that is holding a message for transfer will continue to try to establish a transfer route. Any delay between a communications device receiving a message for transfer and being able to deliver is minimal since each communications device is equipped with at least two channels either of which may be used for message transfers without the messages interfering with one another. Error detection and correction codes may be included in the messages. Messages are of variable length but may be limited as to length in order to avoid routes being occupied for too long. Messages are required to have a minimum length, in bytes, equal to the maximum route length, within the network, plus one byte.

In a preferred form of the multiprocessor data processing system, the connections between adjacent communications devices include character-wide registers, connectable by switches to form a chain of character-wide registers that extend between the source and destination communications devices during message transfer. The switches are activated by control circuits in the communications devices forming a message transfer route, there being no software-controlled elements in the routing control circuits. Preferably, the characters and the registers are eight bits wide. Other parallel data transfer arrangements, corresponding to the character width of a message, are possible.

A message transfer is abandoned by disrupting the links between the chain of registers and the message continues to be stored at the communications device associated with the source or addressing processing device.

Preferably, each communications device is capable of making several attempts at transferring a message provided by its associated processing device.

Preferably, each communications device is capable of making further attempts, following the abandoning of a message transfer, at transferring a message provided by its associated communications device, at irregular intervals.

The arrangement of making further attempts at message transfer at irregular intervals reduces the probability of dynamic deadlock, that is, a situation where a blockage occurs at a communications device because a repeated message arrives at regular intervals which coincide with that communications device being fully loaded.

In a preferred form of the multiprocessor data processing system, the interface between each communications device and its associated processing device is provided by a memory unit belonging to the processing device. Access of a communications unit to a memory unit may be by direct memory access (DMA) or through a dual port structure whereby the communications device has access by way of one port and a processing unit, which with the memory unit forms the processing device, has access by way of another port.

Preferably, each communications device includes a communications unit that has a structure facilitating connection with other similar communications units for the transfer of messages, and a buffer interface control unit that has a structure facilitating its connection between a communications unit and a processing device for the transfer of messages towards the communications unit and the transfer of information towards the processing device.

The communications units of a network perform the functions required for establishing a route between a communications device serving an addressing processing device that is an information source and a communications device serving an addressed processing device that is to receive the information, and of transferring the information as a part of a message. The only buffer interface control units involved in a message transfer are those serving the addressing processing device and serving the addressed processing device.

The buffer interface control unit that serves a processing device providing information performs the functions, at that time, of transferring the information from the processing unit, assembling a message, and transferring the message to the associated communications unit. The buffer interface control unit that serves the processing device that is receiving information performs the functions, at that time, of absorbing the message received by the associated communications unit, extracting the information, and transferring the information to the processing device.

For any n-dimensional network, the communications devices are identical and do not place any constraints on the size of the network because of the modular form of the devices. The communications devices are adaptable to suit different values of n without changes in basic design.

Also, the communications devices are not dedicated to any particular type of processing device, and a network of the communications devices may be provided for connection to a plurality of unspecified processing devices to form a multiprocessor data processing system.

The plurality of unspecified processing devices may be expected to operate at different speeds one from the other.

During path building the advance of a message takes place at a rate compatible with a relatively slow processing device.

When the message header reaches its destination, an assessment is made by the destination buffer interface control unit as to the rate at which the source is able to deliver the message and a clock signal at the appropriate rate is provided.

A communications device may include an input multiplexer and an output multiplexer which provide at least three transfer ports, a routing logic circuit for controlling the input and output multiplexer, a supervising logic circuit for controlling the routing logic circuit, a handshaking logic circuit providing signalling ports, and a buffer interface control unit connected to one transfer port of the multiplexer providing a terminal port for the communications device.

The combination of an input multiplexer and an output multiplexer and routing logic circuit provides one transfer channel in a communications device.

A communications device may include a plurality of channels controlled by a supervising logic circuit providing a plurality of transfer routes through the communications device.

A buffer interface control unit may include a bidirectional information transmission gate with first and second storage means, data ports connected to the transmission gate, a message forming logic circuit for providing address characters connected to the transmission gate, a first control logic circuit for controlling the transmission gate, a second control logic circuit for controlling the first control logic circuit, and signalling ports connected to the first and second control logic circuits.

A network of communications devices each having a free terminal port for connection to a processing device may be provided as a stand-alone sub-system.

A multiprocessor data processing system in accordance with the invention, and communications and buffer interface control units for a multiprocessor data processing system in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:: Fig. 1 is a diagrammatic representation of a part of a multiprocessor data processing system, comprising a network of communications devices connected to respective processing devices (not shown), showing nine of the communications devices and the links between adjacent devices and illustrating, by bold arrows, a route along which a message may be transferred in the network, Fig. 2 is a diagrammatic representation of a part of a multiprocessor data processing system, comprising a network of communications devices connected to respective processing devices (not shown), showing sixteen of the communications devices and bi-directional links between adjacent devices, Fig. 3 is a diagrammatic representation of a complete multiprocessor data processing system comprising sixteen communications devices and respective processing units (not shown), arranged in a of four-row and four-column array, with bi-directional links between adjacent communications devices and between the respective end communications devices of the rows and columns, Fig. 4 is a block diagram representation of one of the communications devices comprising a communications unit and a buffer interface control unit connected to elements of a processing device that is served by the communications device, Fig. 5 is a block diagram representation of a communications unit, Fig. 6 is a block diagram representation of shift registers belonging to communications units involved in establishing the communications path shown in Fig. 1, Fig. 7 is a block diagram representation of the connections between a communications device and its associated processing device, Fig. 8 is a timing diagram illustrating the voltage waveforms existing at a communications device during a period when it is unable to meet a request from a neighbouring communications device for the transfer of a message, Fig. 9 is a timing diagram illustrating the voltage waveforms existing at a communications device during the initial stages of its acceptance of a message from its "south" neighbouring communications device and during the initial stages of its transfer of the message to its "west" neighbouring communications device, Fig. 10 is a timing diagram illustrating the voltage waveforms existing at a communications device when there is a transfer of a part of a message from its "south" neighbouring communications device and when its "west" neighbouring communications device indicates, initially, willingness to accept a message but then withdraws from the operation, Fig. 11 is a timing diagram illustrating the voltage waveforms existing at a communications device, during the transfer of a message involving the "south" neighbouring communications device and, the "west" neighbouring communications device, including the extension of the route and the passing on of the header, Fig. 12 is a timing diagram illustrating the voltage waveforms existing at a communications device when the "west" neighbouring communications device and the "south" neighbouring communications device are involved in transferring a message but the operation is aborted by a signal from the destination to abandon the transfer, Fig. 13 is a block diagram representation of a buffer interface control unit that, as part of each communications device, is positioned between the network communications unit and a processing device served by the communications device, Fig. 14 is a timing diagram illustrating the voltage waveforms existing at a buffer interface control unit when the buffer interface control unit is transmitting information to a processing device, Fig. 15 is a timing diagram illustrating the voltage waveforms existing at a buffer interface control unit when the buffer interface control unit is receiving information from a processing device, Fig. 16 is a timing diagram illustrating the voltage waveforms existing at the processing device port of a buffer interface control unit when the buffer interface control unit is being read by the processing device to obtain status information.

Fig. 17 is a timing diagram illustrating the voltage waveforms existing at the processing device port of a buffer interface control unit during the writing of a command from the processing device to the buffer interface control unit, and, Fig. 18 is a timing diagram illustrating the voltage waveforms existing at the processing device port of a buffer interface control unit during message transfer by DMA (direct memory access) to and from a memory unit used by a processing device served by the buffer interface control unit.

Referring to Fig. 1 of the accompanying drawings, a multiprocessor data processing system includes a rectangular array of communications devices, nine communications devices 11, 12, 13, 21, 22, 23, 31, 32, and 33, of an array, being shown. It is to be assumed that the nine communications devices are a part of a larger array, in which case each of the eight outer communications devices is connected to further neighbouring communications devices. Routes such as that shown linking the device 33 to the device 11 by way of the devices 12, 22 and 32 may be used in the array to permit communication between the devices 33 and 11. The communications connections shown are unidirectional and will effect the flow of information from left to right and top to bottom, referred to the figure.Information transfer from any one of the communications devices to any other of the communications devices and such transfer may be achieved by means of bidirectional communications connections which are assigned a direction for the duration of a message transfer. A processing device (not shown) is connected to each of the communications devices via a transfer port.

A multiprocessor network with sixteen communications devices and bi-directional connections is shown in Fig. 2 of the drawings. Again, there is a processing device (not shown) connected to each of the communications devices.

Referring to Fig. 2, not only is the communications device 11 able to transfer information to the communications device 44 but the communications device 44 is able to transfer information to the communications device 11, that is, information transfer from left to right, and from right to left, referred to the figure, is possible (and also top to bottom and bottom to top).

Referring to Fig. 3 of the accompanying drawings, the connections at the outermost rows and columns of a multiprocessor network may be wrapped around, as shown, in order to provide a multiprocessor network in which each communications device is an element in an endless row and in an endless column of an array of communications devices. Bidirectional communications connections are shown in Fig. 3 and provide the greatest flexibility as regards the number of available communications paths between any two communications devices of the network but unidirectional communications connections may be used, resulting in some loss of flexibility in selecting a communications route for message transfer.

The average route length may be substantially reduced by wrapping the network to make closed loops of the rows and columns.

The multiprocessor networks represented by each of Figs. 1 to 3 include data processing devices and each communications device of any of Figs. 1 to 3 includes a fifth connection providing means for connection to a data processing device.

Referring to Fig. 4 of the accompanying drawings, each communications device, for example the communications device 22 of Fig. 1, includes a communications unit, for example the unit 220, and a buffer interface control unit, for example the unit 221. The communications unit 220 has five input/ output ports, four of which form the connections with the communications unit of the neighbouring communications devices. The fifth input/output port is connected to the buffer interface control unit 221 which, in turn, has an input/output port for connection to a processing device which includes a processing unit 1 and a memory 2.The four input/output ports that are connected to the communications units of the neighbouring communications devices are the transfer ports for the communications device to which they belong and the buffer interface control unit for each communications device provides a terminal port for connection to a processing device.

In the operation of the multiprocessor network, data processing devices connected to respective communications units by way of buffer interface control units carry out their assigned tasks and, from time to time, send information along the communications network to other processing devices, and receive information from other processing devices along the communications network. The information is sent by the communications devices in a message formed that includes administrative information such as the source communications device and the destination communications device. The destination information of each message includes the address of the communications device serving the addressed processing device and is used to effect the routing of the message.The destination address consists of two fields, an x field and a y field, where the x field represents the number of columnto-column steps and the y field represents the number of rowto-row steps that the message must take in travelling through an array of communications devices, each as is represented by any one of Figs. 1 to 3, between the addressing processing device and the addressed processing device.

If in the array of communications devices represented by Fig.

2, say, the devices 12, 23, 32 and 21 are considered to be "north", "east", "south", and "west", respectively, of the device 22, then, within the array, column-to-column steps are east-west movements and row-to-row steps are north-south movements. As messages are moved around the array of communications devices the x field of the address is decremented for each step of east-west motion and the y field of the address is decremented for each step of north-south motion. Information as to the direction in which there is to be movement is contained in the address itself as a result of its being in two's complement code and the destination has been reached when both the x and y fields are zero.As each step is executed, the address information is examined by the communications device holding it by comparing it with zero and the sign digit of the result is used to determine the direction in which the information is to be moved, when there is a non-zero result. When there is a zero result, the message is passed to the processing device being served by that communications device via the terminal port. The number of communications devices in an array and the number of digits used in the address information are related, the number of communications devices in an array as represented by Fig. 1 or Fig. 2 being, for example, of the order of 256, for an address 8 bits wide.

A multiprocessor data processing system as represented by any one of Figs. 1 to 3 has processing devices connected, as explained above, to the communications devices that form the communications network. In the operation of the data processing system, communication is initiated by the processing device providing the message and the process of passing on the message has three stages, these being the establishing of a transfer path, message transfer, and transfer path collapse. As has been explained above, the message includes information as to the destination and the source of the message. A message may include between 32 and 128 bytes of information.The establishing of a transfer path begins when the communications device serving a source addressing processing device sends a request to a neighbouring communications device for the establishing of a message transfer path in the direction of the eventual destination or addressed processing device. The neighbouring communications device will reply by either granting or rejecting the request. When the request for the establishing of a message transfer path is granted, the message is transferred to the neighbouring communications device under the control of clock pulses supplied by the neighbouring communications device.

The neighbouring communications device then assumes responsibility for passing on the message to one of its neighbouring communications devices in the direction of the eventual destination processing device, and so on, until the message reaches the communications device that serves the destination processing device. When the message reaches the communications device that serves the destination processing device, it is transferred from the communications device to a memory unit used by the destination processing device.

When the request for establishing a message transfer path is rejected by a communications device, attempts are made to find an alternative route that satisfies the constraints of the (hardwired) routing algorithm. If an alternative route is obtained, the message will be transferred until the destination communications device is reached provided that alternative routes are found whenever a message transfer request is refused.

After the message header has been passed on to a neighbouring communications path the communications device enters the message transfer state. The communications device remains in this state until a collaps signal is received from the neighbouring communications device to which the header was passed.

A train of clock pulses is propagated back down the chain of connected communications devices from the communications device containing the header, or the destination or addressed communications device, to the source or addressing communications device. Each stage in the route has a single element buffer. At each transition of the clock a character from the previous communications device, that is nearer the source, is latched into the buffer register. On the same transition the character which was in the buffer is latched into the next stage in the route, that is closer to the destination.

Transfer path collapscis initiated in two ways. Firstly, when no route is available to pass on the header of the message which satisfies the constraints of the hardwired routing algorithm. Secondly when a collapse command is written to the buffer interface control unit at the destination or addressed communications device by the processing device at that node. On receiving a transfer path collapse signal the communications device releases the resources used in the transfer and propagates the collapse signal towards the source or addressing communications device. When the transfer path collapse signal reaches the source communications device all resources used by the message are freed.

In the multiprocessor network represented by any one of Figs. 1 to 3, each communications device has two transfer channels in order to reduce the occurrences of the rejection of a transfer route request, that is, each communications device is capable of providing two transfer routes at the same time. Thus, when the transfer directions are identified as "north", "east", "south" and "west" to neighbouring communications devices, and "home" to the associated processing device, for a communications device, the communications device is capable of granting transfer routes between any two pairs of the transfer directions provided that no one transfer direction is required for both transfer routes. The two transfer channels, which may be identified as channel P and channel Q, are identical as regards message transfer, but have different priorities as regards the granting of transfer routes. Suitable priorities are priority (P) = (n,s,h,w,e) and priority (O) = (e,w,h,s,n), where n, s, , w, e represent "north", "south", "home", "west", and "east", respectively.

There are other suitable priorities for the channels P and Q, such as for example, priority (P) = (n,e,h,w,s) and priority = =(s,w,h,e,n), that provide similar performance to those indicated previously. The performance of the network is alterable to some extent by the allocation of priorities in the two channels. For example, the two channels may have identical priorities priority (P) = priority (0) = (n,e,s,w, h) resulting in "north" and "east" bound messages encountering more refusals. The handling of transfer routes in a completely random manner is also possible.

In the operation of a multiprocessor network as represented by any one of Figs. 1 to 3, the following regulations are applied: (a) An incoming message to a communications device has priority over any message the communications device is required to transmit for its associated process ing device.

(b) A processing device must receive a message from its associated communications device when inactive, (c) Messages are not sent to a faulty processing device, being aborted at the addressing or source communications device.

(d) A partly established transfer route is abandoned at the occurrence of a blockage to extending the transfer route.

(e) An addressing or source communications device makes several attempts to send a message, assuming failure to do so initially, at random intervals dependent on the-nature of the blockage causing the failure.

(f) A communications device in a wait state may receive incoming messages.

Referring to Figs. 1 to 3, a suitable format for a message is H1 ... Hn Nadrs Rl ... Rn:La:tb:di ... dn Ca Cb where H1 ... Hn is the destination address in a particular plane, Nadirs is the number of address bytes, R1 ... Rn is a return address (the complement of the destination address), La and Lb are data length indicators, and Ca and Cb are checksum digits for error detection.

As is shown in Fig. 4, each communications device includes a communications unit and a buffer interface control unit. Transfer routes through the network are established by the communications units which treat connections to the buffer interface control units, linking the communications units to the processing devices, as transfer ports.

Referring to Fig. 5 of the accompanying drawings, a communications unit, represented in block diagram form, includes a first input multiplexer 2231, a second input multiplexer 2232, a first output multiplexer 2237, a second output multiplexer 2238, an input/output handshaking line multiplexer 2233, a first channel controller 2234, a second channel controller 2235, and a central controller 2236.

Referring to Fig. 5, the first input multiplexer 2231 has a byte-wide (8-bit) data input port for connection to a data output port of a communications unit to its "north" and there are further byte-wide data input ports for connection to respective neighbouring communications units to its "east", "south", and "west". In addition, the first input multiplexer 2231 has a byte-wide data input port for connection, by way of a buffer interface control unit, to a data output port of a processing device such as is represented by the processing unit 1 and memory 2 of Fig. 4, when the processing device is served by the communications unit represented by Fig. 5.The first output multiplexer 2237 has respective byte-wide data output ports for connection to data input ports of its neighbouring "north", "east", "south" and "west" communications units and for connection, by way of a buffer interface control unit, to a data input port of the processing device served by the communications unit. The second input multiplexer 2232 is substantially identical to the first input multiplexer 2231 and the second output multiplexer 2238 is substantially identical to the first output multiplexer 2237.The first input multiplexer 2231, the first output multiplexer 2237, and the first channel controller 2234 provide a first channel of the communications unit, and the second input multiplexer 2232, the second output multiplexer 2238, and the second channel controller 2235 provide a second channel of the communications unit.

The input/output handshaking line multiplexer 2233 and the central controller 2236 exercise control of the two channels of the communications unit. For the purposes of control, the input/output handshaking line multiplexer 2233 has a first pair of output handshaking lines which, for the purposes of describing the operation of a communications unit, are designated NA1 and NA2, and a first pair of input handshaking lines, designated NB1 and NB2, for cross-connection to the south-facing (SA1, SA2, SB1, SB2) handshaking lines of the neighbouring communications unit to the "south" of the subject communications unit. Similarly, the input/ output handshaking line multiplexer has sets of handshaking lines for connection to handshaking lines of the neighouring communications unit.These further sets of handshaking lines are designated EA1, EA2, EB1, EB2 (for east), SA1, SA2, SB1, SB2 (for south), and WA1, WA2, WB1, WB2 (for west). The input/output handshaking line multiplexer 2233 has a further set of handshaking lines PAl, PA2, PB1, PB2 for connection to a buffer interface control unit that is positioned between the subject communications unit and a processing device served by the subject communications unit.

The operation of a communications unit such as is represented by Fig. 5 will be described with reference to Figs. 8 to 12, and also with reference to Fig. 1 since its operation involves its interaction with its neighbouring communications units. Referring to Figs. 1, 5 and 8, the central controller 2236, through the input/output handshaking line multiplexer 2233 (Fig. 5), scans the unused input handshaking ports for incoming service requests. Assuming that the central controller 2236 of Fig. 5 belongs to the communications unit 22 of Fig. 1 and the "south" communications device unit 32 requests the establishment of a transfer path, the request from the communications unit 32 will appear, as shown in Fig. 8, as a change in level on its handshaking line SB1 at the time ta while its handshaking line SB2 remains undisturbed.The central controller 2236 of the communications unit 22 acknowledges the request from the communications unit 32 by changing the level of the handshaking line SA1 at a time tb (Fig. 8), and, because Fig. 8 represents the situation where the communications unit 22 is unable to handle the transfer of a message from the communications unit 32, so informs the communications unit 32 by maintaining its handshaking line SA2 at a low voltage level. In due course, at time tg# the communications unit 32 withdraws its request by returning the handshaking line SB1 to a low voltage level and the communications unit 22 removes its acknowledgement at time th by taking the voltage level of the handshaking line SA1 to a low value.

Referring to Figs. 1, 5 and 9 of the accompanying drawings, the sequence of exchanges on the handshaking lines of the communications unit 22 leading to the acceptance by the communications unit 22 of a request from the "south" communications unit 32 for a transfer path, is shown in Fig.

9. The request from the communications unit 32 is made on its handshaking line NA1 to the communications unit 22 and, as shown in Fig. 9, is received by the communications unit 32 on its handshaking line SB1 at a time ta. The request is acknowledged by the communications unit 22 at a time tb on its handshaking line SA1 and, at the same time, the acceptance of the request is sent by the communications unit 22 on its handshaking line SA2 (and received on the handshaking line NB2 of the communications unit 32).The communications unit 22 receives a message during the period between the time tb and a later time, tc and, at the time tc, the communications unit 22 sends a request to the "west" communications device 21 for establishing a communications link by changing the voltage level on the handshaking line WA1. The "west" communications unit 21 replies to the request by acknowledging it on the handshaking line WB1 at the time td and informs the communications unit 22, by a change in voltage level on the handshaking line WB2 at the time td, that the request for a transfer is granted.Therefore, at the time td, a message from the communications unit 32 will have passed through the communications unit 22 which will then be occupied in transferring it to the communications unit 21 for onward passage to its destination (unless, of course, the communications unit 21 is its destination).

Referring to Figs. 1, 5 and 10 of the accompanying drawings, the sequence of exchanges on the handshaking lines of the communications unit 22 leading to the acceptance by the communications unit 22 of a request from the "south" communications unit 32 for a transfer path, and the subsequent failure of the communications unit 22 to establish a transfer path to the communications unit 21, is shown in Fig.

10. Referring to Fig. 10, the sequence of events from the time ta to the time tc is as for the same times in Fig. 9.

At time td, however, the communications unit 22 receives acknowledgement on its handshaking line WB1 of its request for a transfer path but there is no change of voltage on its handshaking line WB2 indicating refusal of the request by the communications unit 21 which withdraws its acknowledgement at time te. Soon after, at time tf, the communications unit 22 withdraws its request and at the time tg the transfer connection is broken. The handshaking link with the communications unit 32 is broken at the time th, leaving the communications unit 22 uncommitted to the transfer and free to execute other transfers.

Referring to Figs. 1, 5 and 11 of the accompanying drawings, the sequence of exchanges on the handshaking lines of the communications unit 22 leading to the acceptance by the communications unit 22 of a request from the "south" communications unit 32 for a transfer path, and subsequent transfer of a message between the units 32 and 22 is shown in Fig. 11. Referring to Fig. 11, the communications unit 22 receives a "request" on its line SB1 at the time ta, and acknowledges the "request" on its line SA1 and accepts the transfer path at time tb by the voltage rise on its line SA2.

The communications unit 22 provides a clock pulse on its line SA2 shortly after the time tb to transfer the information label (destination and source data) and, subsequently, provides clock pulses on its line SA2 to continue with the transfer of the message.

Referring still to Figs. 1, 4, 5 and 11, the further transfer of the message, being received from the "south" neighbouring communications unit 32, to the "west" neighbouring communications unit 21 is carried out by a "request" to the "west" communications unit 21 at a time tc on the line WA1, resulting in an acknowledgement from the "west" communications unit 21 at a time td on the line WB1 and clock pulses from the "west" communications unit 21 from a time tf on the line WB2, and the continued provision of clock pulses for executing the message transfer.

Referring to Figs. 1, 4, 5 and 12 of the accompanying drawings, the sequence of exchanges on the handshaking lines of the communications unit 22 towards and at the end of transfer operations with, respectively, its "west" neighbouring communications unit 21 and it "south" neighbouring communications unit 32, are shown in Fig. 12. In the transfer operation with the "west" communications unit 21, the "west" communications unit 21 is receiving a message and is providing clock pulses on the line WB2. The "west" communications unit 21 stops sending clock pulses at a time tx and also, at that time, withdraws its acknowledgement of the "request" for transfer by reducing the voltage level on the line WB1.The sending communications unit 22 then withdraws its acknowledgement for the maintenance of the link with the "south" neighbouring communications unit 32 by reducing the voltage on the line SA1 at the time ty and at the same time withdraws from the link by terminating clock pulses on its line SA2. The lines go to an open-circuit condition a bit later at the time tz.

The situation represented by Fig. 12 may occur when the "west" communications unit 21 is the destination communications unit and the "west" communications unit withdraws from the message transfer because it has received all of the message. Alternatively, the situation represented by Fig. 12 may occur when the "west" communications unit 21 is acting as a link in the message transfer operation and withdraws before the completion of the message transfer, either because it is itself unable to extend the link or because a communications unit further on is unable to extend the link. As will be evident from the description of operation according to Fig.

12, the withdrawal of any communications unit from a message transfer link results in the dissolution of the link as the "withdraw" condition propagates back to the source communications unit. The "withdraw" condition is initiated by the communications unit furthest from the source communications unit when the furthest unit (the one responsible for extending the link towards the destination communications unit) is unable to extend the link.

The manner in which a message passes between a communications device that serves a source processing device that is providing information and a communications device that serves a destination processing device that is receiving information will now be described with reference to Fig. 6 of the accompanying drawings.

Fig. 6 shows a first buffer interface control unit 111 that is connected to a second buffer interface control unit 341 by way of a chain of registers 112, 122,/322, 332 and 342. The first buffer interface control unit ill is connected to a first processing device 100 consisting of a memory 20 and a processing unit 10 and the second buffer interface control unit 341 is connected to a second processing device 300 consisting of a memory 30 and a processing unit 40. The buffer interface control units ill and 341, and the registers 112, 122, 222, 322, 332 and 342 have a common clock line 3 that distributes clock pulses to the units and the registers. The register 112 shown in Fig. 6 belongs to the communications unit 11 shown in Fig. 2, the register 122 shown in Fig. 6 belongs to the communications unit 12 shown in Fig. 2, the register 222 shown in Fig. 6 belongs to the communications unit 22 shown in Fig. 2, the register 322 shown in Fig. 6 belongs to the communications unit 32 shown in Fig. 2, the register 332 shown in Fig. 6 belongs to the communications unit 33 as shown in Fig. 2, and the register 342 shown in Fig. 6 belongs to the communications unit 34 shown in Fig. 2.The first buffer interface control circuit 111 shown in Fig. 6 is therefore connected between the register 112 that belongs to the communications unit 11 shown in Fig. 2 and the first processing unit 100 and, similarly, the buffer interface control unit 341 is connected between the register 342 that belongs to the communications unit 34 shown in Fig. 2 and the processing unit -300. Referring to Figs. 2 and 6, information provided by the processing device 100 is sent to the interface unit 111 which transfers the message to the register 112 belonging to the communications unit 11. The message then progresses through the registers 122, 222, 322, 332, and 342, that is, the message is sent to the communications unit 34 through the communications units 12, 22, 32 and 33.The message arriving at the communications unit 34 is held in its register 342 from where it is transferred to the processing device 300 through the buffer interface control unit 341. Fig. 6 therefore represents a message transfer path that extends between the source processing device 100 and the destination processing device 300 through the communications units 11, 12, 22, 32, 33 and 34 shown in Fig. 2.

Referring still to Fig. 6, the message being passed from the source processing unit 100 to the destination processing unit 300 has a "head" portion and a "body" portion. The "head" portion includes source and destination information used in establishing the message transfer route. The destination information carried initially by the "head" of the message represents the displacement of the source processing device 100 from the destination processing device 300 in terms of the coordinates of the network.The destination information in the "head" of the message is altered systematically by the respective communications units 12, 22, 32, 33, and 34 and the "head" of the message is so directed by the communications units that the displacement information carried by the "head" of the message is reduced to zero at the communications unit 34, which is the communications unit that serves the destination processing device 300. Since the displacement information in the "head" of the message is zero at the communications unit 34, the message is passed to the buffer interface control unit 341 associated with the communications unit 34 and reaches the processing device 300.

It is instructive to consider the operation of a communications unit such as is represented by Fig. 5 with reference to the structure represented by Fig. 11. Referring to Fig. 5, the central controller 2236, through the input/output handshaking line multiplexer 2238, scans the unused input handshaking port for incoming service requests.

Assuming that the central controller 2236 belongs to the communications device 22 of Fig. 1 and that the "south" communications device 32 requests the establishment of a message transfer path, the request from the communications device 32 will appear, as shown in Fig. 11, as a change in level on the handshaking line SB1 at a time ta while the handshaking line SB2 remains undisturbed. The central controller 2236 checks on whether one of the channels 2234 or 2235 is free and, provided that one of the two channels is free, informs the communications device 32 that a channel is available by changing the level of the handshaking line SA1 at a time tb, as is shown in Fig. 11, and providing a clock pulse on the handshaking line SA2 at the time tb.The "head" of the message is transferred to a data register in one of the channels 2234 or 2235 of the communications unit represented by Fig. 11 during the clock pulse and the handshaking line SA2 is maintained at a high voltage level after the clock pulse. The communications unit represented by Fig. 5 examines the destination information carried by the message "head" that it has stored in its data register and determines whether the message "head" has reached its destination or if it is to be passed on.Assuming that the message "head" is to be passed on to the "west" communications device 21, the address displacement value in the "head" is decremented and routing logic in the first channel 2234 causes the central controller 2236, by way of the input/output handshaking line multiplexer 2233, to change the level of the handshaking line WA1 at time tc (Fig. 11) while the handshaking line WA2 remains undisturbed, signalling to the "west" communications device 21 the request for the establishing of a message transfer path.Assuming acceptance of the request by the "west" communications device 21, the communications unit receives a level change on its handshaking line WB1 at time td (Fig. 11) and also a clock pulse, between the time td and a time tf, that transfers the "head" of the message to the communications unit of the communications device 21.

Assuming that the "west" communications device 21 is the destination communications device, the communications device 21 provides clock pulses on the handshaking line WB2 at time tf onwards effecting the transfer of the message and the clock pulses are transferred to the handshaking line SA2 at the same time, thereby effecting the transfer of the message from the communications device 32 through the communications device 22 to the communications device 21 in the form of a "caterpillar".

Fig. 7 of the accompanying drawings illustrates a connection arrangement between a communications device and a processing device in which the communications device, consisting of a communications unit 220 and a buffer interface control unit 2211, has a direct memory access (DMA) form of connection, the processing device consisting of a DMA controller 3, a processing unit 1, and a memory 2.

Referring to Fig. 7, the buffer interface control unit 2211 provides the access ports required by the processing device to the communications network to which the communications unit 220 belongs. The transfer of messages between the communications network and the processing device attached to the buffer interface control unit 2211 takes place by way of the buffer interface control unit 2211. A message for which the control unit 220 is the destination unit will be passed to the buffer interface control unit 2211 for transfer to the processing device attached to the buffer interface control unit 2211. A message initiated by the processing device attached to the buffer interface control unit 2211 will be passed to the buffer interface control unit 2211 for transfer to the communications network.

The transmission of a message from the processing device attached to the buffer interface control unit 2211 will be described with reference to Figs. 7 and 14. The processing device provides a destination address which the buffer interface control unit 2211 stores in an address register.

After the destination address is stored, the operation must wait until a status register in the buffer interface control unit 2211 indicates "not busy" in response to a polled request for "status". Once the status register indicates "not busy", further preparation is made for the transmission by instructing the DMA controller 3 to be ready to provide the remainder of the head or header block information immediately after the destination address that is held in the address register. Once the DMA controller 3 has been set up as required for the transmission, a command register in the buffer interface control unit is set to initiate a "send" command and the command is sent.When the "send" command has been issued and the status register indicates a "busy" status, the transmission of the message will proceed. In the transmission of the message, the DMA controller 3 is operated in bursts as the head of the message moves towards its destination, the DMA controller 3 being held captive during that period, that is, during the building of a path between the source processing device and the destination processing device. The head of the message does not progress at a constant rate during the path building operation and the DMA controller 3 is operated in bursts to match the transmissions from the DMA controller 3 to the progress of the message head during the path building phase of the operation. The DMA controller 3 is made to wait during the periods when the message head is not being moved.When the message head reaches the destination address, the message transfer operation continues at a constant rate until completion under the control of the destination DMA controller and at the full transfer rate of the destination DMA controller.

Referring to Figs. 7 and 14, the buffer interface control unit 2211 has a message for transmission at a time to and so indicates by changing the level of the handshaking line Al at a time tl. The communications unit acknowledges the request on the line Al by changing the level of the handshaking line A2, connected to the buffer interface control unit inputs Bl and B2, at a time t2 soon after which, at a time t3, the buffer interface control unit 2211 returns the handshaking line Al to its low level. Also at the time t21 the communications unit 220 indicates that it will accept the message by changing the level of the handshaking line B2 and effects the transfer of the head of the message by providing an acknowledge signal on the handshaking line B2.

The link between the buffer interface control unit 2211 and the communications unit 220 remains in being as long as the handshaking line B1 remains at the high level. The buffer interface control unit 2211 is able to determine whether a message has reached its destination by examining the number of bytes that have passed through the DMA controller 3 apart from the message head. If, for example, at least thirtythree bytes have passed through the DMA controller 3 and there are 256 nodes in the network (16 x 16), then the message must have reached its destination source, the maximum number of steps available in the network being sixteen.

The reception of a message by a buffer interface control unit, for transfer to a processing device served by the buffer interface control unit, will be described with reference to Figs. 7 and 15.

A message reception operation is initiated when the communications unit 220 requests a link with the buffer interface control unit 2211 by raising the voltage level of the handshaking line B1 at a time t4 while maintaining the handshaking line B2 at a low voltage level. Acceptance of the request for a transfer link is indicated by the buffer interface control unit 2211 by the voltage levels of the handshaking lines Al and A2 being raised at a time t5, and between the time t5 and a time t6 the buffer interface control unit 2211 provides a clock pulse on the handshaking line A2, to effect the transfer of the message head.The message head having been transferred, the buffer interface control unit 2211 provides, from a time t7, a train of clock pulses, on the handshaking line A2, that effect of the transfer of the body of the message through the DMA controller 3 into the memory 2. The train of clock pulses on the handshaking line A2 pass along to each of the handshaking lines A2 along the route occupied by the message and the route dissolves when the message has been transferred.

Figs. 16 to 18 of the accompanying drawings show the control voltages exchanged between the buffer interface control unit 2211 and the DMA controller 3.

Referring to Fig. 16, in the reading of a status byte from the buffer interface control unit 2211, a low voltage applied to the terminal CS of the buffer interface control unit 2211 and a high voltage applied to its terminal RDWR is understood by the buffer interface control unit 2211 to mean that its status is to be read.

Referring to Fig. 17, in the writing of a command to the memory 2, a low voltage applied to the terminal CS of the buffer interface control unit 2211 and a low voltage applied to its terminal RDWR is understood by the buffer interface control unit 2211 to mean that a command is to be written to it.

Referring to Fig. 18, a DMA (direct memory access) cycle is started by a change from a high to a low voltage at the REQ terminal of the buffer interface control unit 2211. The DMA controller 3 then activates data buffers in the buffer interface control unit 2211 by providing a high voltage at the ACK terminal of the buffer interface control unit 2211 and message transfer is executed at each falling edge of a clock signal applied to the DTC terminal of the buffer interface control unit 2211. The writing of a message to the memory 2 takes place while the RDWR terminal of the buffer interface control unit 2211 is provided with a high voltage and the RDY terminal of the buffer interface control unit is provided with a high voltage.The reading of a message from the memory 2 takes place while the RDWR terminal of the buffer interface control unit 2211 is provided with a low voltage and the REY terminal of the buffer interface control unit 2211 is provided with a high voltage.

The RDY signal is used as a BUSY/WAIT signal to regulate the rate at which the DMA operation is conducted. When the buffer interface control unit is receiving a message from the network, the RDY signal is provided until the buffer interface control unit receives a data clock pulse on its input B2. The RDY signal is removed when the DTC signal is provided by the DMA controller until the next data byte.

When the buffer interface control unit is transmitting a message to the network, the RDY signal is generated internally at a rate dependent on the programmed transfer rate.

Fig. 13 of the accompanying drawings shows in detail the structure of a buffer interface control unit as is represented by the buffer interface control unit 2211 of Fig. 7.

Referring to Fig. 13, a buffer interface control unit includes a control logic circuit 22110, a group of registers 22111, transmission gates 22112 and 22113 that include storage means, buffers 22114 and 22115, and a DMA control circuit 22116. The DMA control circuit 22116 has input terminals for the signals DTC and ACK, and output terminals for the signals REQ and RDY. The DMA control circuit is connected to the control logic circuit 22110 which has input terminals for the signals CS and RDWR. The control logic circuit also has input terminals for the handshaking signal B1 and B2, and output terminals for the handshaking signals Al and A2. The group of registers 22111 perform the storage of command, status, and address data.The command and status data storage parts of the group of registers 22111 are connected to the control logic circuit 22110 and to the buffer 22112. The address data storage part of the group of registers 22111 is connected to the buffer 22113. The transmission gate 22114 has its input terminal connected to the output terminal 22118 of the buffer 22113, its output terminal connected to an input terminal of the buffer 22112, and its control terminal connected to the control logic circuit 22110. The transmission gate 22115 has its input terminal connected to the output terminal 22117 of the buffer 22112, its output terminal connected to an input terminal of the buffer 22113, and its control terminal is connected to the control logic circuit 22110.The output terminals 22117 and 22118 of the buffers 22112 and 22113 are connected respectively to the processing unit data path and to the network data path.

Referring to Fig. 13, the storage means included in the transmission gates 22112 and 22113 are first-in first-out (FIFO) stores which act as storage buffers between the devices involved in message and information transfer and permit the transfers to proceed between processor devices that have different operating speeds. Also, because of the double buffer storage, an incoming message may be accepted by the buffer interface control unit from the communications unit while the buffer interface control unit is receiving information from its associated processing device. Also, a message being transferred through the network is retained in the storage buffer port of the transfer gate 22113, and is automatically saved if the transfer route is abandoned before reaching the addressed communications device.

It will be evident that the network of communications devices shown in Figs. 1 to 3, say, may exist separately as a sub-system in which each of the communications devices has a free terminal port for connection to a processing device to form a multiprocessor data processing system. Such a network of communications devices imposes no constraints on the processing devices connected to it since each processing device is treated as a source of information or as a destination for information.

Referring to Figs. 1 to 3, the network of communications devices is constructed from identical modules which are, preferably, connected together in a regular cartesian grid but which may be connected together in other structural forms. Also, the structural form of an existing network may be altered by changing the interconnections of the communications devices without any consideration as to the characteristics of any processing devices connected to the network.

The modules or communications devices are identical to one another in a particular network and are themselves independent of the characteristics of any processing device that may be attached to a network for which they form the "bricks'. The communications devices, as the "bricks" of a network, are themselves, by their structure, representative of networks which they form.

The timing part of the structure of each buffer inter face control unit, as represented by Fig. 13, includes a facility for making repeated attempts at message transfer and for making attempts at irregular intervals in order to reduce the chances of dynamic deadlocking of the system, that is, a condition where a message being sent is blocked at a particular communications device because it always reaches that communications device at a time when that device is busy (although that device is not always busy). Also, each buffer interface control unit includes facilities for preventing attempts to transfer messages to faulty processing devices.

The communications devices may be connected to each other by wired links or by optical links. The communications devices and processing devices may also be connected by wired or optical links.

A communications device belonging to one network may be connected, instead of to a processing device, to a communications device belonging to another network, and so on.

The communications devices may include provision for responding to broadcast transmissions, that is, transmissions routed to all the communications devices in the network.

Claims

Claims:

1. A multiprocessor data processing system comprising a network of communications devices connected to respec tive associated processing devices, the communications devices being capable of transferring, among the processing devices, messages containing information generated by the processing devices, wherein each communications device, in operation, transfers messages without the participation of its associated processing device unless its associated processing device is the addressing processing device providing the message or the addressed processing device receiving the message.

2. A multiprocessor data processing system as claimed in claim 1, wherein each communications device has transfer ports for connection to neighbouring communications devices, and a terminal port for connection to its associated processing device.

3. A multiprocessor data processing system, as claimed in claim 2, wherein each communications device, in opera tion, forms messages from information it receives through its terminal port and delivers the messages to its transfer ports, and delivers, through its terminal port, information contained in messages received through its transfer ports and addressed to its associated processing device.

4. A multiprocessor data processing system as claimed in any one of claims 1 to 3, wherein the network of communications devices form a chain in which each communications device is connected to a neighbouring communications device.

5. A multiprocessor data processing system as claimed in claim 4, wherein the chain is in the form of a closed loop.

6. A multiprocessor data processing system as claimed in claim 4 or claim 5, wherein a processing device con nected to a communications device is a first chain is connected also to a communications device in a second chain of communications devices.

7. A multiprocessor data processing system as claimed in any one of claims 1 to 3, wherein the network of communications devices form a multi-dimensional struc ture in which each communications device is connected to each of its neighbouring communications devices.

8. A multiprocessor data processing system as claimed in claim 7, wherein the multi-dimensional structure is wrapped around to provide a plurality of interconnected closed loops.

9. A multiprocessor data processing system as claimed in claim 7 or claim 8, wherein a processing device con nected to a communications device in a first multi dimensional structure is connected also to a communica tions device in a second multi-dimensional structure of communications devices.

10. A multiprocessor data processing system as claimed in claim 7 or claim 8, wherein the multi-dimensional network structure has the form of a regular cartesian grid in which the communications devices occupy the intersection points of the grid and are identified by the coordinates of the points they occupy.

11. A multiprocessor data processing system as claimed in claim 9, wherein each multi-dimensional network struc ture has the form of a regular cartesian grid in which the communications devices occupy the intersection points of the grid and are identified by the coordinates of the points they occupy.

12. A multiprocessor data processing system as claimed in any one of claims 1 to 11, wherein the operating characteristics of each communications device are fixed and are such that a message is always moved in a direction taking it closer to the processing device to which it is addressed.

13. A multiprocessor data processing system as claimed in claim 12, wherein the direction in which a message leaves a communications device is determined by fixed logic elements in the communications device, the address included in the message, and the availability of transfer ports in directions that would take the message closer to the processing device to which it is ad dressed.

14. A multiprocessor data processing system as claimed in any one of claims 1 to 13, wherein a message includes a train of characters that provide an address and informa tion for the processing device to which it is addressed.

15. A multiprocessor data processing system as claimed in any one of claims 1 to 14, wherein a message includes error detection and correction characters.

16. A multiprocessor data processing system as claimed in claim 14 or claim 15, wherein the address characters of a message indicate initially the position of the addressed processing device relative to the addressing processing device, and the address characters are so altered during transfer that they continue to represent the displacement of the message from the addressed processing device.

17. A multiprocessor data processing system as claimed in any one of claims 1 to 16, wherein the transfer of a message includes the reservation of a transfer route through communications devices situated between the addressing processing device and the addressed process ing device.

18. A multiprocessor data processing system as claimed in claim 17, wherein the communications devices are capable of operating cooperatively to transfer address charac ters of a message from communications device to com munications device, and, at each transfer, to allocate registers for the storage of parts of the message to effect the transfer of the message, through a chain of linked registers, from the addressing processing device to the addressed processing device.

19. A multiprocessor data processing system as claimed in claim 18, wherein each communications device includes a first storage means capable of storing a message and, in operation, the communications device associated with the addressing processing device stores, in the first storage means, a message being transferred from the communications device associated with the addressing processing device.

20. A multiprocessor data processing system as claimed in claim 19, wherein each communications device includes a second storage means capable of storing a message and, in operation, the communications device associated with the addressed processing device stores, in the second storage means, a message being transferred to the communications device associated with the addressed processing devices.

21. A multiprocessor data processing system as claimed in claim 19 or claim 20, wherein a message transfer is abandoned by the dissolution of the reserved transfer route when the communication device furthest along the route from the addressing processing device is unable to extend the route.

22. A multiprocessor data processing system as claimed in claim 21, wherein message transfer is abandoned by disrupting the links between the chain of registers and the message continues to be stored at the communications device associated with the addressing processing device.

23. A multiprocessor data processing system as claimed in any one of claims 1 to 22, wherein each communications device is capable of making several attempts at trans ferring a message provided by its associated processing device.

24. A multiprocessor data processing system as claimed in claim 23, wherein each communications device is capable of making further attempts, following the abandoning of a message transfer, at transferring a message provided by its associated processing device, at irregular intervals.

25. A multiprocessor data processing system as claimed in any one of claims 1 to 24, wherein a memory unit is shared by each communications device and its associated processing device to facilitate the transfer of informa tion between the communications device and the process ing device.

26. A multiprocessor data processing system as claimed in any one of claims 1 to 25, wherein each communications device comprises a communications unit that has a structure directed to its connection with other com munications units for the transfer of messages, and a buffer interface control unit that has a structure directed to its connection between a communications unit and a processing device for the transfer of messages towards the communications unit and the transfer of information towards the processing device.

27. A multiprocessor data processing system as claimed in claim 26, wherein each communications unit comprises an input multiplexer and an output multiplexer which provide at least three transfer ports, a routing logic circuit responsive to a message for controlling the multiplexers, a supervising logic circuit for controll ing the routing logic circuit, and a handshaking logic circuit providing signalling ports.

28. A multiprocessor data processing system as claimed in claim 26 or claim 27, wherein each buffer interface control unit comprises a bi-directional information transmission gate with first and second storage means, data ports connected to the transmission gate, a message forming logic circuit for providing address characters connected to the transmission gate, a first control logic circuit for controlling the transmission gate, a second control logic circuit for controlling the first control logic circuit, and signalling ports connected to the first and second control logic circuits.

29. A communications unit for a multiprocessor data process ing system that includes a network of communications devices connected to respective associated processing devices, wherein each communications device, in opera tion, transfers messages directly to its neighbouring communications devices and each communications device includes a communications unit comprising an input multiplexer and an output multiplexer which provide at least three transfer ports, a routing logic circuit responsive to a message for controlling the multi plexers, a supervising logic circuit for controlling the routing logic circuit, and a handshaking logic circuit providing signalling ports.

30. A buffer interface control unit for a multiprocessor data processing system that includes a network of communications devices connected to respective associ ated processing devices, wherein each communications device, in operation, transfers messages directly to its neighbouring communications devices and each communica tions device includes a buffer interface control unit comprising a bi-directional information transmission gate with first and second storage means, data ports connected to the transmission gate, a message forming logic circuit for providing address characters connected to the transmission gate, a first control logic circuit for controlling the transmission gate, a second control logic circuit for controlling the first control logic circuit, and signalling ports connected to the first and second control logic circuits.

31. A multiprocessor data processing system substantially as herein described with reference to, and as illustrated by, the accompanying drawings.

32. A communications unit substantially as herein described with reference to, and as illustrated by, Fig. 5 of the accompanying drawings.

33. A buffer interface control unit substantially as herein described with reference to, and as illustrated by, Fig. 13 of the accompanying drawings.

34. A network of communications devices for a multiprocessor data processing system as claimed in any one of claims 1 to 28, or claim 31, wherein each communications device has a free terminal port for connection to a processing device.