RU1818697C - Device for testing correct operation of superheterodyne receiver - Google Patents

Abstract

Purpose: control of the high-frequency path of serviced and maintenance-free automated radio receivers. The inventive device comprises a receiver, a balanced demodulator, a filter, 3 amplitude detectors, 5 threshold blocks, 3 memory elements, 3 indicators, an input signal simulator, 3 delay elements, 2 phase detectors, 2 OR elements. The goal is to ensure accurate control of the local oscillators of the superheterodyne receiver is achieved by introducing new units, which leads to an increase in the values of complex indicators, decameter reliability; radio lines. 1 ill.

Description

The invention relates to radio communications technology and can be used in adaptive radiotelephone and radiotelegraph communication systems for monitoring the high-frequency path of serviced and maintenance-free automated radio receivers in the intended use mode.

The purpose of the invention is to improve the accuracy of the control of local oscillators of a superheterodyne receiver,

The drawing shows a structural electrical diagram of the proposed device.

A device for monitoring the performance of a superheterodyne receiver 1, consisting of a series-connected high-frequency amplifier 2, a first mixer 3, a first intermediate-frequency amplifier 4, a second mixer 5, a second intermediate-frequency amplifier b and detector 7, the first and second local oscillators 8

and 9, contains in series a balanced demodulator 10, a filter 11, an amplitude detector 12, a first threshold block 13 and a third memory element 32 and a first indicator 15, an input signal simulator 16, consisting of a series-connected intermediate frequency generator 19, a balanced module torus 17, the first mixer 18 and the second mixer 20, the first delay element 21, the input of which is connected to the output of the pseudo-random sequence generator 14, and the output with the second input of the balanced demodulator 10, connected in series to the second delay element 22, the first phase detector 23, the second threshold block 24 and the first memory element 25, connected in series with the third delay element 27, the second phase 28 detector, the third threshold block 29 and the second memory element 30, connected in series with the second amplitude detector 38 fourth threshold

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block 33, the first OR element 36, the second input of which is connected to the output of the first memory element 25, and the second indicator 26, connected in series with the third amplitude detector 34, the input of which is connected to the output of the second detector 9, the fifth threshold block 35, the second OR element 37, the second input of which is connected to the output of the second memory element 30, and the third indicator 31.

The device operates as follows:

The control signal, which is a sinusoidal carrier modulated by a pseudo-random sequence from the generator 14, from the generator 19, is supplied from the output of the balanced modulator 17 of the input signal simulator 16 to the inputs of the first 18 and second 20 mixers, in which the spectrum of the control signal is transferred to the frequency by conversion settings controlled superheterodyne receiver 1, which then goes to its input. The signal passed through the linear path of the superheterodyne receiver 1 controlled, consisting of amplifier 2, first 3 and second 5 mixers, first 4 and second 6 amplifiers, is fed to the input of the first balanced demodulator 10, to the second input of which the signal from the pseudo-random generator 14 sequence, but delayed in the first delay element 21 by an amount equal to the delay time of the control signal during the passage of the linear path of the superheterodyne receiver 1. As a result, the output of the ball meat demodulator 10 is released from the pilot signal phase manipulation tion and represents a harmonic oscillation. G of the output of the balance of the shot of the demodulator, the TO signal is transmitted through the filter 11, tuned to the value of the second intermediate frequency, to the amplitude detector 12 and its output signal is compared in the first threshold block 13 with a predetermined threshold, and the comparison result is stored in the third memory element 32 and is displayed on the first indicator 15. If the tuning frequency i of the superheterodyne receiver 1 being monitored is shifted due to frequency instability and its first and second local oscillators 8 and 9, the harmonic signal from the output of the balanced of the demodulator 10 leaves the passband of the filter 11 and, therefore, the signal from the output of the amplitude detector 12 is the smaller, the greater the offset of the tuning frequency due to the instability of the frequencies of the first 8 and

second 9 local oscillators. At the same time, to increase the accuracy of the control, the frequency stability of the first 8 and second 9 local oscillators controlled by the superheterodyne receiver 1 is monitored.

It is known that the frequency and phase of harmonic oscillations are interdependent, therefore, the frequency instability of the first 8 and second 9 local oscillators can be checked by comparing the phases of the oscillations over a time interval that is a multiple of the oscillation period.

The harmonic signal from the output of the first 8 and second 9 local oscillators is supplied respectively to the first inputs of the first 23 and second 28 phase detectors to their second inputs through the second 22 and third 27 elements

delays, where it is delayed by a multiple of several periods of oscillation

of these local oscillators 8 and 9. If the oscillation phases at both inputs of the first 23 and second 28 phase detectors coincide, their output signals have a maximum value, and if a phase jump occurs, it is minimal. From the outputs of the first 23 and second 28 phase detectors, the signals are supplied to the second 24 and third 29 threshold blocks, respectively, where they are compared with a predetermined threshold, and the comparison result is stored in the first 25 and second 30 memory elements and displayed on the second 26 and third 31 indicators .

In addition, the harmonic signal from the output of the first 8 and second 9 local oscillators is supplied respectively to the inputs of the second 38 and third 34 amplitude detectors. The detected harmonic signal is fed to the inputs of the fourth 33 and fifth of 35 threshold blocks. If the signal level is at

the output of the first 8 or second 9 local oscillator does not correspond to the specified norm, then the output of the fourth 33 or fifth of the 35th threshold block contains an Avari signal, which is fed to the first input of the first 36

or second 37 OR elements.

The first phase detector 23 is designed to compare the oscillation phases at the output of the first local oscillator 8 over a time interval that is a multiple of its oscillation period.

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The second phase detector 28 is designed to compare the oscillation phases at the output of the second local oscillator 9 over a time interval that is a multiple of its oscillation period. The second threshold unit 24 is for comparing the signal level at the output of the first phase detector 23 with a predetermined threshold.

The third threshold unit 29 is for comparing the signal level at the output of the second phase detector 28 with a predetermined threshold.

The second delay element 22 is designed to delay the oscillation from the output of the first local oscillator 8 by a time multiple of its oscillation period.

The third delay element 27 is designed to delay the oscillation from the output of the second local oscillator 9 by a time multiple of its oscillation period.

The first 25. second 30, third 32 memory elements are designed to store the results of the comparison, respectively, in the second 24, third 29 and first 13 threshold blocks.

The first 18 and second 20 mixers are designed to transfer the spectrum of the control signal to the tuning frequency.

The intermediate frequency generator 19 is designed to generate an intermediate frequency signal.

Therefore, the introduction of this set of blocks compares favorably with the prototype, because, in addition to analyzing the deviation of the local oscillator frequency from the nominal value, it will allow you to analyze their output level, monitoring the output level of the local oscillators will improve the accuracy of monitoring the operability of the superheterodyne receiver. decode radio receivers 1.1, - 1.2 times, which will lead to an increase in the values of complex reliability indicators decameter radio lines .

Claims (1)

The claims A device for monitoring the performance of a superheterodyne receiver, comprising a simulator of an input signal, the output of which is information the input of the controlled superheterodyne receiver, a series-connected generator, a pseudo-random sequence, the first delay element, a balanced demodulator, the second input of which is connected to the output of the second intermediate-frequency amplifier of the controlled receiver, a filter, an amplitude detector, and a first threshold block, the first, second, and third memory elements , the first, second and third indicators, serially connected to the second delay element, the input of which is connected to the output of the first local oscillator of the second receiver, the first phase detector, the second input of which is combined with the input of the second delay element, the second threshold block, the third delay element connected in series, the input of which is connected to the output of the second local oscillator of the monitored receiver, the second phase detector, the second input of which is combined with the input of the third delay element and a third threshold unit, characterized in that, in order to increase the accuracy of monitoring the local oscillators of the superheterodyne receiver, second-amplitude amplitudes are connected in series a detector whose input is connected to the output of the first local oscillator, a fourth threshold block and a first OR element, the second input of which is connected to the output of the first memory element, and the output is connected to the input of the second indicator, a third amplitude detector is connected in series, the input of which is connected to the output of the second local oscillator the fifth threshold block and the second OR element, the second input of which is connected to the output of the second memory element, and the output is connected to the input of the third indicator.