RU1815798C - Converter of active power to code - Google Patents

Abstract

The invention relates to electrical measuring equipment and can be used in energy measuring information systems, mode automation devices and digital power meters. The purpose of the invention is to increase the reliability of the converter due to its simplification. The active power to code converter contains a series-connected multiplier 1, an adder 2. A sample-storage unit 3, an integrator 4 with a reset, a voltage-code converter 5 and a computing unit 6, as well as a period identifier 7 and a frequency multiplier 8. The inputs of the multiplier 1 are the input voltage and current buses of the target being monitored, and one of the inputs of the multiplier is also connected to the inputs of the amplifier 7 of the period and the multiplier 8. The output of the multiplier 8 is connected to the clock inputs of the blocks 3 and 6 and the converter 5. and the output you the loop 7 of the period is connected to the reset input of the integrator 4 and an additional clock input of the block 6, the output of which is the output of the converter. The output of the integrator 4 is connected to the second / inverting / input of the adder 2. 2 ill. ate with

Description

Shchig. 1

Ioobrzteke relates to electrical engineering and can be used in energy measuring information systems, mode automation devices and digital wattmeters.

An object of the invention is to simplify a converter.

Figure 1 presents a structural diagram of the proposed Converter; Fig. 2 is a timing chart illustrating its operation.

The active power to code converter contains a series-connected multiplier 1, an adder 2, a sample-storage unit 3, an integrator A with a reset, a voltage-code converter 5 and a computational unit 6, as well as a period identifier 7 and a frequency multiplier 8. The inputs of the multiplier 1 are connected to the input voltage and current buses of the monitored target, and one of the inputs of the multiplier is also connected to the inputs of the amplifier 7 of the period and the multiplier 8. The output of the multiplier 8 is connected to the clock inputs of the blocks 3 and 6 and the converter 5, and the output is the loop 7 of the period is connected to the reset input of the integrator 4 and an additional clock input of the block 6, the output of which is the output of the converter. The output of the integrator 4 is connected to the second (inverting) input of the adder 2.

The converter operates as follows.

The signals Uu (t) and Ui (t), which are proportional to the voltage and current of the controlled circuit, are fed to the inputs of the multiplier 1 via the corresponding buses (Fig. 2 a, b). At the output of the latter, the voltage Uu (t) is formed, defined by the equality:

Uu (t) S-Uu (t) -Ui (t),

where S is the transmission coefficient of the multiplier 1..

The voltage Uu (t) (Fig. 2c) is proportional to the instantaneous power of the circuit being monitored.

The multiplier 8 generates clock pulses with a frequency FT, M times the frequency FU of the controlled voltage (Fig. 2d).

Upon receipt of the first pulse from the multiplier 8 at the time ti 1 / MFu at the output of block 3, a voltage pulse U ((ti) of constant duration T0 is generated (Fig. 2, e), which is fed to the input of the integrator 4. By the end of the time interval on the output of the integrator 4 sets the voltage (Fig.2.e)

ti yJ / UNdt,

where m is the time constant of integrator 4.

For simplicity of analysis, we assume that the current and the amplitude of the output pulses of block 3 do not change for That, because t 0 «1 / FU. In this case we get

h Ј U (n) Uu (ti)

The converter 5 generates an output code NI corresponding to the voltage AND, which is supplied to the information input of block 6. The voltage AND from the output of the integrator 4 is supplied to the inverting input of the adder 2.

When a second pulse arrives from the multiplier 8 at time t2 2 / MFu, a voltage pulse of duration d Oi with an amplitude U (t2) Uu (t2) (2) -Uu (ti) is generated at the output of block 3 at 12 times the output of the integrator 4 corresponding to the voltage pulse U (t2) will be:

1

t0

 2- T 4 U (t2) (t2) -Uu (tl}

Considering that at the beginning of the voltage pulse with amplitude U (tz), the voltage at the output of the integrator was equal to Uu (ti), by the end of the second time interval Г0, the voltage h at the output of integrator 4 and at the inverting input of adder 2 would be

l2 ll + l 2 UU (t2)

Converter 5 generates code N2 corresponding to voltage 12. which is fed to the information input of block 6.

Upon receipt of the third pulse from the multiplier b at time ts, an pulse of duration r0 and amplitude u (rz) is defined at the output of block 3, which is defined by the equality:

U (t3) Uu (((t2)

By the end of the time interval Г0 in the third cycle, the voltage 1c is set at the output of the integrator 4. defined by equality

1 / o

1zH2 + 1 / o U (t3) (t3),

and at the output of converter 5, code N3 is generated corresponding to voltage 1h.

The process is then repeated.

Thus, at the output of the integrator 4, the voltage (tiO.) Is set at the end of the K-ro conversion cycle (, M). And at the information input of block b, an NK code corresponding to the voltage IK is generated.

The voltage 1k is proportional to the instantaneous value P (1k) of the power

chain at time 1k .. s

M Hz

(tk) Ui (tk) SP (tk)

Since the M-cycle conversion of the input signals is performed during the 1 / FU period, the normalized value of the sum of the codes of the converter 5 will be proportional to the active power P of the controlled circuit:

m1 m

NP m 2, NK i T

W W SPK-SP

In this case, block 6 operates in averaging mode.

The converter can operate in the mode of moving averaging, when the reading of the Np code is carried out after expiration of n periods of the converted voltage. For this, in block b, the number Q of clock pulses of the multiplier 8 is counted and read at the times when CNM; 2M; ...; qM. If it is required to read the code of the measured active power by the end of each period, then it is enough to use the output pulses of the period 7 amplifier, which by the end of each period will reset the integrator 4 and give a pulse to the additional clock input of block b, fixing the end of the period.

The number of M clocks is selected taking into account the spectral properties of the signals Uu (t) and Ut (t), based on the minimization error of the numerical integration.

In determining the rational value of, one can use the criterion of minimizing the dynamic error

second kind; estimated by the Duhamel integral.

In the proposed device, in contrast to the prototype, the signal at the second input of the adder comes directly from the output of the integrator, without double voltage-code and voltage-code conversion, which eliminates the error in the prototype due to the specified

double conversion. This significantly increases the accuracy of the proposed Converter compared with the prototype, another advantage of the proposed converter compared to the prototype

there is greater simplicity and higher reliability due to the absence of a code-voltage converter in its composition.

Formula A from Breteni

An active power to code converter comprising series-connected first and second multipliers, the inputs of which are corresponding input buses, an adder, a sample-storage unit. integrator, voltage converter - code and a computing unit whose outputs are the output bus, a frequency multiplier whose input is combined with the first input of the multiplier, and the output

connected to the clocking inputs of the sample-storage unit, the voltage converter — code and the computing unit, and a period selector whose input is combined with the input of the frequency multiplier, and the output is connected to the reset input of the integrator and an additional clocking input of the computing unit, characterized in that that, in order to simplify the converter, the integrator output is connected to the second input of the adder.

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