KR970002782B1 - Terminal user information interfacer in the isdn - Google Patents

Abstract

A terminal user information interface device in the ISDN where execute the physical layer interface function of the N-ISDN S interface of the ISDN terminal interface device that execute the interface function in order to use the ISDN terminal device in the B-ISDN according to the request that supports the terminal and the present communication network interface, in the first step of providing the B-ISDN, and the ATM adaptive layer (AAL) type 1 function that is requested to the subscriber interface connection of the B-ISDN about the user information.

Description

Integrated Information Communication Network Terminal User Information Matching Device

1 is a schematic configuration diagram of a BISDN matching device (BTA) for an ISDN terminal to which the present invention is applied;

2 is a schematic configuration diagram of an ISDN terminal user information matching device according to the present invention;

3 is a block diagram of an R interface processing unit according to the present invention;

4 is a block diagram of a transmitter according to the present invention;

5 is a block diagram of a receiving apparatus according to the present invention;

6 is a configuration diagram of a receiving buffer control unit according to the present invention;

7 is a block diagram of a clock sensing circuit unit according to the present invention.

The present invention relates to a general information communication network terminal user information matching device, and more particularly, to a request for supporting an existing communication network interface and a terminal in an initial stage of providing a broadband integrated service digital network (hereinafter, referred to as a BISDN) service. According to the narrowband ISDN (hereinafter referred to as NISDN) physical layer matching function and user information of the ISDN terminal matching device which performs the matching function so that the ISDN terminal can be used in the BISDN. An ISDN terminal user information matching device that performs an Asynchronous Transfer Mode (ATM) Adaptation Layer (AAL) type1 function and a part of an ATM layer required for a BISDN subscriber interface (S _B ) connection. will be.

NISDN S A subscriber interface (S) for providing services through a Broadband Integrated Information Network (BISDN) to a narrowband basic speed subscriber by being connected to a reference point interface and processing basic access (2B + D) information. _B ) Matching function is required.

Accordingly, the present invention provides a broadband comprehensive information on the physical layer matching function and user information of the NISDN S reference point interface so that the NISDN terminal can be used in the BISDN. An object of the present invention is to provide an ISDN terminal user information matching device that performs a part of an ATM adaptation layer (AAL) required for accessing a subscriber interface of a communication network (BISDN).

In order to achieve the above object, the present invention is connected to a narrowband integrated telecommunications network subscriber interface processing means for outputting the clock recovery of the data received from the subscriber and the received data for each channel or perform the reverse function; Transmission buffering means for receiving serial data in units of bytes from the interface processing means for each channel, temporarily storing the data, converting the data into parallel data, and outputting the data; Multiplexing channel selecting means for counting the number of data input in units of bytes from said interface processing means and outputting a status signal; If any number of byte data transmitted from the subscriber is received by receiving the status signal of the multiplex channel selection means and stored in the transmission buffering means, a control signal for constructing a header of the cell is output, and the multiplex selection signal is output to output the multiplexing selection signal. Transmission control means for controlling the user data stored in the buffering means to be composed of one cell and transmitted to the asynchronous transfer mode (ATM) layer; Means for generating and inserting a segmentation and assembly protocol data unit (SAR-PDU) header under the control of the transmission control means; Means for storing a connection identifier input from an identifier controller via a system bus, and storing control and status values; Means for inputting a connection identifier stored in the storage means under the control of the transmission control means to form and insert an ATM header; An ATM interface control means connected to an ATM interface and outputting a transmission clock, a synchronization signal, and a frame signal under the control of the transmission control means; Under the control of the transmission control means, the ATM header, the SAR-PDU header, and the user data stored in the transmission buffering means are respectively inputted to form a cell, and multiplexed buffering to output in synchronization with the transmission clock of the ATM interface control means. Way ; Demultiplexed receiving buffer means for temporarily storing a cell received through the ATM interface; Header extracting and comparing means for extracting an ATM header from a cell stored in said demultiplexed receiving buffering means and comparing it with a connection identifier stored in said storing means; Header extracting and processing means for processing sequence number and sequence number protection by extracting a SAR-PDU header from a cell stored in the demultiplexed receiving buffering means; Receiving the synchronization signal received from the ATM interface control means to control the ATM header extraction and comparison means and SAR-PDU header extraction and processing means to receive the results of the demultiplexing process of the cell stored in the demultiplexing receiving buffering means Reception control means for controlling; Reception buffering means for temporarily storing only the demultiplexed user data for each channel; And means for controlling the read / write process of the buffering means under the control of the reception control means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a schematic configuration diagram of a BISDN matching adapter (BTA) for an ISDN terminal to which the present invention is applied.

The existing NISDN terminal is connected to the R interface processing unit 1 through the S interface of the ISDN User Network Interface (UNI), and the data matching unit 2 is an ATM adaptation layer (AAL). ) Converts the user information into an ATM cell and transmits the user information to the subscriber (S _B ) interface processor 3, which is an ATM / physical layer.

The subscriber (S _B ) interface processor 3 performs the functions of the ATM layer and the physical layer described in the CCITT recommendation, and transmits the ATM cell to the network through the subscriber (S _B ) interface.

On the contrary, the cell received from the network side passes through the subscriber interface processing unit 3, which is an ATM / physical layer, and the signal information and operation and maintenance (OAM) information are separated from the user information, and the identifier control unit corresponding to the processor ( 4) The user information is compared with the virtual path identifier (VPI) and the virtual channel identifier (VCI) and the data matching unit of the ISDN terminal user information matching device for the valid cell (2). Is delivered. The data matching unit 2 performs a data conversion process on the transmitted cell and transmits the data to the ISDN terminal through the B1 and B2 channels of the NISDN S interface. The data communication between the ISDN terminal user information matching device and the ATM / physical layer processing unit uses a dedicated line with separate transmission and reception, and is connected through a beck connector in the form of transmitting and receiving clock, synchronization signal, frame signal, and 8-bit data. The identifier controller 4 performs a signaling function, an OAM function, a protocol change function between the NISDN and the BISDN, and controls hardware operations of the lSDN terminal user information matching device and the ATM / physical layer processing unit 3.

The ISDN terminal user information matching device is connected to the system control unit 4 and the standard system bus (VME BUS), and the system control unit 4 and the ATM / physical layer processing unit 3 are local buses connected by dedicated lines. Connected.

2 is a schematic structural diagram of an ISDN terminal user information matching device according to the present invention, in which 21 is an R interface, 22 is an R interface processing unit reset circuit, 24 is an AAL processing unit, 25 is an ATM hair processing unit, and 26 is multiplexing / deactivation. Central, 27 is loopback circuit, 28 is transmit / receive buffer, 29 is ATM interface, 30 is address decoder, 31 is system bus (VME Bus) controller, 32 is local clock generator, 33 is club distribution circuit, 34 is A clock monitoring circuit, 35 represents an error signal generating circuit, 36 represents a control / status register, and 37 represents an identifier bus (VME Bus).

Some functions required by the BISDN to access narrowband subscriber information received through the NISDN S interface in accordance with CCITT Recommendation 1430 to the subscriber (S _B ) interface of the BISDN (the function of AAL-1 for user information and the ATM layer In order to perform some functions), first, the R interface processor 22 is connected to the R interface 21, performs the same function as the electrical standard of the S interface of the NISDN, and is configured to satisfy CCITT Recommendation I.430. . Also, it performs the functions such as transmission of ISB terminal and 2B + D channel, transmission of start / stop signal, maintenance, etc., and transfers 64Kbps B channel information and signal message received to R interface, and 16Kbps D channel. Has the function of separating information. Up to eight ISDN terminals can be connected to the S reference point interface, and two terminals can be connected at the same time.

The reset circuit 23 applies an initialization signal to the entire circuit of the present invention upon power-up or manual reset, and the manual reset can be applied by the method via the system bus (VME) and by its own reset switch from the system controller. . In addition, software reset for control of the present invention is performed using a hardware reset / status register 36. The software reset may apply each of the B1 and B2 channels independently and simultaneously.

The ATM adaptation layer (AAL) processing unit 24 receives a continuous 64Kbps bit stream from the sender and divides the information into 487 byte units to convert the ATM stream into an ATM cell, and the receiving side divides the receiving ATM cell into a continuous 64Kbps ATM. Performs the function of converting into bit stream and performs AAL type 1 function, Sequence Number (SN) and Sequence Number Pro-tector (SNP) processing, to process lost or incorrectly inserted cells. .

The ATM header processing unit 25 performs a function of generating and interpreting a VPI / VCI region of a corresponding ATM header for the B1 and B2 channels.

The VPI / VCI value is assigned to each call when a call is made from the processor's management layer processing module. The value is stored in a register and added with user information each time the cell is transmitted, and the receiving side receives the received VPI / Demultiplex function is performed so that user information is transmitted to corresponding B channel by analyzing VCI value.

The R interface processor 22 independently processes two 64 Kbps B channels of a NISDN, and only one B channel can transmit / receive the ATM layer. Therefore, the multiplexer / demultiplexer 26 Performs multiplexing of the cells for the B1 and B2 channels transmitted to the ATM layer, and performs the demultiplexing function for separating and connecting the received cells to the B1 and B2 channels. The loopback circuit 27 connected to the transmit / receive buffer 28 internally loops the data and control signals at the pre-transmission stage for error detection during hardware testing or communication failure with the ATM module.

In addition, the R interface processor 22 can also perform a B-channel loopback function test by using a device having a B-channel switching function.

The transmit / receive buffer 28 absorbs the jitter of the received cell and the received buffer, which is temporarily stored in the ATM adaptation layer (AAL), in order to transfer the B channel information received from the R interface to the ATM layer. It consists of a receiving buffer for delivery to the R interface unit.

The ATM interface 29 is connected to an ATM layer processing board of an ATM / physical layer processing module to perform a function of transmitting and receiving cells, and exchanges signals and data with the present invention through a local bus. When the cell is transmitted, the cell synchronization signal indicating the start of the cell, the frame signal indicating the cell transmission progress interval, and the data are transmitted in byte units. Therefore, the transmit byte clock necessary for writing and reading the buffer is simultaneously transmitted to the ATM layer processing board. Conversely, in case of reception, the same type of signal and data as the transmission are received from the ATM layer.

The selection signal of each device in the ISDN terminal user information matching device is generated by decoding the system bus address signal and the control signal received from the processor via the system bus (VME) in the address decoder 30.

The VME bus controller 31 is a functional block in which an ISDN terminal user information matching device is connected to a processor to operate as a slave board of a VM E bus. In particular, since the R interface processing device or the like uses a VME bus interrupter, it performs the function of generating and processing a VME bus interrupt.

The clock distribution circuit 33 receives the service clock of 19.44 MHz from the beck connector and distributes it to each device by using the division circuit, and when the service clock is not supplied, the local clock generator 32 for self-function test of the present invention. 19.6608MHz oscillation circuit is configured to selectively input into the division circuit.

The reception clock supervisory circuit 34 uses a watchdog timer to detect a data clock and a service clock received from an ATM module. When the timer expires (error of the reception clock), the LED is hardware-hardened. (LED: Light Emitted Diode) is turned on. The reception clock supervisory circuit 34 uses the mono stable multivibrator 74LS123, and the timeout time constant is 1 us.

The error signal generating circuit 34 informs the processor board using a system bus interrupter to quickly notify an error condition in the ISDN terminal user information matching device. The processor board identifies the error condition through the status register of the error and takes necessary action. To perform.

The control / status register 36 is a means for controlling the operating state of the hardware. The control / status register 36 controls or reports the communication with the processor and the state of the ATM Adaptation Layer (AAL), and is used as a buffer for storing the VPI / VCI during a call connection. It is connected via the VME bus and operated by the program of the processor.

3 is a block diagram of the R interface processing unit, using ISAC-S (PEB2085) 40, an S-transceiver, a commercial VLSI chip manufactured by Siemens, Germany, and EPlC (PEB2055) 41, a PCM (Pulse Code Modulation) interface. In order to provide a stable clock required for operation, a clock generation chip (MT8941) 42 having a phase locked loop (PLL) control function was used. The S-transceiver operates in LT-S, IOM2 mode, and is identical to the electrical specifications of the S reference point interface of the NlSDN and complies with CCITT Recommendation I.430. It performs functions such as transmission of R interface side and 2B + D channel, transmission of start / stop signal, and maintenance.B-channel information of 64Kbps received from R interface side is notified to the processor board by VME interrupter. The module checks the interrupter status register and reads the information on the chip.

An EPIC device is a PCM access controller connected to an ISAC device that provides B-channel switches and loops, synchronous loss monitoring, and signals for selecting B1 / B2 channel data.

The clock generation chip 42 receives the 8KHz clock synchronized from the network side and outputs 8KHz, 4MHz, 2MHz synchronized with the reference signal. EPIC uses 8KHz as a frame synchronization signal and receives 4MHz to obtain the desired data clock. Data passing through the R interface processing unit is output as a 64 Kbps bit stream, and is connected to the AAL processing unit to perform AAL type 1 processing.

4 is a detailed block diagram of a transmission-related functional block of an ISDN terminal user information matching device according to the present invention, and a process of transferring user information received from an NlSDN S interface to an ATM layer. Seems.

The transmission related function converts the B panel information received from the R interface 50 into an ATM cell having a constant speed of 64 Kbps and generates all control signals necessary for transmission as an ATM module.

First, when the sender receives a connection setup request from the processor through the control register 65, the 47-byte counters 51 and 52 store every byte in order to counter the user information stored in the 64 Kbps serial output by the R interface processor in units of bytes. Increases by 1 The 47 counters 51 and 52 operate in a 47-modular manner and operate independently of the B1 and B2 channels. When 47 counters 51 and 52 for the B1 / B2 channel receive 47 bytes, a carrier signal is output, and the signal is latched by a D flip-flop and input to the B1 / B2 multiplex channel selector 58.

The multiplex channel selector 58 determines the B channel to be configured as the current ATM cell and informs the transmission controller 64.

The transmission control unit 64 starts the cell configuration if there is B channel data that can configure an ATM cell, and the call connection setting of the corresponding channel is established. To configure the cell, the transmission control unit 64 divides the 19.44 MHz network synchronizer clock into three and operates a 53 counter that operates at a clock of about 2.5 MHz to use as a clock required for cell configuration.

First, in order to insert an ATM header, an ATM header enable signal is output to the ATM header inserter 62 so that 5 bytes of ATM headers can be written to the multiplex buffer 56 when the counter value of counter 53 is from 0 to 4. When the value is 5, the SAR-PDU header inserter 61 transmits an AAL header enable signal so that a segmentation and reassembly-protocol data unit (SAR-PDU) header can be used in the multiplex buffer 56. Will output

Upon receiving the ATM header enable signal, the ATM header inserter 62 reads the corresponding B channel VPI / VCI of the VPI / VCI register 66 of the selected B channel using the counter clock and outputs the result to the multiplexed buffer 56. .

The SAR-PDU header inserter 61 is also the same as the ATM header inserter 62. Here, the ATM header has meaning only VPI / VCI, and the rest are filled with arbitrary values. The counters 7 through 53 are filled with the multiplexed buffer 56 by payload of 47 bytes from the selected B channel transmit buffers 53 and 54 under the control of the buffer read / write clock generator 59. Thus, one complete cell is constructed.

If at least one cell is present in the multiplexing buffer 56, the ATM interface 57 operates a 53 counter operating at about 5 MHz in synchronization with the network clock, and transmits the 53 byte cell to the aforementioned transmission clock, transmission synchronization signal, and frame. Transmit using signals. One ATM cell consists of 5 bytes, an ATM header, a 1 byte SAR-PDU header, and 47 bytes of user information. The multiplexing channel selection method for the B1 / B2 channel is preferentially performed on the channel in which 47 bytes of user information is filled in the transmission buffer among the B1 and B2 channels. Due to the nature of EPIC devices, B1 and B2 data use different time slots, so B1 and B2 cannot be generated at the same time. If they occur at the same time, the B1 channel is processed first. The data rate output from the EPIC device is 64Kbps for each channel, and when multiplexing, the network service clock of 19.44MHz is divided and multiplexed to about 2.5MHz.

5 is a block diagram of a reception processing function unit of the ISDN terminal user information matching device according to the present invention, and it appears to be a process until the user information received from the ATM layer is transferred to the R interface processing unit.

When the cell arrives at the demultiplexing receiving buffer 71 from the ATM module, the receiving control unit 82 reads the receiving buffer with reference to the state information of the demultiplexing receiving buffer 7l and the receiving synchronous signal received from the ATM module.

First, the ATM header extractor 75 reads 5 bytes of ATM headers and detects VPI / VCI. The VPI / VCI comparator 78 compares the VPI / VCI for the B1 / B2 channel stored from the processor module at the time of call connection establishment. ) Outputs a B1 / B2 selection signal necessary for demultiplexing, and the reception control unit 82 determines the R interface side B channel reception buffers 72 and 73 to be stored using the selection signal.

If the B1 / B2 channel selection is successfully determined, the SAR-PDU header extractor 76 extracts one byte of the SAR-PDU header, outputs it to the SN / SNP processing unit 79, and the SN / SNP processing unit 79 The SAR-PDU header information is interpreted to confirm the serial number of the packet. When the reception control unit 82 obtains a valid result from the SN / SNP processing unit 79, the reception control unit 82 outputs a demultiplexing control signal to the demultiplexer 86 to display 47 bytes. Only the user information is stored in the B interface receiving buffer 72 or 73 on the R interface side.

The transmitting and receiving side of FIG. 4 and FIG. 5 are composed of three buffers, respectively, and the transmitting side has one serial-parallel (S / P) First In First Out (FIFO) 53 and 54 for the B1 and B2 channels, respectively. And a parallel-parallel (P / P) FIFO 56 for performing the multiplexing function. The receiving side stores B1 and B2 channel user information selected by the parallel-parallel (P / P) demultiplexing FIFO 71 for temporarily storing the information received from the ATM layer module performing the ATM function, and the demultiplexing function therefrom. Is composed of parallel-serial (P / S) FIFOs 72 and 73 that connect to each channel. The reason for the two-stage buffer structure is that the data transmission module facilitates processing in the data conversion module because the transmission speed of the R interface side and the ATM module connection are different, and the header processing and the multiplexing / demultiplexing function for the B1 / B2 channel are performed. For sake. The writing and reading of each buffer are controlled by the buffer read / write clock generators 59 and 77 by the set / reset of the status control registers 66 and 84 connectivity bits in the transmission and reception control sections 82 and 64. In addition, the serial-parallel (S / P) and parallel-serial (P / S) FIFOs can perform the serial / parallel conversion and serial conversion functions themselves to reduce the additional circuits required for the conversion. In FIG. 4 and FIG. 5, the ATM header inserter 62 and the VPI / VCI comparator 75 store the VPI / VCI value allocated to each call in a register by a deallocation command when a call is connected from the management layer. The value is used, and the transmitting side reads and inserts the cell every time the cell is transmitted, and the receiving side compares the received VPI / VCI value with the value stored in the register and transmits the user information to the corresponding B channel.

As the SN / SNP processing function, the transmitting side is in charge of the SAR-PDU header generating unit 60 and the receiving side is in charge of the SAR-PDU extracting unit 76 and the SN / SNP processing unit 79. The SAR-PDU header generation unit 60 on the transmitting side generates a 3-bit sequence number for 47 octets of user information, and uses the receiving side to process lost and misinserted cells. In addition, by using a cyclic code for 3-bit information, the sequence number protection (SNP) using a polynomial of G (x) = x ³ + x ¹ +1 is added to the sequence number (SN) value. It will prevent errors.

The SAR-PDU header generator 60 is composed of a sequence number (SN) generator, a 3-bit sequence number protection (SNP) generator, and an even parity generator for the higher 7 bits. The output of the SAR-PDU header outputs the generated SAR-PDU header when the output control signal is enabled for the configuration of the cell from the transmission control unit 64. When the output is completed, the sequence number (SN) counter value is increased by 1 and the SAR-PDU header for the next transmitting cell is calculated and latched in the output register.

The receiver checks the CRC bit (SN) and the even parity bit of the extracted SAR-PDU header to perform 1-bit error correction or error detection for 2 or more bits, and operates in the correction mode or the detection mode. Then, the received procedure number (SN) value is examined to process lost or incorrectly inserted cells. The configuration of the receiver comprises a header register, a correction mode processor, a detection mode processor, and a sequence number (SN) checker.

6 shows a configuration diagram of the reception buffer control unit 80 according to the present invention. The sender stores the user information received from the B1 and B2 channels of the R interface in a serial-parallel (S / P) FIFO at a byte rate of 8KHz as a bit stream of 64bps. It performs and transmits the AAL function and some ATM layer functions. Therefore, the control of the sending buffer is generally simple.

However, in the case of the receiving side, the cell sent from the transmitting side arrives at the receiving buffer of the ATM adaptation layer (AAL) through the network, and includes the jitter of the network due to the difference in the service clock between the transmitting and receiving and the ATM processing function of the network. Therefore, even if the transmitting side continuously transmits cells at a constant speed, the arrival time of these cells may be random.

Therefore, the receiving buffer should be able to maintain a certain buffer level and will not start service until the reference level is reached.

In addition, the buffer has an upper and a lower limit level, and the buffer overflow and underflow conditions must be continuously monitored. To do this, registers are used to send and receive these state processing information from the processor. For reception, use up-down counter 92 with 8 bits each for B1 / B2 channels, and up-down counter 92 sends 8 bits (1 byte) of parallel / serial (P / S) FIFO for output to R interface. When reading, the counter is decremented by 1, and demultiplexed from the ATM module by 1 when the byte is written. The counter value is passed to the buffer level comparator 93 so that the comparator 93 receives the upper limit level of the system bus. It outputs necessary status information such as service start signal by comparing with service start level value. When an underflow of the buffer occurs, a pseudo byte is output.

7 shows the configuration of the clock monitoring circuit 34 according to the present invention. The clock monitoring circuit 34 is implemented by the multivibrator 100 and the retrigger time is adjusted by the resistor 101 and the capacitor 102. .

The present invention configured and operated as described above is connected to a NISDN S reference point interface and processes BAS information for ISDN narrowband BSSDN by processing basic access (2B + D) information. It performs hardware interface of BISDN R interface access function and 64Kbps B channel information of AAL type 1 to create subscriber interface matching function to provide service through AAL type 1, and to generate and interpret ATM header VPI / VCI. It can be used to develop an access function for NISDN primary group speed information.

Claims (5)

Interface processing means for being connected to a narrowband Telecommunications network subscriber and outputting the clock recovery of the data received from the subscriber and outputting the received data separately for each channel or performing the reverse function; Transmission buffering means for receiving serial data in units of bytes from the interface processing means for each channel, temporarily storing the data, converting the data into parallel data, and outputting the data; Multiplexing channel selecting means for counting the number of data input from the interface processing means in units of bytes and outputting a status signal; If any number of byte data transmitted from the subscriber is received by receiving the status signal of the multiplex channel selection means and stored in the transmission buffering means, a control signal for constructing a header of the cell is output, and the multiplex selection signal is output to output the multiplexing selection signal. Transmission control means for controlling the user data stored in the buffering means to be composed of one cell and transmitted to the asynchronous transfer mode (ATM) layer; A means for generating and inserting a segmentation and assembly protocol data unit (SAR-PDU) header under the control of the transmission control means; Means for storing a connection identifier input from a system controller via a system bus, and storing control and status values; Means for inputting a connection identifier stored in the storage means under the control of the transmission control means to form and insert an ATM header; An ATM interface control means connected to an ATM interface and outputting a transmission clock, a synchronization signal, and a frame signal under the control of the transmission control means; Multiplexed buffering under the control of the transmission control means to receive the ATM header, the SAR-PDU header, and the user data stored in the transmission buffering means, respectively, to form a cell and to synchronize the transmission clock of the ATM interface control means. Way ; Demultiplexed receiving buffer means for temporarily storing a cell received through the ATM interface; Extracting and comparing means for extracting an ATM header from a cell stored in said demultiplexed receiving buffering means and comparing it with a connection identifier stored in said storing means; Header extracting and processing means for processing sequence number and sequence number protection by extracting a SAR-PDU header from a cell stored in the demultiplexed receiving buffering means; Receiving the synchronization signal received from the ATM interface control means to control the ATM header extraction and comparison means and SAR-PDU header extraction and processing means to receive the results of the demultiplexing process of the cell stored in the demultiplexing receiving buffering means Reception control means for controlling; Reception buffering means for temporarily storing only the demultiplexed user data for each channel; And a reception buffer control means for controlling a read / write process of the buffering means under the control of the reception control means. The integrated telecommunications terminal as claimed in claim 1, further comprising means for receiving a service clock from the outside and dividing it to generate a clock required for each function processing means and for monitoring a clock received from the ATM interface. User Information Matching Device. 3. The integrated information and communication network according to claim 2, further comprising means for looping transmission data and control signals connected to the transmission buffering means to detect an error in hardware testing or communication failure with an ATM module. Terminal user information matching device. The apparatus according to claim 1 or 2, wherein the interface processing means is connected to the system bus, and connected to a subscriber interface for synchronizing electrical matching and data received from the subscriber to a frame sync clock and outputting the reverse function. Interface means; Clock generation means for receiving a network synchronization clock and a system clock from the outside to generate a frame synchronization signal and a data clock; And receiving the frame synchronization signal and the data clock from the clock generating means, outputting the frame synchronization clock to the interface means, receiving the transmission data, performing switching and loop functions of the channel data, and monitoring the loss of synchronization. And a means for dividing the output into channels or performing a reverse function thereof. The receiving buffer control means according to claim 1 or 2, further comprising: means for storing a buffer upper limit value for preventing overflow of the reception buffering means and a value for notifying the start of a service connected to the system bus; Means for receiving a read clock and a write clock and counting the amount of data stored in the reception buffering means; Comparison means for comparing the value stored in the storage means with the count value of the counting means and outputting the result; And a control signal generating means for receiving a comparison result of the comparing means and outputting a control signal for notifying the start of a service to the buffering means.