KR960014692B1 - Asynchronous transfer mode cell router - Google Patents

Abstract

The ATM(Asynchronous Transfer Mode) cell router includes: an input cell interface section 1 for receiving the input cell flow transferred and synchronized by a byte clock, transmitting data into an extracting circuit 3, and transferring a write control signal and data into a cell buffer 2; a header extracting and header processing section 3 for receiving a header extracting signal 16 from a timing generating circuit section 4, and inputting the extracting header into a header comparing section; a connection table and a header comparing section 6 for comparing the header information 18 received from the header extracting and header processing section 3 with a connection identifier, and sending a connection matching information 21 into a routing control section 7; a routing control section 7 for decoding the connection matching information 21 received from the connection table and header comparing section 6, reading cells from a cell buffer 2 by sending a read control signal 14 after deciding a destination; a cell routing processing section 8 for routing cells by using the routing control information 15 received from the routing control section 7; a timing generating circuit section 4 for receiving a cell clock 27 and a byte clock 28 from the input interface section 1, and generating a timing information 17 and a head extracting control signal 16; a connection setup and release control section 5; and a state/control register section 9 and a process interface section 10.

Description

Asynchronous Forward Mode (ATM) Cell Router

1 is a diagram illustrating an input / output relationship of an asynchronous delivery mode cell router.

2 is an asynchronous delivery mode cell router.

3 is a connection signal and timing diagram of an asynchronous delivery mode cell router.

4 is a bit format of a control resist.

5 is a bit format of a state resist.

Asynchronous Transfer Mode (hereinafter referred to as ATM), which is a component of the Broadband International Services Digtal Network (hereinafter referred to as B-ISDN) of the present invention, is common to a network node, a network termination device, and a terminal access device. The present invention relates to an asynchronous delivery mode (ATM) cell router that can be used.

B-ISDN, a service convergence network created as a backbone network of new information and communication, emerged to overcome the limitations of transmission speed, bandwidth, and various users' demands. B-ISDN provides a high speed communication link as an optical transmission device and a high speed ATM switching system to speed up the network bandwidth and processing speed to enable large-scale real-time service to meet these demands. And increased flexibility. Cell routers that provide UNI and NNI interfaces with a transmission rate of 155.52 Mbit / s, which is one of the core technologies, are essential to construct the B-ISDN high-speed network.

Accordingly, the present invention, which is devised to meet these essential requirements, maintains the association established by the ATM layer between two or more ATM service users to improve end-to-end delivery capability. It is an object of the present invention to provide an asynchronous delivery mode (ATM) cell router for analyzing a header of a cell received from a physical layer to deliver a cell to a corresponding higher layer.

In order to achieve the above object, the present invention provides an ATM cell router, which receives an input cell flow transmitted in synchronization with a byte clock, sends data to a header extraction circuit, and transmits a write control signal and data to a cell buffer. ; A header extracting and header processing unit for receiving a header extracting signal from a timing generating circuit unit and inputting an extracting header to a header comparing unit; A connection table and header comparison unit for comparing connection header information received from the header extraction and header processing unit with the connection identifier to transmit connection matching information to the routing controller; A lighting control unit which decodes the connection matching information received from the connection table and the header comparison unit, determines a destination, sends a read control signal to read a cell from a cell buffer, and simultaneously sends routing control information to a cell routing processor; A cell routing processor for routing a cell using routing control information received from the routing controller; A timing generation circuit unit which receives the cell clock and the byte clock from the input cell interface unit and generates timing information and a hair extraction control signal; A connection establishment and release controller configured to receive connection establishment information and disconnection information of the state control resist unit received through the processor interface and control connection establishment and release in the association table; And a status / control register section and a process interface section for informing the dynamic control and status of the cell router from the process.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 1 is a diagram illustrating the input / output relationship of an asynchronous delivery mode cell router. As shown in the drawing, an ATM cell router basically receives a valid cell A received from a physical layer, analyzes a header, and then analyzes the header. It performs the function of writing according to.

In addition, it provides an interface with the process control unit to give the router as control information when establishing and releasing a new connection.The detailed functions include buffering of cells received at the physical layer, header extraction and header comparison of cells received at the physical layer According to the VPI / VCI analysis result, cell writing function is performed to the corresponding connection point. In this example, VPI / VCI tables are distributed by service pointers in the ATM layer to avoid conflicts in table management, and OAM (Operaion and Maintenance) processing and table management are easily used for bidirectional VPE / VCI allocation. In addition, extraction of unassigned cells, extraction and disposal of idle cells, extraction of misinserted cells, disposal and counting, management of VPI / VCI connection tables, OAM of F4 and F5 flows (Maintenance, management, maintenance) functions, and cell relay functions.

By measuring the resource usage on the link of the currently received physical layer, the headers are compared to extract unallocated cells / rest cells, and the number is counted at the same time. These values provide an interface for access from the Common ATMcell Router or other module controllers connected to the router. In addition, a function of extracting and discarding a cell that is a valid cell due to an unknown header error or a switching error that does not exist in a look-up table that has been mistransmitted from another connection exists. have. Here too, it counts every occurrence and informs the router controller to use it as data information for network management.

Next, FIG. 2 is a block diagram of an ATM cell router. After receiving and retiming the input cell flow A1 transmitted in synchronization with the byte clock A3, the data is sent to the header extraction circuit 3 and the cell is transmitted. Timing generation circuit unit for extracting header from cell flow received from input cell interface unit 1, which transfers write control signal and data to cell buffer 2 for temporary cell storage during processing time, and input cell interface unit 1 Header information received from the header extraction and header processing unit 3 and the header extraction and header processing unit 3 which extracts the header using the header extraction signal 16 received from (4) and inputs it to the header comparison unit 6. A connection table and header comparison unit (6), a connection table and header comparison unit (6), which transmits connection matching information (21) indicating a destination to be routed to the routing control board (7) by comparing with the connection identifiers in the connection table using the " From) Decodes the connection matching information 21 to determine the destination, and then sends a read control signal 14 to read the cell from the cell buffer 2 and simultaneously sends the routing control information 15 to the cell routing processor 8. The cell clock 27 and the byte clock (from the input cell interface unit 1) and the cell routing processor 8 for writing a cell using the routing control information 15 received from the control unit 7, the routing control board 7. 28, the timing generating circuit section 4 which receives the timing information 17 and the header extraction control signal 16, and the connection setting information 23 of the state control resisting section 9 received through the processor interface, and disconnection information. (6) a connection establishment and release control unit (5) which receives (22) and controls connection establishment and release, and a state / control registrar unit (9) for informing the control and state of the operation of the cell router from the process; Based on the process interface unit 10 It consists of a.

The connection establishment / release control unit 5 connects the ATM link, the ATM connection end point, and the physical layer connection end point to each other according to the connection establishment request received from the ATM layer management entity in the processor in order to establish an appropriate association determined by the call establishment signal procedure. It performs the function and releases the connection according to the ATM disconnection request from the LME when the ATM connection established for the higher layer service is no longer needed. In order to support the F4 and F5 flows required to transmit the OAM cell, the connection table manages not only out-band communication of OAM information but also ATM connection establishment and release for in-band communication. It is implemented in relation to the management method. The connection table and header comparison unit 6 includes a connection table buffer and an idle cell processing unit for maintaining tables for ATM-CEL, ATM-LIs (VPI / VCIs), PHY-CEL, and connection prarmeter, which are information on ATM connection. It maintains and compares pre-assigned VPI / VCI. The header comparison is then performed on the valid cell flow received from the physical layer.

It is necessary to separate the parts using devices (FIFO, CAMetc) already made to implement the above-described cell routers and the parts to be integrated by implementing logic in the FPGA and subdivided into detailed functional blocks. Looking at it as follows. The input cell interface unit 1 is a cell synchronization clock A2 and a byte clock A3 from the physical layer, and cell data A1 truncated in units of bytes transmitted in synchronization with the cell, and an effective cell indicating that the cell is a valid cell. A line drive that accepts the A4 signal is implemented. Here, it is implemented with logic for generating WCLK and WEN (write enable), which are write control signals 12 for temporarily storing the received cell in the cell buffer 2. Cell FIFO 2 performs the function of temporarily storing a cell during header comparison and uses a colocked FIFO. The header extracting circuit and the processor extracts only the header portion in parallel from the cell flow transferred from the physical layer by byte using four shift resists 74F273, and inputs the header portion into the header comparison unit 6. Cell processing is performed on the fields such as GFC (Generic Flow Control), PTI, CLP, etc. from the extracted header. The timing generation circuit unit 4 uses timings such as the timing information 17 and the header extraction signal 16 for controlling the cell router using the cell synchronization clock (Cel-sync: A2) and the byte clock (A3) received from the physical layer. Generate a control signal. Therefore, all operations of the cell routers are synchronized with the cell flow transmitted from the physical layer. The connection establishment and release control unit sends VPI / VCI for connection establishment through the process interface from the router control unit in the process and enters it into the connection table CAM (Content Addressable Memory) at the time that is not overlapped with the moment when the header is compared. Do this.

It is the control resistive input signal implemented by the 74F374, the resists for CAM access, and the logic that controls them. The idle cell processing unit and the preassigned VPI / VCI comparator present in the connection table and header comparison unit compare the idle cell with the pre-assigned VPI / VCI by looking at the extracted header and discard the idle cell. MICH signal is generated to route to each interface accordingly. When the idle cell occurs, the count indicates the event occurrence. This is implemented in logic. The connection table and header comparison unit stores VPI / VCI, which is a header for each connection, compares the headers with respect to the extracted header input, and generates connection matching information (MTCH) that is a signal for routing to each interface. They are implemented using one CAMI (DT99C10A) for each of the loop-back interfaces for signaling, ATM, service data, and cell relay, and can be used for subscriber terminals, terminal matching devices, or network termination devices.

The routing controller controls the operation of the overall cell router, and reads the cell temporarily stored in the cell buffer based on the result of the comparison in the header comparison unit and the result of determining whether it is the idle cell or the preassigned cell. Generates a signal and a signal defined by each interface. This is implemented in logic in the ALS1240FPGA. And it may include a counter consisting of 74f161 counting the number to inform the occurrence frequency per measurement time when the idle cell and Misrouting cell occurs. The control resist and state register unit 9 is composed of a 16-bit control resist for controlling the function of the cell router in the processor and a 16-bit state register for informing the state of the CDAB, and includes the number of idle cells and the number of misrouting cells. It consists of resists.

Meanwhile, as shown in FIG. 3, in order to be connected to a cell router, the following connection signal and timing relationship must be satisfied. The purpose of each signal is as follows.

At this time, the cell data bus is the Byte Data contained in the payload region in the SMT-1 (Synohronous Transport Module) frame, and the cell sync clock is active only for the first byte as a signal for indicating the first byte of every cell. The cell enable signal indicates the validity of the cell and is active high. The cell error is a triggering signal that informs the cell router of a cell error (synchronization error). It is defined as a signal with a certain time delay.

Subsequently, the byte clock refers to a gap clock that exists only at 260 octets in which a cell is transmitted among the 19.44 MHz clocks provided by the 155.520 MHz clock reproduced at the physical layer and is low at 10 octets. The interrelationship between the two signals can be seen in the signal timing diagram of FIG.

The output signal of the cell router has the following timing relationship. These all have the same relationship from B1 to Bn in FIG. 1, and the division of n outputs consists of Bn-CEN which is an output cell enable.

At this time, the output cell data is 53 bytes of service data, and the cell sync clock is a signal indicating the first byte of cell data provided from the cell router. The cell enable and Bn-CEN input a cell input to the reception FIFO at each connection point. A signal that indicates the period of cell transfer for write-in. Active-low, byteclock means a gap 19.44MHz clock that occurs only at the moment cell data is transmitted.

The timing diagram of the output signal of the cell route is shown in FIG. 6B.

FIG. 4 shows the bit format of the control resist and FIG. 5 shows the bit format of the state resist.

The present invention as described above is a broadband integrated telecommunications network as an "ATM cell router" for routing the cell flow from the UNI or NNI to the transmission line of multiple subscribers, which have been transmitted by multiplexing various types of service connections into one flow. It can be commonly used for network node, network termination device, terminal access device, etc. In particular, the present invention, in the case of a terminal adapter (B-TA), one subscriber should have a general structure for receiving a plurality of services, and for this purpose, it may be used as a routing function element, and in the case of a network termination device (B-NT2), It is a structure that can be used in common so that it can be used even when it is necessary to provide the service without distorting the characteristics of the service on the transmission line of several subscribers in the traffic distributed in the network. It can also be used for distribution function of output stage in switch structure. Therefore, the present invention is expected to be a core component of the broadband network to be used since the present invention can be commonly used in the above-described advantages and components of the broadband integrated information communication network.

Claims (3)

Asynchronous Transfer Mode (ATM), a component of the Broadband International Services Digital Network (B-ISDN) Asynchronous Transfer Mode (ATM), which can be commonly used for network nodes, network termination equipment and terminal access equipment. In the cell router, an input cell interface unit (1) for receiving an input cell flow transmitted in synchronization with a byte clock, sending data to a header extracting circuit (3), and transmitting a write control signal and data to a cell buffer (2) ; A header extraction and header processing unit 3 for receiving the header extraction signal 16 from the timing generation circuit unit 4 and inputting the extraction header to the header comparison unit 6; A connection table and header comparison unit 6 which transmits connection matching information 21 to the routing control unit 7 by comparing the header information 18 received from the header extraction and header processing unit 3 with the connection identifier; After deciding the destination by decoding the connection matching information 21 received from the connection table and the header comparing unit 6, the read control signal 14 is sent to read the cell from the cell buffer 2 and the routing control information ( A routing controller 7 which sends 15 to the cell routing processor 8; A cell routing processor (8) for routing the cell using the routing control information (15) received from the routing controller (7); A timing generation circuit section (4) which receives the cell clock (27) and the byte clock (28) from the input cell interface section (1) and generates timing information (17) and a head extraction control signal (16); A connection establishment and release controller 5 which receives connection establishment information 23 and disconnection information 22 of the state control resist unit 9 received through the processor interface and controls connection establishment and release in the association table 6; And a state / control register section (9) and a process interface section (10) for informing the dynamic control and status of the cell router from the process. The asynchronous transfer mode (ATM) cell router of claim 1, further comprising a connection table and a header comparing unit, which include a dormant cell processor and a pre-assigned VPI / VCI comparator for managing a pre-allocated connection identifier. 2. The apparatus of claim 1, further comprising a timing generation circuit for generating a system-wide control timing from an input cell byte clock and a cell synchronization clock, and separating the header comparison and the connection control time of the input cell flow. Asynchronous delivery mode (ATM) cell routers.