KR100372519B1 - compound ATM subscriber access appratus - Google Patents

Abstract

An object of the present invention is to provide a complex ATM subscriber matching device that can simultaneously process by providing network matching between low-speed FR / CE / ATM subscriber heterogeneous devices in one board.

The composite ATM subscriber matching device of the present invention provides a network matching and a line matching unit for matching electrical characteristics; A signal exchange unit for switching a corresponding service subscriber to a corresponding protocol processing unit and for connecting and connecting data received from a network to the corresponding service subscriber; A frame relay processor for matching the frame relay protocol and the ATM protocol by converting the frame relay data and the ATM cell data; A circuit emulation processing unit for matching circuits with a public circuit network to emulate circuit data of a subscriber frame, converting the circuit data into an ATM cell, and providing communication with a higher processor; An ATM processor that matches with a low-speed ATM subscriber and provides an access service to an upper ATM network; A cell bus interface unit for providing protocol matching between a memory unit and an upper processor included in each processing unit; An IPC processor providing a signal transmission / reception medium with an upper processor; And a control unit which controls the entire system and performs initialization of various devices, execution of a driver program function, and a signal processing program function.

Description

Compound ATM subscriber access appratus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subscriber matching device in an asynchronous transfer mode (hereinafter, referred to as ATM), and more particularly, a circuit provided in a service or a public network through a frame relay (hereinafter referred to as FR). Emulation (Circuit Emulation, hereinafter referred to as CE) This is about network matching of heterogeneous devices that provide low-speed ATM network service in data service or ATM network, and provides network matching between heterogeneous devices to provide ATM service simultaneously. A multiple ATM subscriber matching device.

In general, exchanges are equipped with matching devices that match networks between heterogeneous devices that provide low speed (2 Mbps) ATM services over CE services or ATM networks over FR or public networks. 1 shows the structure of the FR board. As shown in FIG. 1, since there are three blocks that independently perform data processing on the FR board, the data of the frame relay from the T1 / E1 line is processed and stored in the packet memory unit 1 or the packet. High-level data link control (HDLC) processing unit 3 for converting the data of the memory unit 1 into a frame relay frame and transferring the data to the track, and the high-level processor by segmenting the data of the packet memory unit 1 into ATM cells. A protocol between the segmentation and reassembly (SAR) processor 5, the HDLC processor 3, and the SAR processor 5, which reassembles and transfers an ATM cell received from an upper processor to the packet memory unit 1 This is the processor unit 7 which performs the conversion function and the board-wide control function. Here, the bus arbiter 9 may implement and execute arbitration logic for controlling a bus of each module.

2 is a diagram illustrating a configuration of a CE board. As shown in FIG. 2, the SAR and channel unit 11 of the CE board is composed of a SAR processing unit 11a performing an AAL (ATM Adaptation Layer) 1 function and an E1 × C in the downlink cell bus processing unit 13. The SAR processor 11a divides the data of the transmitted internal cell into data and information for each channel to send data and information of the corresponding channel to each corresponding channel, and each channel transmits data and information to channel subscribers. . In addition, the SAR processing unit 11a converts the data and information received from the channel subscribers into an ATM internal cell and transmits the data and information to the uplink cell bus processing unit 15.

Here, the SAR data is shared with the processor through the buffer 16 and the static random access memory (SRAM) 17, and communicates with the upper processor using the dual port random access memory (DPRAM) 19.

The SRTS processing unit 14 performs a function of restoring a clock.

3 is a diagram illustrating a configuration of an ATM board. As shown in FIG. 3, signals from 8 subscribers are extracted into ATM cells through E1 × C and physical layer processor 21, respectively, multiplexed, enter EPLD (eraserble program logic degign) 23, converted to 16 bits, and then LLI. It is transmitted through the cell bus to the low-rate link interface. On the other hand, the cell received from the LLI unit via the cell bus is VPI / VCI (Virtual Path Indicator / Virtual channel Indicator) by the point to multipoint conversion table through the EPLD 23; After the channel identifiers are converted, they are transmitted to the subscriber in the E1 frame after passing through the E1 × C and the physical layer processing unit 21.

As described above, each conventionally configured as described above to perform matching between heterogeneous devices providing a low speed (2 Mbps) ATM network service in an ATM or a CE data service provided in a public network or a public network. The subscriber matching board had to be provided in the subscriber matching device.

Therefore, in the related art, in order to provide three types of services, all of the circuit packs providing the respective functions must be provided.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides a multiple ATM subscriber matching device capable of simultaneously processing by providing network matching between low-speed FR / CE / ATM subscriber heterogeneous devices on one board. There is this.

Composite ATM subscriber matching apparatus of the present invention for achieving the above object is a line matching unit for providing a network and matching and matching electrical characteristics; A signal exchange unit for switching a corresponding service subscriber to a corresponding protocol processing unit and for connecting and connecting data received from a network to the corresponding service subscriber; A frame relay processor for matching the frame relay protocol and the ATM protocol by converting the frame relay data and the ATM cell data; A circuit emulation processing unit for matching circuits with a public circuit network to emulate circuit data of a subscriber frame, converting the circuit data into an ATM cell, and providing communication with a higher processor; An ATM processor that matches with a low-speed ATM subscriber and provides an access service to an upper ATM network; A cell bus interface unit for providing protocol matching between a memory unit and an upper processor included in each processing unit; An IPC processor providing a signal transmission / reception medium with an upper processor; And a control unit which controls the entire system and performs initialization of various devices, execution of a driver program function, and a signal processing program function. Further, the frame relay processing unit may include a protocol processing unit which performs frame relay data processing; A packet memory unit for storing ATM cells; A bus arbiter section for controlling bus occupancy rights between bus masters of respective devices; A buffer unit for providing communication between the packet memory unit and a protocol processing unit under control of the bus arbiter unit; A division and resynthesis processing unit for dividing the frame relay data received from the protocol processing unit into ATM cells or resynthesizing the ATM cells received by the processor; A memory unit for monitoring cell signals transmitted and received with an upper processor to distinguish between cell boundaries and whether a cell is to be received; And a header converter configured to receive an ATM cell, perform routing tagging, and transmit it to the memory unit, or delete tagging information of the ATM cell received from the memory unit, wherein the circuit emulation processor is configured to channel the contents of the cell received from the upper processor. A division and resynthesis processing unit for dividing each channel and transmitting corresponding data and information for each channel, and converting channel data and information received from a line into a cell bus; A synchronous residual time stamp processing unit performing a function of restoring a clock; A memory unit for monitoring cell signals transmitted and received with an upper processor to distinguish between cell boundaries and whether a cell is to be received; And an up / down cell processing unit for performing ATM cell transmission / reception processing and header conversion functions between the memory unit and the partition and resynthesis processing unit, wherein the ATM processing unit formats and transmits an ATM cell type received from the line matching unit. Cell extraction / insertion; A transmission processor configured to header convert a cell received by the cell insertion / extraction unit; A memory unit configured to transmit cell data and a cell start signal to an upper processor through the cell bus interface unit when receiving a read enable signal from an upper processor; And a reception processor for converting VPI / VCI to the cell extraction / insertion unit when the cell received by the memory unit is a multicasting cell.

1 is a view showing the configuration of the FR board.

Figure 2 is a view showing the configuration of the CE board.

3 is a diagram showing the configuration of an ATM board.

4 is a diagram showing the configuration of a composite ATM subscriber matching device of the present invention.

*** Explanation of symbols for the main parts of the drawing ***

100.Rail matching unit, 200. Signal exchange,

210. Upper Module 220. Lower Module,

300. FR (Frame Relay) processing unit, 310. Protocol processing unit,

320. Buffer section 330. Packet memory,

340. Bus Arbiter Department,

350, 410. Segmentation and Reassembly Processing Unit,

360. header conversion unit,

370, 450, 540.frist-in first-out,

400. CE (Circuit Emulation) processing unit,

420. Synchronous Residual Time Stamp (SRTS) processing unit,

430. The uplink cell processor 440. Down-cell processing unit,

500. ATM (Asychronous Transfer Mode) processing unit,

510. Cell extraction / insertion, 520. Transmission processor,

530. Receive processing unit 600. Cell bus interface unit,

700. IPC (Interconnection Process Communication) processing unit,

800, 801. Control unit

Hereinafter, with reference to the accompanying drawings it will be described in detail with respect to the combined ATM subscriber registration device according to a preferred embodiment of the present invention.

4 is a diagram showing the configuration of a composite ATM subscriber matching device of the present invention. As shown in FIG. 4, the complex ATM subscriber matching apparatus of the present invention includes a line interface 100, a signal exchange unit 200, an FR processor 300, a CE processor 400, and an ATM processor 500. ), A cell bus interface unit 600, an IPC processor 700, and a controller 800.

In the above-described configuration, the line matching unit 100 provides a matching with the network and performs a function to match the electrical characteristics.

The signal exchange unit 200 switches the service subscriber to the corresponding protocol processing unit and converts the data received from the network to the corresponding subscriber type in order to convert the FR / CE / ATM matching protocol into the ATM in the network. do.

The FR processor 300 performs a function of matching the frame relay protocol and the ATM protocol by converting the frame relay data and the ATM cell data, and includes a protocol processor 310, a buffer 320, and a packet memory 330. And a bus arbiter 340, a SAR processing unit 350, a header converting unit 360, and a FIFO (frist-in first-out) 370. Here, the protocol processor 310 performs frame relay data processing, and the buffer unit 320 provides SAR data communication between the packet memory unit 330 and the protocol processor 310 under the control of the bus arbiter unit 340. The packet memory unit 330 stores an ATM cell, the bus arbiter 340 controls bus occupancy rights between bus masters of respective devices, the SAR processor 350 performs an AAL5 function of an ATM, and a header converter. 360 receives the ATM cell and performs routing tagging to transmit to the FIFO 370 or to delete tagging information of the ATM cell received from the FIFO 370, and the FIFO 370 is a higher level. It monitors cell signals transmitted and received by the processor and performs a function of distinguishing cell boundaries and distinguishing whether or not the cell should be received.

The CE processor 400 matches the public communication network and provides communication with a higher processor that converts a protocol of line data into an ATM cell through a circuit emulation (CE), and includes a SAR processor 410, an SRTS processor 420, and an upcell processor ( 430, the downlink cell processor 440, and the FIFO 450. Here, the SAR processor 410 divides the contents of the 53-byte cell transmitted in synchronization with the clock by the downlink cell processor 440 for each channel, provides corresponding data and information for each channel, and removes the AAL1 function in the E1 frame for each channel. To perform line matching, add AAL1 function to data received from the line, convert channel data and information into cell bus (53 bytes), and transmit to the uplink cell processor 430 according to clock synchronization. The SRTS processing unit 420 transmits data by linking a clock toward the CE processing unit channel to synchronize the frequency of another channel or terminal interworking with each channel in the CE processing unit 400, and receives the data at the receiving side if the frequency cannot be synchronized. The TS (time stamp) value and the counter value are compared, and when they are equal, the clock of the transmitting side is restored through PLL (phase loop lock) to synchronize. The up / down cell processing units 430 and 440 perform ATM cell transmission and reception and header conversion functions between the FIFO 450 and the SAR processing unit 410, and the control unit 801 converts the internal cell data converted by the SAR processing unit 410. Are stored in memory through each data buffer to communicate with the upper processor. Here, the SRTS processor 420 uses the frequencies provided by each channel or the terminal, adjusts the remaining time of the frequencies, extracts the original clock, and restores the frequency.

The ATM processing unit 500 extracts and processes a 53-byte ATM cell using HEC (header error detection and control) of an E1 frame received from a low-speed subscriber, sends it to a higher processor, and sends an ATM cell (56 bytes) received from a higher processor. The VPI / VCI conversion is performed by the point-to-multipoint conversion table, and then transmitted. The cell extraction / insertion unit 510, the transmission processing unit 520, the reception processing unit 530, and the FIFO 540 are provided. It features. Here, the cell extracting / inserting unit 510 divides the ATM cell loaded in the E1 frame by using a HEC to delineate the cell and transmits the cell in the E1 frame, and the transmission processing unit 520 transmits the cell inserting / extracting unit. Header conversion (VPI / VCI) of the cell received at 510 is transmitted to the FIFO 540, and the reception processor 530 converts the VPI / VCI if the cell received at the FIFO 540 is a multicasting cell. The table is read and converted to VPI / VCI and sent to the cell extraction / insertion unit 510. If it is a point-to-point cell, it is sent without any conversion.

The cell bus interface unit 600 provides protocol matching between the FIFOs 370, 450, and 540 of each processing unit and the upper processor.

The IPC processing unit 700 provides a signal transmission and reception medium with a higher processor.

The controller 800 initializes various devices, performs a driver program function, and performs a signal processing program function.

Hereinafter, an operation process of the composite ATM subscriber matching apparatus of the present invention will be described with reference to FIG. 4.

The composite ATM subscriber matching apparatus of the present invention may be divided into three processing units according to each subscriber matching type, and the signal exchange unit 200 receives a setting command in the form of a subscriber to be serviced by an upper processor and sets a mode. Take That is, the upstream module 210 of the signal exchanger 200 classifies the data according to the type of the subscriber receiving the data and transmits the data to the corresponding processing unit. The downstream module 220 matches the data received from the corresponding processing line with each subscriber line. It performs the role of transmitting to the unit (100). For example, when the subscriber type in which data is received is a frame relay service method, the upstream module 210 of the signal exchanger 200 transmits the received data to the FR processor 300.

First, when the FR service is to be performed, the data coming from the line matching unit 100 through the signal exchange unit 200 is processed through the HDLC controller or the HDLC control memory in the protocol processing unit 310 to perform the bus arbiter unit 340. By the control, it is stored in the packet memory unit 330 through the buffer unit 320. Meanwhile, the SAR processor 350 performs the AAL5 function of classifying the frame relay data received from the protocol processor 310 into an ATM cell or reassembling an ATM cell received from a higher processor by the bus arbiter 340. Here, the HDLC control memory stores transmission / reception connection information and information on the packet memory unit 330 to store transmission / reception data. The bus arbiter 340 appropriately controls the bus so as to share the packet memory 330 in order to eliminate data usage by the processor when converting protocol data between the protocol processor 310 and the SAR processor 350. When the ATM cell data processed by the SAR processor 350 is sent to the FIFO 370 after VPI / VCI conversion is performed by the header converter 360, 3 bytes of routing tags are attached to the header and recorded in the FIFO 370. Based on the read enable signal applied from the upper processor, the bus is transferred to the upper processor through the cell bus interface 600 according to the bus clock. In this case, an idle cell or an unassigned cell is created and transmitted between user cells in order to control the cell rate.

The FIFO 370 scans a received start of cell (SOC) signal from a higher processor to classify the cell boundary and compares it with its B'd ID (Board Identification) received with the receiving SOC to receive the cell. Distinguish whether or not. Here, the routing tag is ignored and discarded. When one or more cells are filled in the FIFO 370, a cell recognition signal is generated in the FIFO 370, and the cell data is read and processed in the reverse process.

On the other hand, if you want to service the line data through the public telecommunications network to remove each conversion code of each information and data received by the line matching unit 100 and transmit to the SAR processing unit 410, SAR processing unit 410 is AAL1 By adding a function, channel data and information are converted into a cell bus (53 bytes), and are transmitted to the uplink cell processor 430 in synchronization with a clock. Here, the SRTS processing unit 420 uses the frequencies provided in each channel or the terminal, adjusts the remaining time of the frequencies, extracts and restores the originally required clock from the reception clock, and uses other channels linked with each channel. Alternatively, the clock is linked to the CE processor channel to synchronize the frequency between terminals, and if the frequency is not synchronized, the TS is compared with the TS value received from the receiver and transmitted through the PLL. The clock on the side is restored to synchronize.

The information transmitted to the uplink cell processor 430 is made into a cell bus, and the data is stored in the FIFO in the upcell processor 430. If the cell bus is valid by determining whether the current cell bus is valid or not, the uplink HTT header is applied. Translation Table) Change the header stored in DPRAM.

Here, when it is not a valid cell bus compared with the data of the upper HTT DPRAM, all 53-byte cells are deleted to empty the FIFO in the uplink cell processor 430.

The cell to be transmitted to the upper processor by the enable signal UP-REQ * at the moment when 4 headers already stored in the FIFO in the uplink cell processor 430 and 28 words of the payload 24 words of the cell bus are recorded. When the bus is notified and the response signal UP-REN * is received, the SOC and the cell bus are transmitted through the cell bus interface 600 according to the clock.

On the other hand, the downlink cell processor 440 configures the cell bus received through the FIFO 450 as a 56-byte operation and maintenance (OAM) cell (in this case, the OAM cell is 16-bit, that is, a 28-word (56-byte) cell). Bus, and reads the header part of the cell bus, that is, three words, and stores necessary information of 12 bits of VPI information, 16 bits of VCI information, and 3 bits of line information, and stores a 5-byte header if it is normal compared to the lower HTT DPRAM. do. Here, the line information becomes an important element constituting the address of the header and informs whether the address of the actual transmission data test OAM is valid using the validity of the cell bus being transmitted and the test flag in addition to the VPI and VCI information to actually convert the address.

When one cell bus 53 bytes are stored in the FIFO in the downlink cell processor 440, the enable signal is informed to the SAR processor 410, and when the SAR processor 410 supplies a response signal and a clock, the down_AAL1_SOC and the cell bus are supplied. Is transmitted to the SAR processing unit 410.

On the other hand, when matching with the ATM subscriber performing the ATM function to service the cell of the E1 frame received by the line matching unit 100 by using the HEC to separate the cell boundary to transmit to the transmission processor 520 to convert the header After that, the data is stored in the FIFO in the transmission processing unit 520.

When the data stored in the FIFO in the transmission processor 520 is read, a 3-byte header including a 1-byte link ID is attached to the FIFO 540, and the upper processor signal is transmitted, and the upper processor sends a read enable signal. When the FIFO 540 receives the read enable signal, the FIFO 540 transmits the cell data and the SOC to the higher processor through the cell bus interface 600.

On the other hand, the ATM cell received through the cell bus interface 600 is 56 bytes of VPI / to distinguish whether the point-to-point (PTP) or point-to-multipoint (PTMP) and give a link number for each subscriber Multicasting is performed through VCI conversion. If the B'd bit map of the cell bus is checked and its bit is reset, the cell is accepted and the subscriber link number is checked again and accumulated in the subscriber's cell bus reception FIFO.

If the cell read from the FIFO 540 is a multicasting cell, VPI / VCI is converted and sent to the cell extracting / inserting unit 510. Here, if the read cell is a PTP cell, it is sent to the cell extraction / insertion unit 510 without any conversion. If VPI is 1 in the table, only VPI is converted, VCI is transmitted as it is, and if VPI is 0, both VPI and VCI are converted.

The complex ATM subscriber matching apparatus of the present invention is not limited to the above-described embodiment, and can be implemented in various modifications within the range allowed by the technical idea of the present invention.

According to the composite ATM subscriber matching device of the present invention as described above, by providing a network matching between heterogeneous devices by providing a FR / CE / ATM processing unit on one board to handle the network matching between heterogeneous devices on one board at the same time It can be effective. In addition, the system configuration according to the service type is simple, and the modular method is easy. On the other hand, by integrating overlapping circuits, the hardware structure is simplified and the cost is reduced. In addition, it is possible to make the best use of the available link channel and to facilitate maintenance management.

Claims (4)

A line matching unit providing a network and matching and matching electrical characteristics; A signal exchange unit for switching a corresponding service subscriber to a corresponding protocol processing unit and for connecting and connecting data received from a network to the corresponding service subscriber; A frame relay processor for matching the frame relay protocol and the ATM protocol by converting the frame relay data and the ATM cell data; A circuit emulation processing unit for matching circuits with a public circuit network to emulate circuit data of a subscriber frame, converting the circuit data into an ATM cell, and providing communication with a higher processor; An ATM processor that matches with a low-speed ATM subscriber and provides an access service to an upper ATM network; A cell bus interface unit for providing protocol matching between a memory unit and an upper processor included in each processing unit; An IPC processor providing a signal transmission / reception medium with an upper processor; And A complex asynchronous transmission mode subscriber matching device comprising a control unit which controls the entire system and performs initialization of various devices, execution of a driver program function, and a signal processing program function. The method of claim 1, wherein the frame relay processing unit A protocol processing unit which performs frame relay data processing; A packet memory unit for storing ATM cells; A bus arbiter section for controlling bus occupancy rights between bus masters of respective devices; A buffer unit for providing communication between the packet memory unit and a protocol processing unit under control of the bus arbiter unit; A division and resynthesis processing unit for dividing the frame relay data received from the protocol processing unit into ATM cells or resynthesizing the ATM cells received by the processor; A memory unit for monitoring cell signals transmitted and received with an upper processor to distinguish between cell boundaries and whether a cell is to be received; And And a header converting unit configured to receive an ATM cell, perform routing tagging, and transmit it to the memory unit, or delete tagging information of the ATM cell received from the memory unit. The line emulation processing unit of claim 1, wherein the line emulation processing unit A division and resynthesis processing unit for dividing the contents of the cell transmitted by the upper processor into channels, delivering corresponding data and information for each channel, and converting channel data and information received from the line into a cell bus; A synchronous residual time stamp processing unit performing a function of restoring a clock; A memory unit for monitoring cell signals transmitted and received with an upper processor to distinguish between cell boundaries and whether a cell is to be received; And And an uplink / downlink cell processing unit for performing ATM cell transmission / reception processing and header conversion function between the memory unit and the partition and resynthesis processing unit. The method of claim 1, wherein the ATM processing unit A cell extracting / inserting unit for describing and transmitting an ATM cell received at the line matching unit; A transmission processor configured to header convert a cell received by the cell insertion / extraction unit; A memory unit configured to transmit cell data and a cell start signal to an upper processor through the cell bus interface unit when receiving a read enable signal from an upper processor; And And a reception processing unit for converting VPI / VCI to the cell extraction / insertion unit if the cell received by the memory unit is a multicasting cell.