KR960014412B1 - Hdlc communication system using t1 - Google Patents

Abstract

a first bit rate converting means (11) for converting the HDLC format data received from the outside into the input data having 8 bits unit, and outputting ti as a PCM data type with 32 channels; a time slot converting means (13) for occupying transmitting and the channel corresponding to the 32 channels PCM data inputted from the first bit rate converting means (11) to satiety the HDLC communication speed; a T1 relay line access means (15) for setting to inverse only related data among N bytes data of the HDLC data format from the first bit rate converting means; a second bit rate converting means (12) for converting the 32 channels PCM dta inputted from the time slot converting means (13) by inputting the clock from the outside into related HDLC communication speed, and outputting them; and a data converting means 14 for transmitting and restoring the degenerated HDLC data format among the HDLC data format through the first bit rate converting means 11.

Description

H.D.L.C (HDLC) Communication System Using T1 Transmission Line

1 is an overall block diagram according to the present invention.

2 is a diagram illustrating a change in HDLC data format.

3 is a detailed configuration diagram of the data conversion unit.

* Explanation of symbols for main parts of the drawings

11, 12: bit rate converter 13: time slot matching unit

14 data conversion unit 15 T1 relay line matching unit

The present invention relates to an H.D.L.C (HDLC) communication system using a T1 (T1) transmission path.

When data is transmitted using a conventional T1 (North American PCM trunk line), data corruption may be caused by bit 7 stuffing zero code suppression. That is, if there are more than 8 consecutive '0's in the data, when the data is transmitted to the PCM relay line,' 1 'is forcibly inserted into the seventh bit to transmit the data. In this case, when the data hexa value '00' that is known to be transmitted reaches the receiving end through the PCM relay line and the transmission path, the data hexa value '00' is changed to the data hexa value '02'. Therefore, data communication using T1 transmission channel using bit 7 stuffing zero code suppression method is possible when hexadecimal value '00' does not exist in data, and similarly, HDLC data communication is performed in data consisting of N bytes of HDLC data format. '00' should be absent and '00' should not be generated to enable HDLC data communication. Data-free HDLC communication is possible using B8ZS with zero-code suppression on PCM trunks.

However, there is a problem in that the existing zero code suppression method of the transmission path has to be changed to B8ZS in bit 7 stuffing. Accordingly, the present invention devised to solve the above-mentioned problems with the prior art is '00 among the data consisting of N bytes of the HDLC data format to enable HDLC communication to the PCM relay line using the bit 7 stuffing zero code suppression method. The present invention provides an HDLC communication system that enables long-distance HDLC communication using an existing T1 transmission line by using a circuit that changes and transmits data so that it does not occur and thereby reduces corrupted idle data. There is a purpose.

In order to achieve the above object, the present invention, the first bit rate conversion means for receiving the HDLC format data received from the outside received a clock and load signal to process the input data in 8-bit units in the form of 32-channel PCM data; Time slot converting means for transmitting the 32-channel PCM data coming from the first bit rate converting means to occupy the corresponding channel according to the HDLC communication rate; T1 relay line matching means for setting an inversion of only the data among the data consisting of N bytes in the HDLC data format from the first bit rate conversion means, and inverting and transmitting the occupied data intact; Second bit rate conversion means for receiving a clock from the outside and converting 32-channel PCM data input from the time slot conversion means to a corresponding HDLC communication speed and outputting the converted data; And data conversion means for reducing and transmitting the corrupted HDLC data format among the HDLC data formats through the first bit rate conversion means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is an overall block diagram according to the present invention, in which 11 and 12 are bit rate converters, 13 are time slot matching units, 14 data conversion units, and 15 T1 relay line matching units, respectively.

Looking at the effect of using the configuration of the present invention as shown in the drawings as follows.

First, the bit rate converter 11 receives a 2.048 MHz clock and a load signal from the received HDLC format data, processes the input data in units of 8 bits, and converts the data into 32 channel PCM data.

The time slot converter 13 occupies and transmits 32 channel PCM data coming from the bit rate converter 11 in accordance with the HDLC communication speed.

For example,

-Occupy 1 channel when HDLC communication speed is 64Kbps

-Occupy 2 channels when HDLC communication speed is 128Kbps

－ Occupies 4 channels when HDLC communication speed is 256Kbps

Occupied eight channels when the HDLC communication rate is 512 Kbps;

-If the HDLC communication speed is 1024 Kbps, 16 channels are occupied.

The T1 relay line matching unit 15 sets the data so that only the data occupied in order to remove '00' existing in the data consisting of N bytes in the HDLC data format from the bit rate converter 11 is inverted. Is sent to T1 transmission channel, and the data occupied in reverse is reversed and transmitted.

The bit rate converter 12 receives a clock from the outside and converts the 32-channel PCM data input from the time slot converter 13 to the corresponding HDLC communication speed and outputs the converted data.

The data converter 14 reduces the HDLC data format through the bit rate converter 12 to the original data format.

2 is an example of changing the HDLC data format, in which (A) is a data type input to the bit rate converter 11, (B) is a data type passing through the transmitting end of the time slot converter, and (C) The data format is input to the time slot changing unit and the bit rate converter. Here, all data are expressed in hexa value, and the data is cut out and expressed in 8 bit units for convenience.

3 is a detailed view of the data converter 14, in which 31 and 32 are serial / parallel converters, 33 and 35 are idle detectors, 34 and 36 are flag detectors, 37 are valid data area detectors, and 38 are D. FIG. Flip-flops are shown respectively.

As shown in the figure, the data converter 14 converts the 'id' code 'FD' into 'FF' to change the data format as in the data format D of FIG. 2 to the original HDLC data format. Should be changed to To this end, the data RXDATA provided from the bit rate converter 12 is converted into a 16-bit parallel signal through the serial and parallel converters 31 and 32 and output through the D flip-flop 38. At this time, the idle detectors 33 and 35 detect whether there is an idle code FD in the parallel data stream and send it to the valid data area detector 37. At the same time, the flag detectors 34 and 36 perform flag code (D) in the data stream. 7E) is detected and transmitted to the valid data detection unit 37.

The valid data detector 37 receives signals received from the idle detectors 33 and 35 and the flag detectors 34 and 36 as inputs, and the time point at which the N byte data string and the last flag ends from the time point at which the start flag is present. A signal indicating that valid data up to is generated and transmitted to the preset stage of the D flip-flop 38.

Only when the N byte data including a flag among the data strings input to the D flip-flop 38 passes, the preset signal of the D flip-flop 38 is maintained in a 'high' state to pass normally, and the corrupted idle code FD ), The preset signal of the D flip-flop 38 is kept low, thereby making the output of the D flip-flop 38 high. Therefore, in the section in which the corrupted idle code passes, the output of the D flip-flop 38 remains 'high', so that the idle code is converted to 'FF' and restored to the normal HDLC data format and transmitted to the final receiver.

In the present invention as described above, the data is changed and transmitted so that '00' does not occur in the data consisting of N bytes of the HDLC data format to enable HDLC communication to the T1 PCM relay line using the bit 7 stuffing zero code suppression method. Therefore, there is an advantage that the long-distance HDLC communication using the existing T1 transmission line by using a circuit that reduces the corrupted idle data as it is.

Claims (2)

First bit rate converting means (11) for receiving an externally received HDLC format data and receiving a clock and a load signal to process input data in units of 8 bits and to output 32 channel PCM data; Time slot converting means (13) for transferring the 32-channel PCM data coming from the first bit rate converting means (11) by occupying the corresponding channel according to the HDLC communication speed; T1 relay line matching means (15) for setting the inversion of only the data among the data consisting of N bytes in the HDLC data format from the first bit rate converting means (11), and inverting and transmitting the occupied data intact. ; Second bit rate converting means (12) for receiving a clock from the outside and converting 32-channel PCM data inputted from the time slot converting means (13) to a corresponding HDLC communication speed and outputting the converted data; And data conversion means (14) for reducing and transmitting the corrupted HDLC data format of the HDLC data format through the first bit rate conversion means (11). H.D.L.C (HDLC) communication system. The data converting means (14) according to claim 1, wherein said data converting means (14) comprises first and second serial / parallel converting means (31) for converting data input through said second bit rate converting means (12) into a 16-bit parallel signal. , 32); First and second idle detection means (33, 35) connected to the first and second serial / parallel converting means (31, 32), respectively, for detecting whether an idle code (FD) is present in the data sequence; Connected to the first and second serial / parallel conversion means 31 and 32, respectively, the first and second idle detection means 33 and 35 simultaneously detect the presence of the flag code 7E in the data stream and transmit the same. First and second flag detection means (34, 36); Idle data area detection means for generating and transmitting a valid data presence signal by inputting the signals received by the first and second idle detection means 33 and 35 and the first and second flag detection means 34 and 36. (37); And a D flip-flop 38 which receives data output from the second serial / parallel conversion means 32 and outputs data by an idle data presence signal from the valid data area detection means 37. H. D.L.C (HDLC) communication system using a T1 transmission path, characterized in that configuration.