JPS61101142A - Data protection circuit - Google Patents

Abstract

PURPOSE:To eliminate a data error generated on a transmission line by allocating a data from a data terminal device of a low speed at the transmission side into a frame, transmitting a frame having the same data content for plural number of times, taking majority decision of the frame data received for plural number of times at the reception side and using it as a reception data and transmitting it to a data terminal device of low speed at the reception side. CONSTITUTION:A data from a low speed data terminal device 1 enters a sampling circuit 2-1, a bit signal obtained from the sampling is fed to a transmission side shift register 2-3, a synchronizing flag bit from a synchronizing flag generating circuit 2 is added at plural n-bit, and the result is transmitted for plural number M of times as a high speed synchronizing data. A reception side data adaptor 5 stores the plural M-set of frame signals to a signal shift register 5-1 one after another, a synchronism detection circuit 5-2 detects the synchronizing flag bit and moves only the reception data to a datalatch circuit 5-3a one after another. The data latch circuit 5-3a applies majority decision to the M-set of frame data and its output data is inputted to an output shift register 5-4.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to data transmission, and in particular to a data protection circuit for transmitting data between low-speed data terminals using a high-speed data transmission line. It is related to.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional data protection circuit when data is transmitted between low-speed data terminals via a high-speed data transmission line.

In the figure, 1 is a low-speed data terminal (sending side), 2 is a data adapter for low-speed data terminal 1, 3 is an exchange, 4 is a low-speed data terminal (receiving side), and 5 is a data adapter for low-speed data terminal 4. It is.

Here, as an example, it is assumed that the low speed is a communication speed of 300 bps, and the high speed is a communication speed of 64 K bps.

When sending data from low-speed data terminal 1 to low-speed data terminal 4 via a high-speed data transmission line, connect data adapter 2 to the output side of low-speed data terminal 1, as shown in Figure 1. Converts to high-speed data and sends it out.

This data is sent to the receiving side via the exchange 3 and the like, and on the receiving side, it is first received by the data adapter 5, converted into low-speed data, and then sent to the low-speed data terminal 4.

Data exchange between the low speed data terminal 1 and the data adapter 2 and between the data adapter 5 and the low speed data terminal 4m1 is performed using, for example, an R3232C ink face.

Communication must be performed by converting the signal format in this way, and the above operation will be explained in more detail next.

FIG. 4 is a configuration diagram of the transmitting side data adapter and the receiving side data adapter shown in FIG. 3.

In the figure, 2-1 is a sampling circuit, 2-3 is a transmission side shift register, 5-1 is a reception side shift register, 5-3 is a data launch circuit, and 5-4 is an output shift register.

FIG. 5(a) shows data sent from the low-speed data terminal 1, and FIG. 5(b) shows a signal sent from the data adapter 2 on the sending side.

The data from the low-speed data terminal 1 is an asynchronous signal in which a start signal ST, a data signal, and a stop signal SP are arranged in this order as shown in FIG. 5 (Bj).

Data from such a low-speed data terminal 1 enters the sampling circuit 2-1, where it is sampled by a high-speed clock, and the signal obtained by sampling is sent to the transmission side shift register 2-3, where it is high-speed. Send as speed data.

In this case, as mentioned above, the communication speed is 64 K bps vs. 300 bps, which is a difference of more than 200 times, so
The transmission side shift register 2-3 will send out the same low-speed data many times.

Therefore, the "1" signal of the low speed data is the same data sampled by the sampling circuit 2-1.
It will be sent 0 or more times.

The receiving side data adapter 5 receives the above signal, stores it in the receiving side shift register 5-1, transfers the data to the data launch circuit 5-3, and then transfers the data to the output shift register 5-4.
Output to.

The data adapter 5 on the receiving side uses this output shift register 5.
-4 is output to the low-speed data terminal 4 as an output.

[Problem that the invention seeks to solve]

In the conventional method described above, low-speed data is sampled at high speed and only one piece of data is received, so if a bit error occurs in the high-speed data line, its impact will be It had the disadvantage of being strongly affected by

It is an object of the present invention to provide a data protection circuit that is tolerant to noise on high speed data lines.

[Means for solving problems]

A means to solve the problem is that when data is transmitted from a low-speed data terminal on the transmitting side to a low-speed data terminal on the receiving side via a high-speed data transmission line, the transmission from the low-speed data terminal on the transmitting side is Data is sampled and stored in a frame provided with a synchronization flag, the frame with the same data content is sent multiple times, and the receiving side takes a majority vote of the received frame data and uses it as received data. This is achieved by transmitting the speed of data terminals.

[Effect]

According to the present invention, the same frame obtained by sampling data from a low-speed data terminal at high speed and storing it in a frame provided with a synchronization flag is transmitted multiple times, and the receiving side receives the received frame data multiple times. Since the received data is determined by a majority vote, the received data is completely unaffected by transmission errors.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a data protection circuit according to the present invention.

FIG. 2 is a diagram for explaining the operation of the data protection circuit of the present invention shown in FIG. 1.

In the figure, 5-3a is a data latch circuit according to the present invention;
5 is a majority circuit.

The present invention will be described in detail below with reference to the drawings.

In the present invention, data from the low-speed data terminal 1 shown in FIG. 2(a) enters the sampling circuit 2-1 and is sampled by a high-speed clock. Note that FIG. 2 (al is the same as the above-mentioned FIG. 5 (+1).

The bit signal obtained by sampling is sent to the transmission side shift register 2-3t, and a synchronization flag signal from the synchronization flag generation circuit 2 is added to every n bits to create a frame as shown in FIG. 2 Tb). It is sent multiple M times as high-speed synchronization data.

Note that the value of the plurality M is an arbitrary value.

In the receiving side data adapter 5 according to the present invention, these plural M frame signals are stored one after another in the receiving side shift register 5-1, the synchronization flag bit is detected by the synchronization detection circuit 5-2, and the frame signals are stored one after another by the launch clock. Only the received data is transferred to the data latch circuit 5-3a.

The data latch circuit 5-3a has a capacity capable of storing M frames of data, and the majority decision circuit 5-5 takes a majority decision regarding the M frames of data stored in the guitar association circuit 5-3a. , and inputs its output data to the output shift register 5-4.

The data stored in the output shift register 5-4 in the data adapter 5 according to the invention is sent to the receiving low-speed data terminal 4. Since this data is obtained by majority vote, it is not affected by transmission errors.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect of being able to eliminate data errors that occur on the transmission path.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a data protection circuit according to the present invention. FIG. 2 is a diagram for explaining the operation of the data protection circuit of the present invention shown in FIG. 1. FIG. 3 is a diagram showing an example of a conventional data protection circuit when data is transmitted between low-speed data terminals via a high-speed data transmission line. FIG. 4 is a configuration diagram of the transmitting side data adapter and the receiving side data adapter shown in FIG. 3. FIG. 5 (al indicates the data sent from the low-speed data terminal l, and (bl indicates the signal sent from the data adapter 2 on the transmitting side. In the figure, 1 indicates the low-speed data terminal (transmitting side), 2 is a data adapter for low-speed data terminal 1, 3 is an exchange, 4 is a low-speed data terminal (receiving side), 5 is a data adapter for low-speed data terminal 4, 2-1 is a sampling circuit, 2-2 is a synchronization flag generation circuit, 2-3 is a transmission side shift register, 5-
1 is a receiving side shift register, 5-2 is a synchronization detection circuit, 5
-3 is a data latch circuit, 5-4 is an output shift register, 5-3a is a data latch circuit according to the present invention, 5-5
is a majority circuit. Figure 1

Claims (1)

[Claims] When transmitting data from a low-speed data terminal on the sending side to a low-speed data terminal on the receiving side via a high-speed data transmission line, the data from the low-speed data terminal on the sending side is sampled and a synchronization flag is set. The frame is stored in a frame, and the frame with the same data content is sent out multiple times, and the receiving side takes a majority vote of the received frame data for the plurality of times, becomes received data, and sends the received data to the receiving side low-speed data terminal. data protection circuit.