KR960011133B1 - Pn generation unit of 1.544 mbps digital line - Google Patents

Abstract

The generator for providing a good simulation in random errors on DS1(Digitl Signal Level 1) lines, includes a line matching part converting DS1 signals into binary digital data in non return zero form, an error generator receiving the data to feed them to the line matching part in inverted form or in not inverted form, a pseudo random clock generator synchronized by received clocks from the line matching part, an user matching part resetting inner values.

Description

Pseudorandom error generator for digital line

1 is a bit error rate (BER) insertion timing diagram according to the prior art.

Figure 2 is a schematic diagram showing the configuration of a pseudo random error generating apparatus according to the present invention.

Figure 3 is a detailed configuration of an embodiment of the line matching portion of Figure 2 according to the present invention.

4 is an output timing diagram of the line matching unit shown in FIG.

Figure 5 is a detailed configuration of an embodiment of the error generator of Figure 2 according to the present invention.

6 is an operation tie diagram of the error generator of FIG.

7 is a block diagram of an embodiment of the pseudorandom clock generator of FIG. 2 according to the present invention.

8 is a detailed configuration diagram of one embodiment of the MLSR of FIG. 7 according to the present invention.

9 is a detailed configuration diagram of an embodiment of a user matching unit of FIG. 2 according to the present invention.

* Description of the main parts of the drawings

201: line matching unit 202: error generating unit

203: Pseudorandom clock generator 204: User matching unit

The present invention is a device that is inserted in the section that receives the DS1 (Digital Signal Level 1) level of the domestic digital transmission network, by inserting a pseudo-random error corresponding to any Bit Error Rate (BER) to the line The present invention relates to a pseudo-random error generating device for a digital line that simulates an error that may occur in a real line.

A conventional error generating device is inserted into a transmission path, and as shown in FIG. 1, the time slot position in the BER period is as shown in (a) of FIG. 1 or by one bit as shown in (b) of FIG. It was to insert the moved error 101.

However, since the time slot positions of the line errors that can occur in the actual line are random according to time, the conventional error generating device described above can generate an error in accordance with the BER, but the line error generated in the line The problem was that the form was completely different.

Accordingly, an object of the present invention is to provide an error generating device for a digital line which generates and inserts a pseudo random error into a line in order to effectively simulate a random error that may occur in a section of a DS1 signal.

In order to achieve the above object, the present invention is made.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

2 is a block diagram schematically showing the configuration of a pseudo random error generating apparatus according to the present invention, in which 201 is a line matching unit, 202 is an error generating unit, 203 is a pseudo random clock generating unit, and 204 is a user matching unit. do.

The pseudorandom error generating apparatus according to the present invention includes a line matching unit 201, an error generating unit 202, a pseudorandom error generating unit 203, and a user matching unit 204, as shown in the drawing. The DS1 line signal 211 input at 1.54 Mbps passes through the line matching unit 201 to change the non-zero zero form NR, which is binary digital data, to 213. The signal is inverted or non-inverted according to the presence or absence of the inverted signal COUT 216 outputted from the pseudo random clock generator 216 while passing through the error generator 202 to match the line in the form of NRZ 214. It is input to the unit 201.

The NRZ type data input to the line matching unit 201 is converted into a 1.544 Mbps line signal 212 which is a DS1 signal and output. The period of the inverted signal (COUT) 216 generated by the pseudorandom clock generator 203 is set by the user matching unit 204 according to the BER value (B0-B2; 218), and the range of BER that can be set. Is 10 ⁻² to 10 ⁻⁶ . The pseudo-random clock generator 203 is synchronized by the reception clock 215 extracted by the line matching unit 201 and its internal values are reset by the reset signal 217 from the user matching unit 204. .

3 is a detailed block diagram of an embodiment of the line matching unit of FIG. 2 according to the present invention.

As shown in FIG. 3, the line matching unit 201 may include a known line matching VLSI chip 301, a pulse transformer 302, and passive elements.

The line matching VLSI chip (R8069B; Rockwell, USA) satisfies G.703 and G.823 of the CCITT Recommendation for line matching, and is configured to provide equalizer and line service functions. And converts the 1.544Mpbs line signal into positive and negative NRZ type digital data (ROPS and RNEG) 402 and other synchronization information.

The present invention utilizes NRZ type digital data output from the VLSI chip 301 and receiving clocks 215 and 401 of 1.544MHZ. The output timing diagram of the line matching unit 201 is shown in FIG.

FIG. 5 is a detailed configuration diagram of an error generating unit of FIG. 2 according to the present invention, in which 501 denotes a register unit and 502 denotes a selection unit.

As shown in the drawing, the error generator 202 may include first to third D flips connected to receive the positive and negative NRZ data (RPOS and RNEG) and the inverted signal (COUT) 505 one by one to the data input terminal (D). The register unit 501 including the flops 501a, 501b, and 501c, and the non-inverted output and the inverted output of the first D flip-flop 501a of the register unit 501 are respectively input to the two data input terminals. Two data input terminals include a non-inverted output and an inverted output of the first selection element 502a connected to receive the non-inverted output of the flip-flop 501c and the second D flip-flop 501b of the register unit 501. And a second selecting element 502b connected to each other and receiving the non-inverting output of the 3D flip-flop 501c as an enable terminal, with or without an inversion signal COUT (refer to 601 in FIG. 6). Selector 502 for generating an error by inserting an error bit (see 602 in FIG. 6) accordingly. It is configured.

That is, when the inversion signal COUT is not generated from the pseudo random clock generator 203, the error generator 202 returns the NRZ data 503 inputted from the line matching unit 201 without inversion. While passing through the line matching unit 201 again, if an inverted signal is applied from the pseudo random clock generation unit 203, the corresponding one bit of the digital data input from the line matching unit 201 is inverted (602). By making the output 504 to the line matching unit 201 to make the desired BER.

The process is well illustrated in the timing diagram of FIG. 6, in which the input NRZ data (RPOS, RNEG; 603) has an error inserted (602) or outputted as originally due to the presence or absence of an inverted signal (COUT) (601). The result is output NRZ data (TPOS, TNEG) 604.

7 is an exemplary configuration diagram of the pseudorandom clock generator of FIG. 2 according to the present invention, in which 701 is a 48-bit maximum length shift register (MLSR), 702 is simply referred to as MLSR in FIG. A binary / BCD (Binary Coded Decimal) converter, 703 is a 24-bit comparator, 708 to 712 are AND products, and 173 is a BER selector.

As shown in the figure, the pseudorandom clock generation unit 203 receives a reception clock and generates a 48-bit maximum length shift register 701 for generating a pseudorandom sequence of shift signals shifted to the right by one bit, and the 48 Binary / BCD converter 702 which receives the output of the maximum bit length shift register 701, converts it into BCD code, and outputs it in decimal form, and sequentially outputs each output of the binary / BCD converter 702 by 4 bits. A 24 bit comparator 703 for comparison, an OR product processing unit 708 to 712 for performing an AND operation on the output of the 24 bit comparator 703, and an output of the AND product processing unit 708 to 712 for user matching. And a BER selector 713 which selects according to the control signals B0-B2 (714) input from the unit 204 and outputs an inverted signal COUT.

8 is a detailed block diagram of an embodiment of the MLSR of FIG. 7 according to the present invention.

As shown in the figure, the 48-bit MLSR 701 of the present invention is a function unit for generating a pseudorandom sequence, and has a structure in which 48 registers 801 are connected in series, and a reference clock. By 803, the bit shifts to the right by one bit.

To generate the maximum pseudorandom period, certain registers (R6, R31, R46) were taken to the final output and the exclusive logical product 802 and then returned to the input. As the reference clock, line receiving clock 1.544MHz was used. The total pseudorandom period is 2 ⁴⁸ and corresponds to approximately 2110 days at 1.544 MHz, ensuring sufficient period for the test.

The initial value of the MLSR registers is set to mode 1 upon reset 804 of the device. In the present invention, a simple logic cell array is used to realize this.

The binary / BCD converter 702 converts 20 bits of the 48-bit outputs of the MLSR 701 into 24-bit BCD codes and outputs them in decimal form. In this embodiment, 27 of 74AS185 are used to realize this.

The comparator 703 may set an arbitrary BCD value every 4 bits. The comparator 703 compares the set value (set to 0; 705) with the output value 706 of the binary / BCD conversion valuer. Output 707.

These outputs are then combined into five AND gates 708-712 to be classified into values in the range 10 ² -10 ⁶ , the sorted values being selected by the BER selector 713 and output as an inverted signal COUT. do. BER selection is controlled by B0 through B2 714, which are outputs of the user matching section.

9 is a detailed configuration diagram of an embodiment of the user matching unit of FIG. 2 according to the present invention.

As shown in the figure, the user matching unit 204 includes a key input unit 901, a display unit 902, and a 3-bit register 903.

The user matching unit 901 is configured to maintain a predetermined value until the BER value 904 that is set is temporarily stored in the register 903 so that another value is set. It is composed of a known keypad and logic, the display unit 902 is realized by using a known LCD (16Character) having a data matching function. In the drawing, reference numeral KCLK (Key Syncronize Clock) is a signal indicating the presence or absence of key input data, and KDATA (Key DATA) is a 3-bit key input value.

The present invention, which is constructed and operated as described above, is inserted into a DS1 class signal receiving section having the highest configuration rate among domestic digital transmission networks, and generates a pseudo random error similar to a random error that may occur in an actual line. It is easy to carry and economical because it can be used and compactly simplified.

Claims (1)

A pseudo-random error generating device for digital lines, which receives a digital signal level 1 (DS1) line signal input at 1.54 Mbs and converts it into binary digital data NRZ (Non Return to Zero) form 213 for output. Line matching means 201; After receiving NRZ (Non Return to Zero) data output from the line matching means 201, the bit matching means 201 generates an error bit by inverting and non-inverting the corresponding bit according to an inversion signal (COUT) 216. Error generating means 202 for outputting back to; Pseudorandom clock generation means synchronized with the reception clock 215 outputted from the line matching means 201 and generating an inverted signal COUT 216 for controlling the error bit generation operation of the error generation means 202. 203; And a bit error rate (BER) value 218, which is set to determine a period of the inversion signal COUT output from the pseudorandom clock generation means 203, and is preset until another value is set. And user matching means 204 for continuously maintaining the first and second error generating means 202. The first and second error generating means 202 may be connected to receive the positive and negative NRZ data and the inverted signal COUT 216 one by one into the data input terminal D. A register 501 having a 3D flip flop; And a non-inverting output and an inverting output of the first D flip-flop 501a of the register unit 501 to two data input terminals, respectively, and receiving a non-inverting output of the 3D flip-flop 501c as an enable terminal. The non-inverting output and the inverting output of the first selection element 502a and the second D flip-flop 501b of the register unit 501 are respectively input to two data input terminals, and the non-inverting output of the 3D flip-flop 501c is received. And a second selection element 502b connected to be input to the enable terminal, and a selection unit 202 for generating an error by inserting an error bit according to the presence or absence of an inversion signal (COUT) 216. The pseudorandom clock generating means 203 includes: a 48-bit maximum length shift register 701 which generates a pseudo random sequence of shift signals received by the reception clock and shifted by one bit to the right; A binary / BCD converter 702 which receives the output of the 48-bit maximum length shift register 701 and converts it into a BCD code and outputs it in decimal form; Logical AND processing units 708 to 712 for logical AND processing the output of the binary / BCD converter 702; And a BER selector 713 connected to receive the outputs of the AND products 708 to 712, and outputting an inverted signal COUT 216 according to a control signal input from the user matching means 204. Pseudorandom error generating device for a digital line, comprising: a.