JP2833922B2 - PN code inspection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PN (Pseudo Noise, Pseudo Noise) code inspection circuit used for a transmission line test of communication equipment, and more particularly to a method for receiving a signal under test and an internal PN code generation circuit. Faster PN
The present invention relates to a code check circuit.

[0002]

2. Description of the Related Art In general, a PN code inspection circuit is composed of n stages.
= 15 is generated by the polynomial X ¹⁵ + X + 1 (CCITT Recommendation 0.
151) using a PN code.

Conventionally, a PN code inspection circuit of this type is shown in FIG. PN that generates a PN code for verification
A code generation circuit 50, a flip-flop 7 for retiming the external input test data 101, and a comparator 3 for comparing the output signal generated by the PN code generation circuit 5 with the external input test data. And a counter 6 for counting the number of pull-in data when pulling the data under test 101 into the PN code generation circuit 5.

In this circuit, when checking the PN code of the data under test 101, first, the data under test 1
01 to the PN code generation circuit 5,
At this time, since the PN code generation circuit 5 is composed of a 15-stage shift register, 15 bits of data to be tested must be loaded. Therefore, the pull-in start control signal from the external control system circuit 9 is counted by the counter 6 to generate a control signal for pulling in for 15 clock times, and the 2-1 selector (2-input 1
Output selector 51) is controlled. Note that the data under test 101 is a PN code signal transmitted on the receiving side from the test PN code signal inserted on the transmitting side of the transmission path under test.

[0005]

In this conventional PN code inspection circuit, when external test data is introduced into the PN code generation circuit in the inspection circuit at the start of measurement, n clock times must be acquired. As the number of stages of the PN code increases, the pull-in time increases, and there is a problem that it takes more time from the start of measurement to the time when a result is obtained.

[0006]

The PN code checking circuit of the present invention alternately includes an n-stage (n is an integer) shift register which receives data under test, a 2-input / 1-output selector and a flip-flop. A PN code generation circuit having a shift register configuration in which n stages are continuously connected to each other and an output signal of each stage of the shift register is used as a corresponding input signal of each stage; an output signal of the first stage of the shift register and the PN code generation A first comparison circuit for comparing the output signal of the first comparison circuit with the output signal of the circuit, and a control circuit for sending a pull-in start signal to each stage of the PN code generation circuit and receiving the output signal of the first comparison circuit to determine a comparison result And

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the present embodiment. Here, assuming that n = 15, the generator polynomial X ¹⁵ + X + 1 (CCI
1 shows a check circuit of a PN15 stage code according to TT Recommendation 0.151). A PN code generation circuit 1 for generating a PN code signal for comparison, a 15-stage shift register 2 to which data under test 101 from the outside is input, and a PN code signal generated by the PN code generation circuit 1 A comparator 3 for collating with the data.

The PN code generation circuit 1 has an n-stage shift register composed of 15 2-1 selectors 11 and 15 flip-flops 12, and a term "1" according to a generator polynomial.
And an exclusive OR circuit 13 having a flip-flop output corresponding to the input as an input. 2-1 selector 11
Has one input terminal connected to the output of the shift register in the PN code generation circuit 1, and the other input terminal connected to the output of each corresponding stage of the shift register 2 that receives the data under test. The selection control terminal S of the 2-1 selector 11 inputs a pull-in start control signal from the external control system circuit 4 in common.

When measuring external input data, the test data 101 is first loaded into the PN code generation circuit 1. The data under test 101 is always input to the shift register 2 irrespective of the execution of the measurement, and the flip-flops of the shift register 2 and the shift register in the PN code generation circuit 1 correspond one to one. Therefore, the data acquisition at the time of measurement is completed in one clock.

[0010]

As described above, according to the present invention, when inspecting a PN code signal, an n-stage shift register is provided independently of the PN code generation circuit, and externally input data under test is always input to the n-stage shift register. However, at the beginning of the measurement,
It has a function of pulling the data latched in the flip-flop in the n-stage shift register into the flip-flop in the PN code generation circuit on a one-to-one basis. For this reason, the pull-in can be completed in one clock time regardless of the number n of stages of the PN code to be tested, so that the test data pull-in time can be greatly reduced and the time required for the test can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment according to the present invention.

FIG. 2 is a block diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PN code generation circuit (CCITT recommendation 0.151) 11 2-1 selector 12 Flip-flop 13 Exclusive logic circuit 2 Shift register 3 Comparator 4 External control system circuit 101 Data under test

Continuation of front page (56) References JP-A-2-257714 (JP, A) JP-A-4-291511 (JP, A) JP-A-3-165622 (JP, A) (58) Fields investigated (Int .Cl. ⁶ , DB name) H04L 29/14 H03K 5/19

Claims (2)

(57) [Claims] 1. A shift register of n stages (n is an integer) configured to receive data under test, and a selector and a flip-flop of two inputs and one output are connected alternately and continuously in n stages. A PN code generation circuit having a shift register configuration using an output signal as an input signal of each corresponding stage, and a first comparison circuit for comparing an output signal of a first stage of the shift register with an output signal of the PN code generation circuit And the P
A PN code inspection circuit, comprising: a control circuit that sends a pull-in start signal to each stage of an N code generation circuit, receives an output signal of the first comparison circuit, and determines a comparison result. 2. The PN code generation circuit according to claim 1, wherein an output signal of said flip-flop is input to one input terminal, and an output signal of each corresponding stage of said shift register is input to another input terminal, and said control circuit is started to input to a selection terminal. N two-input / one-output selectors each for inputting a signal;
The output signals of the n flip-flops for inputting the output signal of the output selector, the output signal of the (n-1) th flip-flop and the output signal of the n-th flip-flop are compared. A second comparison circuit that outputs the signal to the first comparison circuit as an output signal of the PN code generation circuit and simultaneously outputs the signal to one input terminal of the first-stage 2-input / 1-output selector. The PN code inspection circuit according to claim 1.