KR950024078A - Computer Bus Interruption Malfunction Prevention Circuit - Google Patents

Computer Bus Interruption Malfunction Prevention Circuit Download PDF

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Publication number
KR950024078A
KR950024078A KR1019940000540A KR19940000540A KR950024078A KR 950024078 A KR950024078 A KR 950024078A KR 1019940000540 A KR1019940000540 A KR 1019940000540A KR 19940000540 A KR19940000540 A KR 19940000540A KR 950024078 A KR950024078 A KR 950024078A
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KR
South Korea
Prior art keywords
prevention circuit
output
malfunction prevention
bus
signal
Prior art date
Application number
KR1019940000540A
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Korean (ko)
Inventor
조용호
Original Assignee
이헌조
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 엘지전자 주식회사 filed Critical 이헌조
Priority to KR1019940000540A priority Critical patent/KR950024078A/en
Publication of KR950024078A publication Critical patent/KR950024078A/en

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Abstract

본 발명은 최종슬롯 상의 보드에서 출력되는 버스사용허가신호(BG0∼BG3)를 논리곱하는 게이트소자와, 상기 게이트소자의 출력에 따라 입력신호가 결정되어 시스템의 에러발생 신호(SYSFAIL)와 사용중신호(BUSY)를 각각 출력하는 게이트소자로 구성되어 임의의 보드에서 버스사용 요구신호가 출력되어 구동된 상태에서 상기 보드가 갑자기 사용요구신호를 취소해도 버스중재동작이 중지되지않는 컴퓨터의 버스중재오동작 방지회로.According to an embodiment of the present invention, a gate element multiplying the bus permission signals BG0 to BG3 output from a board on a final slot, and an input signal is determined according to the output of the gate element to generate an error signal (SYSFAIL) and a busy signal of the system. A bus arbitration prevention circuit of a computer in which a bus arbitration operation is not stopped even when the board abruptly cancels the request signal while the bus use request signal is output and driven from an arbitrary board. .

Description

컴퓨터의 버스중재오동작 방지회로Computer Bus Interruption Malfunction Prevention Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명을 채용한 컴퓨터의 버스중재회로도.2 is a bus arbitration circuit diagram of a computer employing the present invention.

제3도는 본 발명에 따른 컴퓨터의 버스중재오동작 방지회로도.3 is a bus arbitration malfunction prevention circuit diagram of a computer according to the present invention.

Claims (2)

최종슬롯 상의 보드에서 출력되는 버스사용허가신호(BG0∼BG3)를 논리곱하는 게이트소자와, 상기 게이트소자의 출력에 따라 입력신호가 결정되어 시스템의 에러발생신호(SYSFAIL)와 사용중신호(BUSY)를 각각 출력하는 2개의 게이트소자로 구성된 것을 특징으로하는 컴퓨터의 버스 중재오동작 방지회로.The gate element multiplying the bus permission signals BG0 to BG3 output from the board on the last slot, and the input signal is determined according to the output of the gate element, so that the error occurrence signal SYSFAIL and the busy signal BUSY of the system are determined. A bus arbitration malfunction prevention circuit of a computer, comprising two gate elements each outputting. 제1항에 있어서, 상기 게이트소자는 낸드게이트인 것을 특징으로하는 컴퓨터의 버스 중재오동작 방지회로.2. The bus arbitration malfunction prevention circuit of claim 1, wherein the gate element is a NAND gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940000540A 1994-01-14 1994-01-14 Computer Bus Interruption Malfunction Prevention Circuit KR950024078A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940000540A KR950024078A (en) 1994-01-14 1994-01-14 Computer Bus Interruption Malfunction Prevention Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940000540A KR950024078A (en) 1994-01-14 1994-01-14 Computer Bus Interruption Malfunction Prevention Circuit

Publications (1)

Publication Number Publication Date
KR950024078A true KR950024078A (en) 1995-08-21

Family

ID=66663345

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940000540A KR950024078A (en) 1994-01-14 1994-01-14 Computer Bus Interruption Malfunction Prevention Circuit

Country Status (1)

Country Link
KR (1) KR950024078A (en)

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