KR970007627A - Malfunction prevention circuit in control system - Google Patents

Malfunction prevention circuit in control system Download PDF

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Publication number
KR970007627A
KR970007627A KR1019950021368A KR19950021368A KR970007627A KR 970007627 A KR970007627 A KR 970007627A KR 1019950021368 A KR1019950021368 A KR 1019950021368A KR 19950021368 A KR19950021368 A KR 19950021368A KR 970007627 A KR970007627 A KR 970007627A
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KR
South Korea
Prior art keywords
output
peripheral device
latch
key input
input unit
Prior art date
Application number
KR1019950021368A
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Korean (ko)
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KR100385454B1 (en
Inventor
윤정수
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019950021368A priority Critical patent/KR100385454B1/en
Publication of KR970007627A publication Critical patent/KR970007627A/en
Application granted granted Critical
Publication of KR100385454B1 publication Critical patent/KR100385454B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3041—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is an input/output interface

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

본 발명은 컨트롤 시스템의 오동작 방지회로에 관한 것으로서 특히, 본 발명에 의한 컨트롤 시스템의 오동작 방지회로는 주변장치의 동작을 제어하기 위해서 소정의 신호를 발생하는 키이 입력부; 키이 입력부의 출력을 입력하여 주변장치를 설정하고 주변장치의 동작이 수행되는 상태를 인지하여 소정의 데이타를 출력하는 마이크로 프로세서; 마이크로 프로세서에서 처리된 데이타를 저장하는 래치; 마이크로 프로세서와 래치의 메모리를 리셋시키는 리셋부; 래치와 키이 입력부의 출력을 입력하여 래치의 출력에 따라 키이 입력부의 출력을 주변장치로 전달하거나 차단하는 프로그램 로직부를 구비한 것을 특징으로 한다.The present invention relates to a malfunction prevention circuit of a control system, and in particular, a malfunction prevention circuit of a control system according to the present invention includes a key input unit for generating a predetermined signal to control an operation of a peripheral device; A microprocessor for inputting an output of the key input unit to set a peripheral device and recognizing a state in which an operation of the peripheral device is performed to output predetermined data; A latch for storing data processed by the microprocessor; A reset unit for resetting the memory of the microprocessor and the latch; And a program logic unit configured to input an output of the latch and the key input unit to transfer or block an output of the key input unit to the peripheral device according to the output of the latch.

따라서, 본 발명은 래치의 출력에 따라 키이 입력부에 입력된 외부신호를 주변장치로 전달하거나 차단함으로서 부주의로 인한 컨트롤 시스템의 오동작을 방지하는 효과를 제공한다.Therefore, the present invention provides an effect of preventing a malfunction of the control system due to inadvertent operation by transmitting or blocking an external signal input to the key input unit to the peripheral device according to the output of the latch.

Description

컨트롤 시스템에 있어서 오동작 방지회로Malfunction prevention circuit in control system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 컨트롤 시스템에 있어서 오동작 방지회로의 구성도, 제2도는 본 발명에 의한 컨트롤 시스템에 있어서 오동작 방지회로의 신호처리를 설명하기 위한 도면, 제3도는 제1도에 있어서 각부의 타이밍도.1 is a configuration diagram of a malfunction prevention circuit in a control system according to the present invention, and FIG. 2 is a view for explaining signal processing of a malfunction prevention circuit in a control system according to the present invention, and FIG. Timing diagram.

Claims (2)

외부신호에 상응하여 소정의 동작을 수행하는 주변장치를 구비한 콘트롤 시스템에 있어서, 상기 주변장치의 동작을 제어하기 위해서 외부신호를 입력하여 소정의 신호를 발생하는 키이 입력부; 상기 키이 입력부에서 출력된 신호를 입력하여 상기 주변장치를 세트 또는 리세트시키고, 상기 주변장치의 동작이 수행되는 상태를 인지하여 상기 주변장치가 임의의 동작을 수행하는지 여부에 따라 소정의 데이타를 출력하는 마이크로 프로세서; 상기 마이크로 프로세서에서 출력된 소정의 데이타를 입력하여 소정의 클럭신호와 동시시켜 출력하는 래치; 상기 마이크로 프로세서와 상기 래치의 메모리를 리셋시키는 리셋부; 및 상기 래치의 출력과 상기 키이 입력부의 출력을 입력하여 상기 래치의 출력에 따라 상기 키이 입력부에 의한 외부신호를 상기 주변장치로 전달하거나 차단하는 프로그램 로직부를 구비한 것을 특징으로 하는 컨트롤 시스템에 있어서 오동작 방지회로.A control system having a peripheral device that performs a predetermined operation in response to an external signal, comprising: a key input unit configured to input an external signal to generate a predetermined signal in order to control an operation of the peripheral device; The peripheral device is set or reset by inputting a signal output from the key input unit, and the predetermined data is output depending on whether the peripheral device performs an arbitrary operation by recognizing a state in which the operation of the peripheral device is performed. A microprocessor; A latch for inputting predetermined data output from the microprocessor and simultaneously outputting the predetermined data with a predetermined clock signal; A reset unit for resetting the memory of the microprocessor and the latch; And a program logic unit configured to input an output of the latch and an output of the key input unit to transmit or block an external signal by the key input unit to the peripheral device according to the output of the latch. Prevention circuit. 제1항에 있어서, 상기 래치에서 출력된 신호를 입력하여 상기 주변장치의 동작수행에 따라 램프를 점멸시키는 램프 구동기를 더 포함하는 것을 특징으로 하는 컨트롤 시스템에 있어서 오동작 방지회로.The control system of claim 1, further comprising a lamp driver configured to input a signal output from the latch to flash a lamp according to an operation of the peripheral device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950021368A 1995-07-20 1995-07-20 Circuit for preventing malfunction on control system KR100385454B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950021368A KR100385454B1 (en) 1995-07-20 1995-07-20 Circuit for preventing malfunction on control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950021368A KR100385454B1 (en) 1995-07-20 1995-07-20 Circuit for preventing malfunction on control system

Publications (2)

Publication Number Publication Date
KR970007627A true KR970007627A (en) 1997-02-21
KR100385454B1 KR100385454B1 (en) 2003-08-02

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