KR950008662B1 - Interrupt request selection circuit - Google Patents

Abstract

The circuit provides efficient interrupt relection, which prevents the generation of error and is compatible with the conventional system, by separately processing the interrupt request(IRQ) signal. At the start of the system operation, a CPU determines the type of the interrupt request and transmits the information to the keyboard controller(1). The circuit includes: (a) a determining circuit(11) which clears the output of determination signal according to the control signal; (b) an interface circuit(12) which controls the loading of the interrupt request signal to the interrupt controller(2) by the control signal of the keyboard controller.

Description

Interrupt request selection circuit

1 is a block diagram of a conventional interrupt request selection circuit.

2 is a block diagram of an interrupt request selection circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 15: controller 11: 8-bit latch

12: 3-state output buffer 13: register array

14: PAL J1 to J8, J11 to J19: pin header

R11 to R18: Resistor S1: Shunt

The present invention relates to an interrupt request (IRQ) selection circuit for selecting an expansion card connected to an expansion slot in a personal computer.

1 is a circuit diagram of a conventional interrupt request selection circuit.

As shown in FIG. 1 of the conventional interrupt request selection circuit, the interrupt request signal output of the controller 1 is connected to one of the pinheads, and the specific IRQ is selected from one of J1 to J8 to the shunt S1. To be connected.

In the expansion slot of a conventional personal computer, a prescribed electrical signal is used, and an interrupt request signal used for interrupt processing of a card is IRQ (Interrupt Request) 3, 4, 5, 6, 7, 8, 9, 10 There are 11 of 11, 12, 14, and 15, and four or eight of them are usually selected and one of them is connected by pin heads J1 to J8 and shunts S1.

The IBM PC provides eight expansion slots, so up to eight expansion cards can be used. Generally, expansion cards for IBM PCs are controllers for specific purposes, such as LAN controllers and modem cards for LAN cards. In this case, when the interrupt request signal is received from the expansion card by using the interrupt request signal to inform the system of the operation result of the command from the computer, the interrupt controller of the system receives the interrupt request signal and is set in advance. Run the interrupt handling routine.

However, if multiple expansion cards are used, the pinheads J1 to J8 and the shunt (S1) must be directly connected by hand in order to use the interrupt request selection signal without duplication. there was.

In addition, when the IRQ can be set only in software, there is a problem that not only the change can be made when there is no setup disk, but also the case where the initialization cannot be performed.

Accordingly, an object of the present invention is to provide an interrupt request selection circuit for enabling interrupt request selection in software, so that it can be selected in hardware or software.

In order to achieve the above object, the present invention provides a controller for outputting an interrupt request signal to inform the system of an operation result of a command from a computer, and one end of the interrupt request signal output terminal of the controller and the other end of the interrupt request. An interrupt request selection circuit comprising first to eighth pin headers connected to a terminal for outputting a signal, comprising: a PAL for outputting a clock signal by inputting a read and write signal for an address and an input / output font, and outputting the PAL; A latch for inputting a signal for changing the selection of the interrupt request signal as a clock input, an input terminal connected to the latch, and an output terminal connected to the other end of the first to eighth pin headers, and an interrupt request of the controller. It is connected to the signal output terminal and the output enable terminal of the three-state output buffer to interrupt request And the choice characterized in that further comprising: a ninth pin header for selecting to change the hardware or software.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a block diagram of an interrupt request selection circuit according to the present invention, in which 11 is a 1-bit latch, 12 is a three-state out put buffer, 13 is a register array, and 14 is a PAL (programmable array logic). Is a controller, J11 to J19 are pin headers, and R11 to R18 are resistances, respectively.

In the interrupt request selection circuit according to the present invention, as shown in FIG. 2, the three-state output buffer 2 is connected to the output terminal of the 8-bit latch 11 to which the data SD0 to SD7 of the ISA slot SLOT are input. PAL 14 for connecting the input terminal and outputting the clock signal by inputting the address A9 to A9 of the ISA data and the read / exchange signal IOWR to the clock input terminal of the 8-bit latch 11 as input. The one end of the pin header J19 to the interrupt request signal output terminal of the controller 15 which informs the system of the operation result of the instruction from the computer, and the other end of the pin header J19. The output enable terminal of the tri-state output buffer 12 is connected, and the interrupt request signal of the ISA is transmitted through one end of the pin headers J11 to J18 to the eight output terminals of the tri-state output buffer 12. From among the accepted signals IRQ 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15 The selected eight interrupt request signal output terminals are connected, the other end of the pin heads J11 to J19 is connected to the interrupt request signal output terminal of the controller 15, and a register is output to the output terminal of the interrupt request signal IRO and ground. The array 13 is connected and configured.

If a specific value is written to an input / output port added to enable the program to change the selection of the interrupt request signal, the specific value is written to the 8-bit latch 11, and the output of the 8-bit latch 11 is set to 3 When the interrupt output signal is generated from the controller 15 and the interrupt request signal is generated, the tri-state output buffer 12 becomes an output enabled state, i.e., the 8-bit latch 11. The stored contents are output through the three-state output buffer 12, and the outputs of the three-state output buffer 12 are output to eight interrupt request output terminals selected from the inputs of eleven interrupt request signals of the ISA bus. Is entered.

Accordingly, when any content is written into the 8-bit latch 11, only one of the values is written in a high state, and the controller 15 according to the interrupt request signal input signal of the ISA bus connected to the value corresponding to the bit. When another interrupt request signal is generated, another interrupt request signal is low, and the interrupt request signal written high to the 8-bit latch 11 becomes high and is interrupted by the interrupt controller of the system. It is recognized that the request signal has occurred.

The pin header J19 must be connected when the interrupt request is selected by software program. If the interrupt request is set by hardware, the pin header J19 is pulled out to select the desired interrupt request signal. One of the pinheads J11 to J18 can be used. In this case, it is impossible to select a software interrupt request by a program. That is, the hardware interrupt request selection takes precedence over the software interrupt request selection.

The register array 13 including the pull-down resistors R11 to R18 connected to each output terminal of the interrupt request signal IRQ and ground, respectively, is configured to output the tri-state because the interrupt request signal of the ISA data is active high. It functions to stabilize the signal level when the output of the buffer 12 is high impedance.

The present invention configured and operated as described above can be directly connected by a shunt in hardware or can change the selection of interrupt request in software, so that there is an application effect that can be selectively used in some cases.

Claims (2)

The controller 15 outputs an interrupt request signal to inform the operation result of the instruction from the computer, and one end is connected to the interrupt request signal output terminal of the controller 15, and the other end is output of the interrupt request signal IRQ. A first to eighth pin headers J11 to J18 connected to the terminal to be configured in the interrupt request selection circuit; Programmable Array Logic (PAL) 14 which outputs a clock signal by inputting addresses A0 to A8 and read and write signals IOWR to the input / output ports, and interrupts the output of the PAL 14 as a clock input. A three-state output buffer having an input terminal connected to the latch 11 and an output terminal connected to the other end of the first to eighth pin headers J11 to J18. 12) and an interrupt request signal output terminal of the controller 15 and an output enable terminal 0E of the tri-state output butter 12 for selecting hardware or software to change the selection of the interrupt request. And an ninth pin header (J19). The resistor array of claim 1, further comprising: a resistor array (13) comprising pull-down resistors (R11 to J18) connected to the other ends of the first to eighth pin heads J11 to J18 and stabilizing a signal level, respectively. And an interrupt request selection circuit, characterized in that.