KR960008245Y1 - Disabling circuit for chip without chinp selecting signals - Google Patents

Abstract

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Description

Circuit to disable chips without chip select signal

FIG. 1 is a block diagram of a conventional chip (SCSI control chip) logic without a chip select signal.

2 is a block diagram of a circuit for disabling a chip (SCSI control chip) without a chip select signal according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

SA19: System address of 20 bits binary number from 0 to 19

SD15: System data consisting of 16 bits binary numbers from 0 to 15

SD1 (0): System data consisting of 0 1 bits inputted from I / O port.

SA1 (17): system address of 17 1 bit

NSA1: This is an output signal of the logic sum gate 6 having SA1 17 and the enable / disable signal SCSI EN as both inputs, and is included as a system address SA19 input to the SCSI control chip.

The invention relates to a circuit for disabling a chip without a chip select signal. More specifically, a chip that is not selected as a chip select signal and that has no register for disabling the chip by software among chips that decodes an address internally. The present invention relates to a circuit for disabling a chip without a chip select circuit for disabling these chips in software.

Today, personal computers are introducing a new concept of plug and play. This concept means that when a new card or device is installed in the system, the user can redistribute resources (memory or input / output addresses) of various cards or devices in software without incurring hardware manipulation. This is a method to facilitate the user's convenience by enabling the disable.

In order to realize the above concept of 'plug and play', the control chips (input / output chips, small computer system interfaces; controllers) already mounted on the system board are software-enabled. Or be able to be disabled.

However, many chips are not software-enabled or disabled in software, making it impossible to introduce the concept of plugs and plugs. In addition, new cards that must use the resources (same address area) already in use by chips already mounted on the system board cannot be installed.

Hereinafter, a chip logic without a chip select circuit will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a chip (SCSI control chip) logic without a conventional chip select signal.

As shown in FIG. 1, the chip logic without the conventional chip select signal is a system memory read cycle for the system bus SD15 and the address bus SA19 in order to access the memory inside the SCSI control chip 1. When the signal SMEMR and the system memory write cycle signal SMEMW are inputted, the SCSI control chip 1 and the SCSI device 2 which export data via the SCSI bus to the corresponding specific SCSI device 2, And a separate ROM 4 and programmable array logic 3 for decoding the address that accesses the ROM.

The SCSI control chip 1 uses a memory area of 2K bytes for checking RAM and status therein. The address of this area is expressed in hexadecimal notation and becomes CF800 to CFFF _h . In addition, the memory used for the ROM is an area of 6K bytes whose addresses are represented by the hexadecimal numbers CE000 to CF7FFH _h .

However, since the SCSI logic, which is one of the chips without the conventional chip select signal, has no function to disable the entire logic, it is necessary to use the resources used in the SCSI logic (memory in the area where the memory address is indicated by CE000 to CFFFF _h ). There is a disadvantage that other cards can not be mounted.

Therefore, the object of the present invention is to solve the disadvantages of the prior art, and among the chips that decode the address internally without the chip select signal, there is no register necessary to disable the chip in software. It is an object of the present invention to provide a circuit for disabling a chip without a chip select signal that can disable chips that are impossible to introduce.

In order to achieve the above object, a configuration of the present invention is that when the enable / disable command code made of software is enabled, a chip without a chip select signal is driven as in the prior art, and in the case of a disable, the chip select signal A control unit for converting an enable / disable signal so that a chip without a chip is not driven, and a system address input to the chip logic as the enable / disable signal, and executing enable / disable of chip logic. And chip logic without a chip select signal whose drive is determined by the above enable / disable signal.

When described with reference to the accompanying drawings the most preferred embodiment which can easily implement this invention by the above configuration as follows.

2 is a block diagram of a circuit for disabling a chip (SCSI control chip) without a chip select signal according to an embodiment of the present invention.

As shown in FIG. 2, the circuit configuration for disabling the chip without the chip select signal according to the embodiment of the present invention is such that the flip-flop 5, which operates when the clock pulse rises, has a clock equal to the PAL 3; The control unit 30 receives the command code SD1 (0) corresponding to the enable / disable at the input / output port and outputs the enable / disable signal (SCSI EN) to the execution unit according to the pulse, and the above enable / Disable signal (SCSI EN) as one input, limiting the memory area used by the current chip logic as the upper bit of the 20-bit system address SA19 input to the SCSI control chip 1 in the chip logic. A system address into which the logic sum gate 6 which inputs one bit address (SA1 (17); address bit 17, which is the third bit from the upper part indicated by binary number) in the present embodiment is input to the chip logic. To (SA19) Execution unit 20 for outputting one bit control address NSA1 and another control if system address SA19 including one bit control address NSA1 corresponds to a memory area currently used by chip logic. Enable / disable output from the SCSI control chip 1, the SCSI device 2, and the controller 30, which receives signals SMEMR, SMEMW, and SD15, if necessary, and outputs data to the SCSI device 2; It consists of a PAL 3 and a ROM 4 whose drive is determined by the signal SCSI EN.

The action according to the embodiment of the present invention by the above configuration is as follows.

The initial operation is when the system is powered up or reset and the Clear input is logically '0' so that the output of the flip-flop (5) and the enable / disable signal (SCSI EN) are logically ' 0 '. Thus, one side input of the logical sum gate 6 of the execution unit 20 is logically '0' so that the input state of one bit of the address signal SA1 17 is output as one bit of the control address signal NSA1 as it is. do.

Operation of the disabled state is the write "1" to the logical 0 of the data one bit to the current input address (hexadecimal representation of the input and output port 20 _h) as possible. This is a software operation, and when displayed as a command, it is out 20, 01. By the above operation, an input that is logically '1' is inputted to the flip-flop 5 through the system data bus SD1 (0) input with one bit. Thus, the enable / disable signal SCSI EN output from the flip-flop 5 is logically '1'. This is the output value in the disabled state of the control unit 30.

The logic sum gate 6 of the execution unit 20 has the enable / disable signal SCSI EN of one input logically '1', regardless of one bit address [SA1 (17)], which is the other input. Always produces an output that is logically '1'.

In the SCSI control chip 1 of the chip logic 10, a system address SA19 including a one-bit control address NSA1 logically inverted in place of address 17, which is a one-bit address SA1 (17). Get input. This system address SA19 corresponds to a memory in a region other than the memory region currently used by the SCSI control chip 1. Therefore, in any case, the SCSI control chip 1 does not receive the address of the memory (area indicated by the hexadecimal addresses CE000 to CF7FF _h ) used by the SCSI control chip 1, and therefore the SCSI control chip 1 does not operate at all.

When the PAL 3, which decodes the address for accessing the separate ROM 4, outputs a system ROM chip select signal SROMCS logically '0' to the ROM 4, the corresponding address may be accessed. However, the enable / disable signal (SCSI EN), which is logically '1', prevents the system ROM chip select signal (SROMCS) output from the PAL 3 from being logically '0'. Therefore, since the ROM 4 cannot be accessed, the chip logic 10 without all the chip select signals becomes disabled.

The enable switching operation from disable logically writes a '0' to one bit of data zero at the I / O address (hexadecimal representation of the I / O port 20 _h ). This is a software operation, and when displayed as a command, it is out 20, 00. By the above operation, the logically '0' input is inputted to the flip-flop 5 through the system data bus SD1 (0) inputted with one bit. Thus, the enable / disable signal SCSI EN output from the flip-flop 5 is logically '0'. This is the output value of the controller 30.

The enable / disable signal (SCSI EN), which is one input of the OR gate 6 in the execution unit 20, is logically '0' so that the input state of one bit of the address signal [SA1 (17)] remains as it is. The bit is output as the control address signal NSA1. Therefore, the SCSI control chip 1 operates by receiving an address of a memory area used by the SCSI control chip 1.

According to this embodiment, the memory used by the SCSI control chip 1 is an area represented by the hexadecimal number of the memory addresses CE000 to CF7FF _h . If this address is expressed in binary number, it becomes 20 bits, as shown in Table 1 below.

TABLE 1

The bits common to the binary representation of the memory area of the SCSI control chip (1) in Table 1 and from the start address to the end address of this area are the bits 16 to 19 when the lowest level is designated as 0. . Among them, enable / disable signal (SCSI EN) is logically '0' and one bit address [SA1 (17)] passes through the OR gate 6 to maintain the initial logic state, and enables / disables When the enable signal (SCSI EN) is logically '1', if one bit address [SA1 (17)] passes through the OR gate 6 and has an inverted logic state from the beginning, one address SA1 is Logically it should be '1'. Referring to (Table 1) above, the 16th and 17th address bits logically correspond to this, and it is possible to use one of them as one input of the OR gate 6.

As an example of the procedure for applying this design to a real personal computer, the system bias (BIOS) first disables SCSI and checks if there is a card using an area with address address of memory CE000 to CFFFF _h . If it is present, disable SCSI, and if no card is used, enable SCSI logic so that cards with the same resources as SCSI logic can be populated.

As described above, in the embodiment of the present invention, since there is no chip select signal, there are no registers necessary for disabling the chip in software among the chips that decode the address internally. A circuit for disabling a chip without a chip select signal having an effect of disabling impossible chips in software can be provided.

Claims (3)

In the case of enabling the command code of the enable / disable made of software, the chip logic 10 without the chip select signal is driven as in the prior art, and in the case of the disable, the chip logic 10 without the chip select signal is driven. The control unit 30 converts the enable / disable signal (SCSI EN) so as not to be activated, and the system address inputted to the chip logic 10 without the chip select signal as the enable / disable signal (SCSI EN). SA19), the execution unit 20 which executes enable / disable of the chip logic 10 without the chip select signal, and a chip whose driving is determined by the above enable / disable signal (SCSI EN). A circuit for disabling a chip without a chip select signal, characterized by consisting of chip logic (10) without a select signal. The flip-flop 5, which operates when the clock pulse rises, receives a command code SD1 (0) corresponding to the enable / disable at the input / output port. A circuit for disabling a chip without a chip select signal, characterized by outputting an enable / disable signal (SCSI EN) to an execution unit. 4. The execution unit 20 according to claim 1, wherein the execution unit 20 uses the enable / disable signal (SCSI EN) as one side input, and among the 20-bit system address SA19 input to the SCSI control chip 1 in the chip logic. On the other side, one bit of an addresser (SA1 (17); address bit 17, which is the third bit from the upper side shown in binary), which can limit the memory area used by the current chip logic as the upper bit. A circuit for disabling a chip without a chip select signal, characterized in that a logic sum gate (6) serving as an input outputs one bit of a control address (NSA1) included in a system address (SA19) input to the chip logic.