KR940003246A - Packet Assembly and Disassembly Controller of Electronic Switching System - Google Patents

Packet Assembly and Disassembly Controller of Electronic Switching System Download PDF

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Publication number
KR940003246A
KR940003246A KR1019920006819A KR920006819A KR940003246A KR 940003246 A KR940003246 A KR 940003246A KR 1019920006819 A KR1019920006819 A KR 1019920006819A KR 920006819 A KR920006819 A KR 920006819A KR 940003246 A KR940003246 A KR 940003246A
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KR
South Korea
Prior art keywords
packet
information
matching means
packetized
bus
Prior art date
Application number
KR1019920006819A
Other languages
Korean (ko)
Other versions
KR950005644B1 (en
Inventor
홍현하
박천관
신우호
한치문
Original Assignee
양승택
재단법인한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 양승택, 재단법인한국전자통신연구소 filed Critical 양승택
Priority to KR1019920006819A priority Critical patent/KR950005644B1/en
Publication of KR940003246A publication Critical patent/KR940003246A/en
Application granted granted Critical
Publication of KR950005644B1 publication Critical patent/KR950005644B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H04L69/166—IP fragmentation; TCP segmentation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9057—Arrangements for supporting packet reassembly or resequencing

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

본 발명은 전전자 교환기내의 패킷 교환 장치에 구현되는 패킷 조립/분해 제어기에 관한 것이다.The present invention relates to a packet assembly / disassembly controller implemented in a packet switching device in an electronic switchboard.

본 발명은 공중 전화망과 종합 정보 통신망의 연동시 공중전화망에 수용된 비동기 단말 가입자에게 효율적이고 경제적인 패킷 서비스를 제공할 수 있으며, 종합 정보 통신망과 기존 망과의 연동시 그에 상응한 기술을 제공할 수 있는 효과가 있다.The present invention can provide an efficient and economical packet service to an asynchronous terminal subscriber accommodated in a public telephone network when interworking a public telephone network and a comprehensive information communication network, and can provide a corresponding technology when interworking a comprehensive information communication network and an existing network. It has an effect.

Description

전전자 교환기의 패킷 조립 및 분해 제어기Packet Assembly and Disassembly Controller of Electronic Switching System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 패킷 교환 장치 구성도.1 is a block diagram of a packet switching device.

제2도는 패킷 조립 및 분해 장치 구성도.2 is a block diagram of a packet assembly and disassembly apparatus.

제3도는 본 발명의 패킷 조립 및 분해 제어기 구성도.3 is a block diagram of a packet assembly and disassembly controller of the present invention.

제4도는 본 발명의 제어부의 흐름도4 is a flowchart of a controller of the present invention.

Claims (2)

패킷호 제어 장치(1), 패킷 버스 장치(2), 패킷 처리 장치(3), 및 패킷 조립/분해장치(4)를 구비한 패킷 교환 장치의 상기 패킷 조립/분해 장치(4)에 적용되는 패킷 조립/분해 제어기에 있어서, 속도 정합 및 다중/역다중화 제어기(6)에서 가입자 정보를 입력받아 각종 정보를 포함한 헤더를 완전 패킷화한 정보로 변환하여 인터페이스 하고, 패킷 버스 장치(2)로부터의 패킷정보는 상기 속도 정합 및 다중/역다중화 제어기(6)로 인터페이스 하는 HDLC 정합 수단(7)와, 상기 완전 패킷화한 정보를 패킷 버스 장치(2)로 전송하고 패킷 버스 장치(2)로부터 입력되는 패킷 정보를 입력받아 순수 패킷정보로 변환하여 인터페이스 하는 패킷 버스 정합 수단(10)과, 상기 HDLC 정합 수단(7)과, 상기 패킷 버스 정합 수단(2)에 연결되어 인터페이스되는 완전 패킷정보와 순수 패킷정보를 저장하는 공통 메모리(8)와, 상기 HDLC 정합 수단(7), 상기 패킷 버스 정합 수단(2), 그리고 상기 공통 메모리(8)에 연결되어 입출력되는 패킷정보의 완전 패킷화와 순수 패킷화를 제어하도록 마이크로 프로세서와 제어 프로그램으로 구성된 제어수단(9)을 구비한 것을 특징으로 하는 패킷 조립/분해 제어기.Applied to the packet assembling / decomposing apparatus 4 of the packet switching apparatus equipped with the packet call control apparatus 1, the packet bus apparatus 2, the packet processing apparatus 3, and the packet assembling / decomposing apparatus 4 In the packet assembly / decomposition controller, the speed matching and multiplex / demultiplexing controller 6 receives subscriber information, converts the header including various information into fully packetized information, and interfaces with it. The packet information is transmitted to the packet bus device 2 by the HDLC matching means 7 interfaced to the speed matching and multiplexing / demultiplexing controller 6, and the complete packetized information to the packet bus device 2, and inputted from the packet bus device 2; Complete packet information and pure interface connected to the packet bus matching means 10, the HDLC matching means 7, and the packet bus matching means 2 for interfacing the received packet information into the pure packet information. Packet The common memory 8 for storing the data, the HDLC matching means 7, the packet bus matching means 2, and the packet information connected to the common memory 8 are completely packetized and purely packetized. And a control means (9) consisting of a microprocessor and a control program for controlling. 제1항에 있어서, 상기 패킷 버스 정합 수단(2)은 전송의 신뢰성을 높이기 위해 이중화로 구성된 것을 특징으로 하는 패킷 조립/분해 제어기.2. A packet assembly / decomposition controller according to claim 1, wherein said packet bus matching means (2) is configured in redundancy in order to increase transmission reliability. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920006819A 1992-04-22 1992-04-22 Packet assembling and disassembling controller of full electronic switching system KR950005644B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920006819A KR950005644B1 (en) 1992-04-22 1992-04-22 Packet assembling and disassembling controller of full electronic switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920006819A KR950005644B1 (en) 1992-04-22 1992-04-22 Packet assembling and disassembling controller of full electronic switching system

Publications (2)

Publication Number Publication Date
KR940003246A true KR940003246A (en) 1994-02-21
KR950005644B1 KR950005644B1 (en) 1995-05-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180119956A (en) * 2017-04-26 2018-11-05 현대자동차주식회사 Method for manufacturing a pressure vessel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180119956A (en) * 2017-04-26 2018-11-05 현대자동차주식회사 Method for manufacturing a pressure vessel

Also Published As

Publication number Publication date
KR950005644B1 (en) 1995-05-27

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