KR930008177B1 - Picture image processing apparatus - Google Patents

Abstract

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Description

Image processing device

1A to 1E are schematic diagrams schematically showing various graphic processings by PDI codes.

2 is a block diagram of an embodiment in which the image encoding apparatus according to the present invention is applied to an input data processing apparatus of a digital image transmission system.

3 is a flowchart showing an image processing procedure in the above embodiment.

4 is a flowchart showing a color processing procedure in the embodiment.

FIG. 5 is a schematic diagram showing an arrangement of processing target pixels for explaining the operation of the information amount reduction processing in the embodiment. FIG.

6 is a block diagram showing a configuration of an example of an economic detection circuit of an image in the embodiment.

7 is a time-chart for explaining the operation of the detection circuit.

8 is a schematic diagram showing an arrangement of pixels to be bounded.

9 is a schematic diagram showing the direction in which the boundary of an image continues with respect to the boundary detection target pixel and the contents of the image data of each pixel.

10 is a schematic diagram showing an operation principle of detection direction determination in the initial detection operation of the boundary.

11A to 11H are schematic views showing various contents and detection directions of image data of each pixel in the case of sequentially determining the direction in which the boundary is continuous.

12 is a block diagram showing the configuration of a boundary line processing circuit.

13 is a block diagram showing the configuration of an area processing circuit.

14 is a time-chart diagram for explaining the operation of the area processing circuit.

15 is a schematic diagram showing a color processing target area.

16 is a block diagram showing the configuration of a start address detection circuit.

17A and 17B are schematic diagrams showing respective processing target regions for explaining the operation of the start address detection circuit.

18 is a schematic diagram showing a processing target area having another area therein.

Fig. 19 is a block diagram showing the configuration of a discriminating circuit for discriminating the boundary between the other area and the processing target area.

20 is a diagram showing a color specification processing target image area in the encoding process of the embodiment.

21 is a diagram showing each example of a configuration pattern.

FIG. 22 is a diagram showing a state in which color is designated with each texture pattern shown in FIGS. 7A to 7H with respect to the image area shown in FIG. 20;

FIG. 23 is a diagram showing the principle of color specification operation in the case of converting color data of three levels to color data of two levels; FIG.

Fig. 24 is a diagram showing an example of a configuration pattern used when color specification of 27 colors is performed in accordance with the color specification operation principle.

* Explanation of symbols for main parts of the drawings

41, 42, 43, 44: frame memory 90: auxiliary memory

100: microcomputer 200: high speed operation processing circuit

201: timing counter 202: offset

203: data adder 204: timing gate

205: 3 state interface circuit 210: image memory

211, 212: data selector 213, 223, 223A, 223B, 250: latch circuit

214, 224 data comparator 215 address counter

220: shift register 221: data gate

222 mask gate 228 flip-flop

230: data comparison circuit

For example, the present invention treats a single color image as a set of geometric figure areas, converts the color image information into geometric command data, and transmits various image information using a telephone circuit or a wireless circuit. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus used for a digital image transmission system such as telest, and more particularly, to an area processing apparatus for an image in which each figure region is arbitrarily designated and painted in an arbitrary color.

In recent years, the development and practical use of digital image information transmission systems such as videotex and teletext as so-called new media for transmitting various image information with the development of the information society have been progressed in various countries. It is becoming. For example, in the UK, a Captain: Charactor And Pattern Telephone Access Information Network System (PRESTEL) has been developed and, moreover, North American Presentation in France, Teletel, Canada, and the United States. Level Protocol Syntax) has been put to practical use.

By the way, a single image employed in the NAPLPS is treated as a set of geometric figure regions, and the image information is represented as geometric command data by PDI (Picture Description Instruction) code, and the image information is mapped to mosaic pixels. Compared with the other system represented by the character code, the efficiency is extremely high and the high efficiency is evaluated. The PDI code includes five types of instruction data [POINT], [LINE], [AFC], [RECTANGLE], [POLYGON], and instruction data for dot-compatible graphics instruction [ BIT] and color or color gradation, and the like, and command data [CONTROL] for controlling the mode of the drawing command are defined. As the command data [POINT], as shown in FIG. 1A, a drawing start point is set at an arbitrary coordinate position in the display screen, or a point Po is plotted. As shown in the figure, a line segment connecting two points P ₁ and P ₂ is drawn. Furthermore, as the command data [AFC], as shown in FIG. 1C, an arc is drawn based on the coordinates of three points P ₁ , P ₂ , and P ₃ , and the two points as indicated by a dashed line in the figure. A string connecting the P ₁ and P ₃ is drawn to fill the contour seamlessly. In addition, the command [RECTANGLE] draws a rectangular outline with two points P ₁ and P ₂ as diagonal vertices as shown in FIG. 1D, and paints all of the outlines seamlessly. Further, as the command [POLYGON], vertices P ₁ , P ₃ ,... , The contour of the polygon defined by P _n and the inside of the contour are filled in seamlessly.

However, in the digital image information transmission system using the geometric command data as described above, it is possible to reduce the amount of information of the image information actually transmitted in a large amount, so that highly efficient information transmission can be performed. There is a problem that a lot of effort and time are required for the work for creating the geometric command data showing the image.

For example, the operation of converting a video signal captured from an image to be transmitted into the geometric command data is performed by the operator using a tablet while viewing the target image on a monitor television receiver. After inputting (color hue and gradation inforamation), etc., various modifications are applied to convert the geometric command data into geometric command data. However, it is difficult to accurately represent the information of the original image, and it takes a lot of time to input various information. It requires labor and labor.

Therefore, in view of the above-described problems, the present invention designates an arbitrary image region and processes the image region so that the data processing for substituting the image data of the region with another arbitrary image data can be efficiently performed within a short time. It is an object of the present invention to provide an apparatus and to facilitate creation of transmission data and the like in the digital image transmission system as described above.

In order to achieve the above object, the image area processing apparatus according to the present invention stores the input image data in the image storage means, and the image area displayed in the same image data with respect to the image data read out from the image storage means. The boundary line is tracked by the boundary detecting means for the designated image area, and the boundary data is stored in the storage means, and the image data corresponding to the boundary of the designated image area represented by the boundary data is replaced with other image data which is arbitrarily designated. Image data is sequentially read out from the storage means for each scanning lime, and window pulses corresponding to the designated image area are formed for each scanning line in accordance with the image data and the boundary data, and the designated image is made according to the window pulses. Image data in the area Is replaced by the other image data specified above.

EMBODIMENT OF THE INVENTION Hereinafter, one Example of the area processing apparatus of the image which concerns on this invention is demonstrated, referring drawings.

2 to 24 show the present invention applied to an input data processing apparatus in a teledon type digital image information transmission system. The apparatus of this embodiment does not show a color image to be transmitted. An RGB color signal obtained by imaging with a color video camera or a color television signal of a standard television system (for example, NTSC) is used as an input, and a color image for one frame shown by this input is treated as a set of geometric figure areas. The geometric command data showing the color image is formed in the microcomputer 100 and output through the data bus.

In the block diagram of FIG. 2 showing the overall configuration of the apparatus of the present embodiment, for example, an NTSC system color television signal is connected to the NTSC / RGB converter 5 and the synchronous separation circuit via the first signal input terminal 1. The RGB color signal is supplied to the input selection circuit 10 via the second signal input terminal 2.

The input selection circuit 10 is provided from the RGB color signal converted from the color television signal supplied from the first signal input terminal 1 via the NTSC / RGB converter 5 or from the second signal input terminal 2. The RGB color signal to be supplied is selected, and one RGB color signal is supplied to the analog / digital (A / D) converter 20.

In addition, the synchronous separation circuit 6 separates the synchronous signal among the color television signals supplied from the first signal input terminal 1 and supplies the synchronous signal to the synchronous switching circuit 5. The synchronous switching circuit 5 is supplied with a synchronous signal corresponding to the RGB color signal supplied to the second signal input terminal 2 from the third signal input terminal 3, and is connected to the input selection circuit 10. A synchronizing selection operation is performed to supply a synchronization signal corresponding to the RGB color signal supplied to the A / D converter 20 to the address data generation block 30. The address data generation block 30 is constituted of the counter circuit 32 by counting the oscillation output pulse of the PLL generator 31 and synchronized with the synchronization signal by counting the PLL generator 31 and the counter circuit 32. Address data is formed, and the address data is supplied to the selection circuit 35.

The address selection circuit 35 selects address data supplied via the address bus of the computer 100 and address data supplied from the address data generation block 30 to form first to fourth frame memories 41 and 42. 43, 44) The address data is supplied to a cursor memory 45 and a character generator 46. In addition, the frame memories 41, 42, 43, 44, the cursor memory 45, and the character generator 46 are configured to exchange various data via the data bus of the computer 100.

The first frame memory 41 is a memory for storing original data, and digitalizes an RGB color signal in the A / D converter 20, and the input color image data is transferred from the address data generation block 30. The data is written for each color of RGB on the basis of the address data. The input color image data stored in the first frame memory 41 can be arbitrarily read at any time, converted into an analog RGB color signal by the digital / analog (D / A) converter 61, and the first output selection circuit 71. It is possible to monitor the color original image by supplying it to the first RGB monitor device 81 via.

The second to fourth frame memories 42, 43, and 44 are used for processing various data such as color processing and redundant data reduction processing on the original data stored in the first frame memory 41. As used as a general purpose memory, various image data in various processing steps described later are written / read out via the data bus. The image data after completion of the data processing stored in the second frame memory 42 is converted into color data in the color table memory 52 and returned to the analog RGB color signal via the D / A converter 63 to be converted into the first and second images. It is supplied to the two output selection circuits 71 and 72, and the color image after data processing completion can be monitored by the 1st or 2nd RGB monitor apparatuses 81 and 82. FIG. Further, the image data after completion of the data processing stored in the third frame memory 43 is converted into color data in the color table memory 53, and returned to the analog RGB color signal via the D / A converter 64 to the above-mentioned first. It supplies from the 2nd output selection circuit 72 to the 2nd RGB monitor apparatus 82, and can monitor the color image after data processing fee. Further, the fourth frame memory 44 returns the original data stored in the first frame memory 41 to the analog RGB color signal by the D / A converter 61 and then to the RG / Y converter 68. The black-and-white image data of the original image obtained by converting into a luminance Y signal, and digitalizing via the A / D converter 69 is written. The black-and-white image data after the redundancy data reduction process etc. with respect to this black-and-white image data are returned to an analog RGB color signal through the color table memory 53 and the D / A converter 63, and are supplied to the signal synthesis circuit 70. It is supposed to be.

The cursor display signal is supplied from the cursor memory 45 to the signal synthesizing circuit 70, and the character data for displaying various control commands of the system is supplied from the character generator 46 to the analog RGB in the color table memory 53. The image is converted into a color signal and supplied, and the image is stored in the fourth frame memory 44 and the cursor image is generated by the cursor display signal from the cursor memory 45 and the character generator 46. RGB color signals obtained by combining the image data by the character data are synthesized and output. The image by the RGB color signal obtained by this signal synthesizing circuit 70 can be monitored by the second RGB monitor device 82 and the RGB color signal is converted into the luminance Y signal by the RGB / Y converter 80. The monitor can be monitored by the monochrome monitor device 83.

In addition, in the present embodiment, the computer 100 acts as a controller for controlling the operation of the entire apparatus, and the data bus and the address bus have an auxiliary memory 90 such as a ROM or a RAM and a flippy disk controller ( flopy disk controller 91, an input / output interface circuit 93, a high speed arithmetic processing circuit 200, and the like are connected. The input / output interface circuit 93 is also connected to a tablet 94 and a monitor device 94 for inputting various data during manual editing processing.

The apparatus of this embodiment performs image processing in the order as shown in the flowchart of Fig. 3, and inputs the input color image data supplied to the first frame memory 41 via the A / D converter 20. It is converted to geometry command data and output through the data bus.

That is, the input color image data is first written into the first frame memory 41, and stored as original data. The input color image data can be selected from either an NTSC color television signal or an RGB color signal by switching the input selection circuit 10 and the synchronization switching circuit 15. Also, the original data stored in the first frame memory 41 is converted into black and white image data by the RGB / Y converter 68 and stored in the fourth frame memory 44 as well.

Next, on the basis of the image data stored in the first and fourth frame memories 41 and 44, color processing of the input color image data is performed, and redundancy data is processed to reduce the characteristics of the original image. Automatically forms image data suitable for conversion into geometric command data without loss.

After each of the above processes, a conversion process for converting the image data into geometric command data is automatically performed.

In addition, in the case of artificially modifying and transmitting the original image, manual editing processing is performed before the geometric command data conversion processing.

In the color processing, the high frequency n high frequency is automatically selected among the original color images shown in the input color image data stored in the first frame memory 41, and each pixel is assigned either one of the n colors. Processing is performed in the order of the flowchart shown in FIG.

The color processing first generates a histogram of the respective color data with respect to the input color image data stored in the first frame memory 41 by the high speed arithmetic processing circuit 200. Select the top n color data. Next, for each image region displayed at the same luminance of the monochrome image displayed in the monochrome image data stored in the fourth frame memory 44, the color of n color closest to the color of the original color image is allocated. Color table data in order of luminance is formed, and the color table data is corrected so that the deviation is minimized in each cycle. In this way, the color table data formed by the high speed arithmetic processing circuit 200 is stored in each color table memory 51, 52, 53. The second frame memory 42 writes image data after the color processing of the n-colors allocated to the respective image regions is completed.

The color image subjected to the color processing uses the image data stored in the second frame memory 42 as address data, and reads each color data from the first color table memory 41 so as to first or second RGB. The monitor apparatuses 81 and 82 are monitored.

In the redundant data reduction process, for each image data stored in the second and fourth frame memories 42 and 44, a noise removing process, an intermediate tone removal processing, and a small area are performed. A deletion process or the like is performed to remove redundant data that is unnecessary for the next geometric instruction data conversion process to reduce the amount of information.

This reduction processing is performed in the high speed arithmetic processing circuit 200. For example, as shown in FIG. 5, three pixels of nine pixels [A], [B], [C], [D], [E], [F], [G], and [H] In [I], when three or more of four neighboring pixels [B], [D], [F], and [H] have the same data as the center pixel [E], the center pixel [E] The noise removal process is performed by substituting the data of. Further, with respect to the center pixel [E], two or more of each pixel name [A · E · I] [B · E · H], [C · E · G] [D · E · F] are monotonic If it is an increase or decrease in monotonic tone, the intermediate tone removal processing is performed by replacing the data of the center pixel [E] with a value closest to 8 in the vicinity of the center pixel [E] as an intermediate tone pixel. Again, the small area deletion processing is performed by combining small areas of less than or equal to the designated area with adjacent areas. Thus, the image data subjected to the redundancy data removal process in the high speed arithmetic processing circuit 200 is input to the third frame memory 43, and passes through the second color table memory 52 to the second RGB monitor. Monitored at device 82.

Here, the boundary of the configuration as shown in FIG. 6, which is mounted in the high speed arithmetic processing circuit 200, for the determination of the processing target image region to be subjected to the color processing and the information amount reduction processing as described above. The detection circuit is used.

신호가 공급되고 있다.6, image data for one frame of n bits per pixel of an image to be processed by this apparatus is pre-written in the image memory 210. In FIG. The image memory 210 is composed of randomly accessible RAM of any size. In addition, in the address line of the image memory 210, the offset data read from the offset ROM 202 addressed to the count output of the timing counter 201, which counts the colog pulses supplied from the microcomputer 100, and the microcomputer. The address data obtained by adding the center address data supplied from the computer 100 by the adder 203 is supplied. In addition, the write / read control line of the image memory 210 is obtained by decoding the output of the timing counter 210 with the timing gate 204.

The signal is being supplied.

, [①], …, [⑦], [⑧],

이 기입되어 있다. 상기 오프셋 데이타

, [①], [②], …, [⑦], [⑧],

은 제 8 도에 도시한 3행 3열의 9화소

, ①, ②, …, ⑦, ⑧에 대응하고 있다. 또, 상기 타이밍 게이트(204)는 상기 계수 출력[0], [1],…, [9]를 디코드함으로써, 계수 출력[0]으로부터 계수 출력[8]의 기간중에는 논리「1」로 기입 시간 T_R을 표시하는 계수 출력[9]의 기간중에서는 논리「0」으로 판독기간 T_WR을 표시하는

신호를 형성한다. 그리고, 상기 가산기 (203)는 상기 센터 어드레스 데이타와 상기 오프셋 데이타를 가산함으로써, 상기 센터 어드레스 데이타로 지정되는 검출 대상 화소를 중심 화소 ⑧로 하여, 그 8근방 화소

, ①,…, ⑦ 및 상기 중심 화소 ⑧의 각 화상 데이타를 1사이클 기간중에 순차로 지정하는 어드레스 데이타를 형성한다.Here, the timing counter 201 counts the clock pulses as shown in the time chart of FIG. 7 to output decimal counts [0], [1],... , [9] is supplied to the offset ROM 202 and the timing gate 204. The offset ROM 202 further includes the count outputs [0], [1],... , Offset data at the address specified by [9]

, [①],… , [⑦], [⑧],

Is written. The offset data

, [①], [②],… , [⑦], [⑧],

9 pixels in 3 rows 3 columns shown in FIG.

, ①, ②,… , ⑦, ⑧. The timing gate 204 is provided with the coefficient outputs [0], [1],... , Decoding period [9] to logic "0" in the period of coefficient output [9] indicating the writing time T _R in logic "1" during the period of coefficient output [0] to coefficient output [8]. To display T _WR

Form a signal. Then, the adder 203 adds the center address data and the offset data to make the detection target pixel designated in the center address data as the center pixel ⑧, and the eight neighboring pixels.

, ①,… And address data for sequentially specifying each image data of the?,?, And the center pixel? In one cycle period.

, ①, …, ⑧의 각 화상 데이타를 일차적으로 기억한다.The image data sequentially read from the image memory 210 is supplied to the n-bit 9-stage shift register 220 through the data line. The shift register 220 sequentially transfers the image data in accordance with the clock pulse, and executes nine pixels of the three rows and three columns.

, ①,… , Each image data of (8) is stored first.

, ①, …, ⑦의 각 화상 데이타를 비교된다. 상기 데이타 비교 회로 (230)는 각각 n비트의 8개의 비교기(231, 232, …, 238)로 이루어지며, 각 화상 데이타의 일치 출력 데이타를 방향 ROM(24)에 판독 어드레스 데이타로서 공급한다.Each image data temporarily stored in the shift register 220 is supplied to the data comparison circuit 230, so that the image data of the center pixel (8), i.

, ①,… , And image data of 7 are compared. The data comparison circuit 230 is composed of eight comparators 231, 232, ..., 238 of n bits each, and supplies the coincidence output data of each image data to the direction ROM 24 as read address data.

신호가 랫치 클록으로서 공급되고 있으며, 이

신호의 하강 타이밍, 즉 상기 시프트 레지스터(220)에 각 화소

, ①, …, ⑧ 모두의 화상 데이타를 일시 기억한 상태의 타이밍에서 상기 방향 데이타를 랫치하도록 되어 있다. 또, 이 랫치 회로(250)를 거쳐 출력되는 경계 검출 출력, 즉 방향 데이타는 상기 방향 ROM(24)에 어드레스 데이타로서 공급되어 있다.In the direction ROM 240, direction data indicating a direction in which the boundary of the image is continuous is written in advance, and the direction data is read out as the boundary detection output via the latch circuit 250. The latch circuit 250 from the timing gate 204

The signal is being supplied as a latch clock, which

The timing of the signal falling, i.e. each pixel in the shift register 220

, ①,… The direction data is latched at the timing of the state in which all of the image data (8) and (8) are temporarily stored. The boundary detection output, i.e., direction data, output through the latch circuit 250 is supplied to the direction ROM 24 as address data.

, ①, …, ⑦로 표시되는 화상 경계가 연속하는 방향은 상기 중심화소⑧를 검출 대상 화소로 한 경우에, 제 9 도에 도시한 8종류의 방향 데이타 D₀[→], D₁[ ], D₂[↑], …, D₇[ ]로 일의적으로 결정할 수가 있고 중심 화소 ⑧에 대해 화상의 경계가 연속하고 있음을 예를들면 8근방 화소

, ①, …, ⑦에 대하여 D₀, D₁, …, D₇은 각 요소

, ①, …, ⑧의 화소의 화상 데이타가 제 9 도에 도시한 바와같은 상태에 있음을 조건으로서, 다른 5개의 화소의 화상 데이타 Δ의 내용에 의하여 결정된다. 환언하면, 각 방향 데이타 D₀, D₁, …, D₇에 대하여 4개의 화소 데이타는 일의적으로 결정된다. 한편, 제 9 도에 있어서, 0표는 화상 데이타가 일치되고 있음을 나타내고, X표는 화상 데이타가 불일치하고 있음을 나타내고 있다.Here, the center pixel ⑧ and its eight neighboring pixels

, ①,… , The direction in which the image boundary indicated by ⑦ is continuous includes the eight kinds of direction data D ₀ [→], D ₁ [], D ₂ [shown in FIG. ↑],… , D ₇ [] to be determined uniquely by, for example, and that the boundary of the image, and continuous with respect to the center pixel ⑧ 8 neighboring pixel

, ①,… , D ₀ , D ₁ ,. , D ₇ is each element

, ①,… On the condition that the image data of the pixels 8 and 8 are in the state as shown in FIG. 9, the content of the image data Δ of the other five pixels is determined. In other words, each direction data D ₀ , D ₁ ,. For D ₇ , four pixel data are uniquely determined. In FIG. 9, the 0 mark indicates that the image data matches, and the X mark indicates that the image data does not match.

, ①, …, ⑦의 각 화소 데이타의 일치, 불일치 상태로부터 방향 데이타를 일의적으로 결정할 수 있다.If the continuous boundary of the image is sequentially tracked in the counterclockwise direction, the direction data obtained by the previous detection operation and the pixel 8 to be detected relative to the detection target pixel at the present time, that is, the center pixel (8).

, ①,… The direction data can be uniquely determined from the coincidence and inconsistency of the pixel data of?

, ①, ②의 화상 데이타 Δ의 내용에 의해 제 10 도에 도시한 바와같이 일의적으로 결정할 수 있다.That is, first of all, in determining the first detection target pixel of the image area for performing boundary detection, image data is searched from the lower left side of the image, and among the at least eight neighboring pixels as shown in FIG. The four pixels ④, ⑤, ⑥, and ⑦ may all detect a detection target pixel that is in an inconsistent state with respect to the center pixel ⑧. The direction detection output for the first detection target pixel is any one of three types of D ₀ [→], D ₁ [], D ₂ [↑], and each pixel

Can be determined uniquely as shown in FIG. 10 by the contents of the image data?

In the state where the boundary is traced and the direction is detected, a match or inconsistency of three pixels among the eight neighboring pixels has already been determined with respect to the center pixel? Determined by the previous detection operation, and the image data? Thus, as shown in FIGS. 11A to 11H, the direction detection output is uniquely determined by the position of the previous detection target pixel. On the other hand, in Figs. 11A to 11H, the? Marks indicate the detection target pixels during the previous detection operation, and the non-display indicates that any of the mismatches is good.

, ①, …, ⑦의 각 화상 데이타의 일치 검출 출력 데이타와 이전의 경계 검출 출력, 즉 방향 데이타에 의하여 일의적으로 결정된 방향 데이타 D₀, D₁, …, D₇이 미리 기입되어 있으며, 상기 일치 검출 출력 데이타와 방향 데이타를 판독 어드레스로서, 상기 방향 데이타 D₀, D₁, …, D₇가 경계 검출 출력으로서 판독된다.The direction ROM 240 includes eight neighboring pixels with respect to the center pixel ⑧ as described above.

, ①,… , Direction data D ₀ , D ₁ ,... Which are uniquely determined by the coincidence detection output data of each image data of?,? , D ₇ is written in advance, and the direction detection data D ₀ , D ₁ ,... , D ₇ is read as the boundary detection output.

As in the present embodiment, when the edge detection output is obtained by reading the direction data previously written in the direction ROM 240 into the output data of the comparison circuit 230, the processing time of about several tens of microseconds is achieved in a conventional 16-bit microcomputer. The boundary detection process of an image required can be performed in a very short time of about 1 to 3 s.

신호가 논리 「0」즉 기입 기간 T_WR중에 상기 스테이트 인터페이스 회로 (205)를 인에이블 상태로 제어함으로써, 경계 검출 레벨을 임의로 변경할 수 있도록 되어 있다.On the other hand, in this boundary detection circuit, detection level data is input to a data line via the three-state interface circuit 205, and

By controlling the state interface circuit 205 to the enabled state during the logic "0", that is, the write period T _WR , the boundary detection level can be arbitrarily changed.

Then, after the color processing and information amount reduction processing as described above are automatically performed, when further correction is made to the original image, a color image displayed by the image data obtained by automatically performing the color processing and reduction processing described above is newly added. Manual editing is performed to artificially add or delete motifs, correct colors, and the like.

The said material editing process is performed using the transparent tablet 94 provided on the screen of the black-and-white monitor apparatus 83 which monitors the image by the black image data stored in the said 4th frame memory 44. As shown in FIG. On the screen of the monochrome monitor device 83, a character information image for displaying various control commands necessary for manual editing is given by the character generator 46, and for cursor display indicating position information generated from the tablet 94. A cursor image is provided in the cursor memory 45, and when an operator corrects the image using a fan attached to the tablet 94, the effect is displayed in real time.

Here, the area processing apparatus according to the present invention is used when the manual editing process changes the color of an arbitrary image area, for example.

This area processing apparatus is mounted on the high speed arithmetic processing circuit 200, and uses a boundary line processing circuit having a configuration as shown in FIG. 12 using the above-described edge detection circuit, and an area after boundary line processing by the boundary line processing circuit. It consists of an area processing circuit having a configuration as shown in FIG. 13 which performs processing.

The boundary line processing circuit shown in FIG. 12 is a start indicating the position on the boundary line of the processing target region as data for designating the processing target region from the mitrocomputer 100 in the data adder 203 in the above-described boundary detecting circuit. Address data is supplied through the first data selector 211, and image data specifying a new color of the processing target area is supplied to the three-state interface circuit 205.

Furthermore, in this boundary line processing circuit, the coefficient output of the timing counter 201 and the latch output by the latch circuit 250, that is, the direction data, as the shift register input of the offset ROM 202, cause the second data selector 212 to operate. The start address data supplied from the microcomputer 100 and the addition output data by the adder 203 are supplied to the latch circuit 213 as center address data supplied through the same and supplied to the adder 203. The latched latch output data is supplied through the first data selector 211. The start address data provided to the microcomputer 100 and the latch output data by the latch circuit 213 are compared in the data comparator 214.

The second data selector 212 is a direction data output from the direction ROM 240 through the latch circuit 250 during the above-described write period T _WR by the timing gate 212. The operation is controlled to address. The first data selector 211 latches the addition output data of the microcomputer 03 except for a period in which the start address data supplied from the microcomputer 100 is handled by the data adder 203. Operation is controlled to return the latch output data of 213 to the adder 203. FIG.

In the boundary processing circuit of the above-described configuration, when the start address data and the image data specifying the processing target region and the new color are supplied from the microcomputer 100, the image designated by the start address data is first centered. The edge data and the start address data obtained by addressing the offset ROM 204 sequentially as latch output data, namely boundary detection data, which are output from the direction ROM 240 through the latch circuit 250 as a boundary detection data. By adding to the adder 203, the center address data is obtained in the next detection operation, and the center address data is latched by the latch circuit 213. Then, by performing a boundary detection operation on the center pixel designated by the center address data latched by the latch circuit 213, the image data corresponding to each center pixel is sequentially tracked while tracking the boundary line of the processing target region. Replace with the new image data. The tracking operation of the border line is repeated until the start address data provided by the data comparator 203 and the center address data latched by the latch circuit 213 coincide with each other, and the border line processing ends at the matching point. .

When the boundary line processing is completed, the microcomputer 100 receives the coincidence output from the data comparator 214 to indicate the end of the boundary line processing, and the connection state in the high speed arithmetic processing circuit 200 is shown in FIG. Switch to the area processing circuit shown.

In this area processing circuit, an address counter 215 is connected to the address line of the image memory 210 in which the image data of the boundary line is converted into image data of a new color by the above-described boundary line processing, and by this address counter 215 All addresses are sequentially accessed, and image data read from the image memory 210 is supplied to the data gate 221 and the microphone gate 222 via data lines.

The address counter 215 forms the address data by counting a time clock obtained by dividing the access clock 1/2 by the timing counter 210. The timing clock obtained by the timing counter 201 is supplied as a control pulse to the three-state interface circuit 205 through the NAND gate 229, and at the same time, the write / read control (R / WR) is performed in the image memory 210. Is supplied as a signal.

The data gate 221 supplies the image data read from the image memory 210 to the data comparator 224 through the latch circuit 223. The data comparator 224 is provided with image data indicating a color of a color processing target area from the microcomputer 100, and data read from the image memory 210 and image data provided from the microphone computer 100. Is compared to determine whether or not it is in the processing target area, and supplies a coincidence output, for example, as shown in FIG. 14 to the NAND gate 229 via the switch 225, indicating that it is in the processing target area. At the same time, the coincidence output is supplied to the first AND gate 227A through the inverter 226. In other words, the first AND gate 227A is supplied with an inconsistent output indicating that it is outside the processing target region obtained by the data comparison circuit 224.

In addition, the microphone gate 222 extracts the image data subjected to the above-described boundary processing from the image data read out from the image memory 210, and passes it to the second latch circuit 223B through the first latch circuit 223A. At the same time, it is supplied to the second AND gate 227B. The second latch circuit 223B supplies the latch output to the first AND gate 227A.

로서 상기 NAND게이트(229)에 공급한다.The first AND gate 227A supplies its output to the reset terminal of the RS flip-flop 228. In addition, the second AND gate 227B supplies its output to the set terminal of the RS flip-flop 228. Furthermore, the negative output of the flip-flop 228 is supplied. The flip-flop 228 then window-posites its positive output.

It is supplied to the NAND gate 229 as a.

를 상기 플립-플롭(228)으로 형성한다. 상기 플립-플롭(228)에서 형성된 윈도우 펄스로서 게이트 제어되는 NAND게이트(229)는 상기 처리 대상 영역내의 화상 데이타에 대응하는 타이밍의 타이밍 클록만을 통과시키고, 그 게이트 출력에 의해 상기 3스테이트 인터페이스 회로(205)의 동작 제어 및 상기 화상 메모리(210)의 각 주사 라인마다에 기입/판독 제어를 행하며, 상기 3스페이트 인터페이스 회로(210)에 공급되고 있는 새로운 색의 화상 데이타로 상기 처리 대상 영역내의 화상 데이타를 치환한다.In the area processing circuit of the above-described configuration, when an area processing start pulse is supplied from the microcomputer 100 to the address counter 215, the image memory in accordance with the address data formed in the address counter 215. Image data is sequentially read from 210. FIG. When the image data of the processing target region is read from the image memory 210, the microphone gate 222 detects the boundary data representing the boundary position of the processing target region and sets the flip-flop 228. Thereafter, the data comparator 224 determines that the image data is not outside the processing target region and resets the flip-flop 228 with the boundary data, thereby making the image for one horizontal line of the processing target region. Window pulse corresponding to data

Is formed into the flip-flop 228. The NAND gate 229 gate-controlled as a window pulse formed in the flip-flop 228 passes only a timing clock at a timing corresponding to the image data in the processing target region, and the gate outputs the three-state interface circuit ( Operation control of 205 and write / read control are performed for each scan line of the image memory 210, and the image in the processing target area is image data of a new color supplied to the three-spatter interface circuit 210. Replace the data.

는, 예를들면, 제 15 도에 도시한 바와같은 영역내부에 다른 영역 AR_o을 포함한 처리 대상 영역 AR_s에 대해서, 또한 모든 영역에 대해서도, 모든 영역에 걸친 1수평 라인분의 윈도우 펄스로 되어 있다. 그리고, 상기 다른 영역 AR_o을 제외하는 데에는 상기 데이타 비교기(224)로부터의 일치 출력을 상기 NAND게이트(229)에 공급하는 스위치(225)를 폐쇄하여, 상기 일치 출력 및 상기 위도우 펄스로서 상기 NAND게이트(229)의 게이트 제어를 행하는 것이 좋고, 상기 스위치(225)의 조작에 의해서, 상술한 경계선 처리를 추적한 처리 대상 영역의 경계선으로 둘러 쌓여진 모든 영역에 대한 처리와, 그 내부의 다른 영역을 제외한 처리를 선택적으로 행할 수 있다.In this embodiment, the window pulse formed by the flip-flop 208

For example, for a processing target area AR _s including another area AR _o in the area as shown in FIG. 15, and for all areas, it is a window pulse for one horizontal line across all areas. have. In order to exclude the other area AR _o , the switch 225 for supplying the coincidence output from the data comparator 224 to the NAND gate 229 is closed to close the NAND gate as the coincidence output and the widow pulse. It is preferable to perform the gate control of 229, and by the operation of the switch 225, the processing for all the regions surrounded by the boundary of the processing target region which tracked the above-described boundary line processing, and excluding other regions therein. The process can be selectively performed.

Here, for example, the start address data supplied to the boundary line processing circuit shown in FIG. 12 is mounted in the high speed arithmetic processing circuit 200 by, for example, a start address detecting circuit having a configuration as shown in FIG. If so, the tablet 94 can be used to obtain an arbitrary position within the region to be processed.

In the start address detection circuit shown in FIG. 16, initial address data designating a position in the processing target area provided to the tablet 94 is loaded into the X address counter 215X and the Y address counter 215Y. Each of the address counters 215X and 215Y is supplied with a clock pulse through an AND gate 241 gated by an output of a flip-flop triggered by an address detection start pulse, and counts this clock pulse. . Then, the image memory 210 is accessed as the address counters 215X and 215Y, and the image data read out from the image memory 210 is directly connected to the data comparator 242 and the latch circuit 243. The data is supplied through the data comparator 242, and is compared with image data of one pixel before in the data comparator 242, and it is determined whether or not the data is on the boundary line. The data comparator 242 outputs the comparison output from the inverter 244 through the OR gate 245. The flip-flop 246 detects that the data comparator 242 outputs a logic “0”, that is, a boundary line. When the data is cleared, the AND gate 241 is closed to end the address detection operation. In addition, when the carry output of the X counter 215X is supplied to the clear terminal of the flip-flop 246 through the OR gate, and no boundary is detected between the horizontal scan line end positions. Cleared by the carry output, the AND gate 241 is closed to terminate the address detection operation. The contents of each of the address counters 215X and 215Y at the end of the address detection operation are output as start address data through the latch circuit 214. In the start address detection circuit, as shown in FIG. 17A, when initial address data indicating P _s is provided at any position within the processing target area AR _s closed by the border line, the boundary line position on the horizontal line where the position P _s exists is provided. The start address data indicating P _E is outputted from the latch circuit 214, and as shown in FIG. 17B, when the processing target area AR _S is located on the right side of the whole image, it is represented by the initial address data. Start address data indicating the end position P _E ′ of the horizontal line including the position P _S is obtained.

In addition, when another area AR _O is included inside as in the process target area AR _S of FIG. 15 described above, the boundary line with the other area AR _O can be detected. Can be discriminated by detecting that the detection operation is performed in the clockwise rotation direction. That is, the above-described boundary line detection circuit designates eight pixels in the vicinity of the detection target pixel in the counterclockwise rotation direction to perform a detection operation, and removes a boundary line with another area AR _{O in} the processing target area AR _S. As shown in FIG. 18, the detection is performed sequentially in the clockwise rotation direction. In order to determine whether the detection operation by the boundary detection circuit is performed in the counterclockwise rotation direction or the clockwise rotation direction, it is preferable to use a discrimination circuit having a configuration as shown in FIG. 19, for example.

In the discriminating circuit shown in FIG. 19, the detection output obtained by the above-described boundary detecting circuit, that is, the direction data is supplied directly to the difference 248 and through the latch circuit 247, and the difference obtained by this difference 248. Data is accumulated by the data adder 249.

The data adder 249 integrates the difference data while a boundary line of one week is detected in the boundary detection circuit. The most significant bit data of the add output obtained by this data adder 294 becomes logic "0" when the counterclockwise rotation direction detection operation is performed by the boundary detection circuit, and conversely, when the clockwise direction detection operation is performed, the logic " 1 ". Therefore, in the discrimination output by this discriminating circuit, boundary data indicating the boundary line with the other area AR _O can be designated, and the boundary line of any processing target region can be accurately detected by performing the boundary detecting operation and the discriminating operation in parallel. Can be. In addition, using the discrimination circuit, it is possible to perform area processing on another area AR _O in the processing target area AR _S.

As described above, in the geometric command data conversion processing performed after the manual editing process using the area processing apparatus, each image area of each image area is individually displayed with respect to the image represented by the color image data for various processing as described above. Geometry command data is formed in the following order.

First, the boundary of each image area is traced by the high speed arithmetic processing circuit 200 to detect the position coordinates of each vertex. Next, the detected position coordinate is regarded as the vertex position of the geometric figure (polygon), and converted into the geometric command data according to the above-described PDI code, for example, POLYGON. Furthermore, command data CONTROL corresponding to the color determined by the above-described color processing is given to each image region represented by the geometric figure connecting the vertices.

For example, as shown in FIG. 20, each vertex P ₀ , P ₁ ,... , In the said done for specifying the image area AR color as texture pattern TXP and combination of colors of the Tax processing pattern TXP, first each vertex P ₀ when converting to the command data according to the PDI code for the image area AR in the P ₄ , P ₁ ,.. Each location coordinates [X _0, Y _0] of the _{P 4, [X 1, Y} 1], [X 4, Y 4] , and by encoding the background color (background color), and specify the next texture pattern TXP in that Foreground color and the respective position coordinates [X ₀ , Y ₀ ], [X ₁ , Y ₁ ],... , Coding [X ₄ , Y ₄ ] again ends the coding for the picture region AR. As the texture pattern TXP, for example, as shown in FIG. 21, three types of patterns TXP ₁ , TXP ₂ , and TXP ₃ are selectively designated, and the foreground color is selectively designated from black and white two colors. As shown in the figure, five different color tones can be designated for the image area AR. In other words, if the texture pattern TXP between two kinds of colors is mp type and np is color,

The color of the N _p type can be represented schematically.

Now, a specific example of color specification of each image area in the present embodiment will be described. For the sake of simplicity, the input color image data assumes that the original image represents the color as color data of 3 ³ = 27 colors with each color of RGB as three levels. For example, as shown in FIG. 23, in order to synthesize the color C0 in which each level of RGB is represented as (0, 1, 2) to 2 pebbles, that is, 2 ³ = 8 colors, the RGB in the drawing is RGB. It is preferable to combine the color C _B indicated by the broken line with the level of (0, 2, 2) and the color C _F indicated by the dashed dashed line with the (0, 0, 2) at 1: 1. That is, it is good to use a checkered textural pattern with the foreground color as C _F (0, 2, 2) and the background color as C _B (0, 20, 2). Therefore, by designating the color data Dc (RGB) of the input color image data representing the respective colors of the original image as the read address, and reading the texture data as shown in FIG. 24 from the texture memory, 27 colors can be designated. Can be. In addition, the texture data is composed of the foreground color specification data D _CF (RGB), the background color specification data D _CB (RGB), and the texture specification data D _TX , where D _TX = 0 indicates color specification using only the foreground color, and D _TX = 1. Indicates a checkered texture pattern.

As is apparent from the description of the above-described embodiments, in the image area processing apparatus according to the present invention, each image region is arbitrarily designated for an image displayed by the image data stored in the image storage means, and image data of the designated region is changed. It is possible to provide a data processing apparatus which can be replaced with image data extremely simply and which is suitable for input image processing in a digital image transmission system or the like.

Claims (1)

An image processing apparatus comprising: (81.82.83) means for displaying digital image information, and an operation means 94 for performing a desired process on the displayed image, wherein the image storage memories 41 to 41 store input image data. 44) and area determining means (Figs. 6 to 11) for determining each image area of an image displayed as the same image data with respect to the input image data stored in the image storage memory, and the corresponding image area. Boundary detection means for tracking the boundary line of the image region (Fig. 6), boundary line memory 210 for storing the boundary line data obtained by the boundary detecting means, and a boundary line of the designated image region displayed in the boundary line data. The image data is replaced with another image arbitrarily designated, and the images are sequentially read from the image storage memory for each scanning line. Reading means (Fig. 13) and window pulse forming means 228 for forming each window scanning window pulse corresponding to the designated image area based on the image data and the boundary data; And image data in the designated image area according to the other specified image data.

Images