KR920008768A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR920008768A
KR920008768A KR1019910017788A KR910017788A KR920008768A KR 920008768 A KR920008768 A KR 920008768A KR 1019910017788 A KR1019910017788 A KR 1019910017788A KR 910017788 A KR910017788 A KR 910017788A KR 920008768 A KR920008768 A KR 920008768A
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South Korea
Prior art keywords
word line
memory device
semiconductor memory
test
signal
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KR1019910017788A
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Korean (ko)
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KR960001300B1 (en
Inventor
야수히로 훗타
Original Assignee
쓰지 하루오
샤프 가부시끼가이샤
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Publication of KR920008768A publication Critical patent/KR920008768A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)

Abstract

내용 없음No content

Description

반도체기억장치Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 제1실시예를 개략적으로 설명하는 회로도,1 is a circuit diagram schematically illustrating a first embodiment of the present invention;

제2도는 본 발명의 제2실시예를 개략적으로 설명하는 회로도,2 is a circuit diagram schematically illustrating a second embodiment of the present invention;

제3도는 본 발명의 제3실시예를 개략적으로 설명하는 회로도.3 is a circuit diagram schematically illustrating a third embodiment of the present invention.

Claims (9)

병렬로 배열되는 복수의 워드선과, 그리고 상기 워드선을 각각 구동하는 워드선 구동수단을 포함하는 반도체 기억장치에 있어서, 테스트 신호를 수신하고 그리고 출력신호를 생성하는 워드선 테스트 수단을 포함하고, 상기 출력신호의 레벨은 상기 테스트신호가 활성일때는 high 그리고 상기 테스트 신호가 비활성일때는 low로 되고, 상기 워드선 구동수단의 사전선택된 상기 테스트 수단의 출력에 결합되고, 그리고 대응워드선이 구동되지 않을때 상기 출력신호를 상기 대응워드선에 적용하는 반도체 기억장치.A semiconductor memory device comprising a plurality of word lines arranged in parallel and word line driving means for driving the word lines, respectively, comprising: word line test means for receiving a test signal and generating an output signal; The level of the output signal is high when the test signal is active and low when the test signal is inactive, coupled to the output of the preselected test means of the word line driving means, and the corresponding word line is not driven. And applying the output signal to the corresponding word line. 제1항에 있어서, 상기 사전선택 워드선 구동수단은 홀수워드선에 접속된 것인 반도체메모리장치.2. The semiconductor memory device according to claim 1, wherein said preselection word line driving means is connected to an odd word line. 제1항에 있어서, 상기 사전선택 워드선 구동수단은 짝수워드선에 접속된 것인 반도체메모리장치.2. The semiconductor memory device according to claim 1, wherein said preselection word line driving means is connected to an even word line. 병렬로 배열되는 복수의 비트선을 포함하는 반도체 기억장치에 있어서, 테스트신호를 수신하고, 상기 테스트신호가 활성일때, 제1출력신호는 상기 비트선의 홀수것에 그리고 제2출력신호는 상기 비트선의 짝수것에 적용하는 비트선 테스트 수단을 포함하고, 상기 제1과 제2출력신호는 서로 레벨에서 다른 반도체 기억장치.A semiconductor memory device comprising a plurality of bit lines arranged in parallel, wherein a test signal is received and when the test signal is active, a first output signal is an odd number of the bit lines and a second output signal is an even number of the bit lines. And bit line test means applied to the semiconductor memory device, wherein the first and second output signals are different from each other. 제4항에 있어서, 상기 비트선 테스트 수단은 상기 테스트신호가 활성일때, 상기 비트선 테스트수단을 상기 비트선에 접속하는 스위치 수단을 포함하는 반도체메모리장치.5. The semiconductor memory device according to claim 4, wherein said bit line test means comprises switch means for connecting said bit line test means to said bit line when said test signal is active. 병렬로 배열되는 복수의 워드선과, 병렬로 배열되는 복수의 비트선과, 그리고 상기 워드선을 각각 구동하는 워드선 구동수단을 포함하는 반도체 기억장치에 있어서, 테스트신호를 수신하고, 그리고 출력신호를 생성하는 워드선 테스트수단을 포함하고, 상기 출력신호의 레벨은 상기 테스트신호가 활성일때 high이고 상기 테스트신호가 비활성일때는 low이고, 테스트신호를 수신하고, 상기 테스트신호가 활성일때, 제1출력신호는 상기 비트선의 홀수것에 그리고 제2출력신호는 상기 비트선의 짝수에 적용하는, 비트테스트 수단을 포함하고, 상기 제1과 제2출력신호는 서로 레벨에서 다르고, 상기 워드선 구동수단의 사전선택된 것을 상기 테스트 수단의 출력에 결합되고, 그리고 대응워드선이 구동되지 않을때, 상기 출력신호를 상기 대응워드선에 적용하는 반도체기억장치.A semiconductor memory device comprising a plurality of word lines arranged in parallel, a plurality of bit lines arranged in parallel, and word line driving means for driving the word lines respectively, wherein the semiconductor memory device receives a test signal and generates an output signal. And word line test means, wherein the level of the output signal is high when the test signal is active and low when the test signal is inactive, and receives a test signal and when the test signal is active, a first output signal. Includes bit test means for applying an odd number of the bit lines and a second output signal to an even number of the bit lines, wherein the first and second output signals differ from each other at a level and are preselected. Is coupled to the output of the test means, and when the corresponding word line is not driven, the output signal is applied to the corresponding word line. The semiconductor memory device. 제6항에 있어서, 상기 사전선택된 워드선 구동수단은 홀수 워드선에 접속된 것인 반도체 기억장치.7. The semiconductor memory device according to claim 6, wherein said preselected word line driving means is connected to an odd word line. 제6항에 있어서, 상기 사전선택된 워드선 구동수단은 짝수 워드선에 접속된 것인 반도체 기억장치.7. The semiconductor memory device according to claim 6, wherein said preselected word line driving means is connected to an even word line. 제6항에 있어서, 상기 비트선 테스트수단은 상기 테스트신호가 활성일때, 상기 비트선 테스트수단을 상기 비트선에 접속하는 스위치수단을 포함하는 반도체기억장치.7. The semiconductor memory device according to claim 6, wherein the bit line test means includes switch means for connecting the bit line test means to the bit line when the test signal is active. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임※ Note: The disclosure is based on the initial application.
KR1019910017788A 1990-10-11 1991-10-10 Semiconductor memory device KR960001300B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP90-274803 1990-10-11
JP2274803A JP2647546B2 (en) 1990-10-11 1990-10-11 Test method for semiconductor memory device

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KR920008768A true KR920008768A (en) 1992-05-28
KR960001300B1 KR960001300B1 (en) 1996-01-25

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US (1) US5331594A (en)
EP (1) EP0480752B1 (en)
JP (1) JP2647546B2 (en)
KR (1) KR960001300B1 (en)
DE (1) DE69124562T2 (en)
TW (1) TW218935B (en)

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Also Published As

Publication number Publication date
KR960001300B1 (en) 1996-01-25
US5331594A (en) 1994-07-19
EP0480752B1 (en) 1997-02-05
EP0480752A3 (en) 1993-02-24
EP0480752A2 (en) 1992-04-15
DE69124562T2 (en) 1997-08-14
JP2647546B2 (en) 1997-08-27
JPH04149900A (en) 1992-05-22
TW218935B (en) 1994-01-11
DE69124562D1 (en) 1997-03-20

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