KR920006281B1 - Circuit for queue maiutenance on pos terminal - Google Patents

Abstract

The circuit includes an interrupt control section, a processing section, and an interrupt generating section. The circuit further includes a means for receiving sales information and for generating OBR termination signals. Another means enables the OBR termination signals, and still another means latches a first control signals upon encountering an OBR termination signal. Further another means makes the first control signal transformed into a second control signal, and still further another means forms a signal path upon encountering the second control signal and blocks the signal path upon encountering the first control signal. With the circuit, the sales order is maintained regardless of the contents of the sales.

Description

Sales Order Maintenance Circuit of Poster Terminal

1 is an interrupt circuit diagram of conventional sales information.

2 is an operating waveform diagram of FIG.

3 is an interrupt circuit diagram for sales information of the present invention.

4 is a concrete circuit diagram of FIG.

5 is an operational waveform diagram of FIGS. 3 and 4;

6 is a data processing flowchart according to the present invention.

* Explanation of symbols for main parts of the drawings

10: keyboard 12: OBR

12: MCR 13: serial / parallel conversion unit

14 interrupt control unit 16 decoder

16,17: Oagate 18: Andgate

19,22: 3 state buffer 20: Inverter

21: NAND Gate 23: Counter

24: flip flop

The present invention relates to a poster terminal, and more particularly to a circuit capable of maintaining the order of sales information generated from a plurality of information input devices.

In general, a point of sales terminal refers to a device that processes sales information generated at a point of sale in real time, and should be able to process information generated from a plurality of input devices.

It should be possible to process information generated by multiple input devices. The input device includes a keyboard, an OBR (Optrcar Barcode Reader), an MCR (Magnctic Card Reader), and the keyboard is a device that generates information at the point of sale through a key, and the OBR is barcode information displayed on a product. It is a device that generates data consisting of multiple bytes by analyzing the data, and MCR refers to a device that reads a credit card.

)로 공급된다. 이때(2f)와 같이 판매정보의 발생순서가 단품→OBR→소계→현금마감 순으로된 경우를 가정하면, 키보드(1)는 (2a)와 같이 판매정보 발생시점에서 인터럽트 요구신호(KBO REQ)를 발생하고, OBR(2)는 상기 키보드(1)에 출력이 없는 경우에 OBR데이타들을 처리하게 된다. 즉, 키보더(1)와 OBR(2)에서 CPU(6)로 인터럽트 요구신호를 발생하여 데이타 처리를 요구하는 경우, OBR데이타는 여러개의 데이타로 구성되어 있으므로, 여러번의 인터럽트 요구신호(PBR REQ)를 발생하게 된다. 그러나 이때(2a)와 같이 OBR데이타 처리 도중에서 키보드(1)의 인터럽트 요구신호(KBD REQ)가 발생되면, CPU(6)는 OBR데이타 수신도중에 키보드(1)의 1바이트 정보를 수신하게 된다. 예를들면, 제2도의 (A)시점에서 단품키가 눌려지면 단품판매에 대한 정보가 발생되며, (B)시점에서 OBR데이타 발생되면 CPU(6)는 수신되는 OBR데이타를 수신하고 있는 시점에서 다시 키보드(1)의 소제정보가 발생되며, CPU(6)는 OBR처리중에 키보드(1)의 정보를 수신하게 된다.Conventionally, the sales information of the keyboard, OBR, and MCR shown in FIG. 2 has been processed in the configuration of FIG. That is, when an interrupt request signal (KBDREQ: OBRREQ, MCRREQ) occurs in accordance with sales information in the keyboard 10, OBR 12, MCR 13, etc., these signals are output through the oragate 14, and through the interrupt control unit. The interrupt terminal (INT) of the CPU 6 through the AND gate 15 together with the generated interrupt acknowledgment signal ACK.

Is supplied. In this case, assuming that the generation order of sales information is in the order of unit → OBR → subtotal → cash closing as shown in (2f), the keyboard (1) interrupt request signal (KBO REQ) at the point of sales information generation as shown in (2a) The OBR 2 processes the OBR data when there is no output on the keyboard 1. That is, when the interrupt request signal is generated from the keyboard 1 and the OBR 2 to the CPU 6 to request data processing, since the OBR data is composed of a plurality of data, the interrupt request signal PBR REQ ) Will occur. However, when the interrupt request signal KBD REQ of the keyboard 1 is generated during the OBR data processing as in (2a) at this time, the CPU 6 receives 1-byte information of the keyboard 1 during OBR data reception. For example, when the unit key is pressed at the time (A) of FIG. 2, information on the sale of the unit is generated. When the OBR data is generated at the time (B), the CPU 6 receives the received OBR data at the time of receiving the received OBR data. The cleaning information of the keyboard 1 is again generated, and the CPU 6 receives the information of the keyboard 1 during the OBR process.

Then, when the cash close key of the keyboard 1 is pressed at the time (D) of receiving the OBR data, the CPU 6 processes this signal prior to the OBR data processing as described above. Therefore, when the sales information of the keyboard 1 is generated, the type of data received by the CPU 6 as a result of being processed in preference to the interruption of the OBR 2 is equal to (2e). Therefore, the sales results are in the order of single item → subtotal → cash deadline → OBR → data. However, in the conventional method as described above, when data is input from the keyboard and other input devices during OBR data reception, the OBR data reception is received and the corresponding data is received first, which causes the OBR data to be reregistered or other customers. There were problems that could not be maintained in the accuracy of the sales store because it could be included in the sales process.

Accordingly, an object of the present invention is to provide a sales order maintenance circuit that can receive data while maintaining the generation order of sales information regardless of the data length of the input device in the poster terminal.

Hereinafter, the present invention will be described in detail with reference to the drawings.

3 is a configuration diagram of the present invention, including an input device, a CPU for detecting and processing a sales information generation signal generated from the input devices of the keyboard 10, the OBR 11, and the MCR 12 as an interrupt signal ( A poster terminal having 30) maintains the generation order of interrupt request signals generated by the input devices and connects the interrupt control circuit 40 to generate an interrupt signal to the CPU 30.

4 is a detailed circuit diagram of the interrupt controller in FIG. 3, which includes an inverter 20 and a NAND gate 21, means for generating an OBR end signal by detecting an OBR operator from data output to a data bus; Means comprising a hexadecimal counter 23 and a tertiary buffer 22 to count the conversion clock to " on " the toll of the second control signal between when the OBR & Means for latching a first control signal when an OBR acknowledgment signal is generated, and for stopping the first control signal and transitioning to a second control signal when an OBR termination signal is generated, and when the second control signal is generated as a three-state buffer 19 (24). And a means for forming an interrupt request signal path of the keyboard 10 and the MCR 12, and blocking the path of the keyboard 10 and the MCR 12 when the first control signal is generated.

FIG. 5 is a waveform diagram showing that data is processed in the order of generating sales information when the interrupt control circuit as shown in FIG.

6 is a flowchart in which the CPU 30 processes data while maintaining the generation order of sales information in accordance with the occurrence of an interrupt.

Based on the above configuration, the present invention will be described in detail with reference to FIGS. 3, 4, 5, and 6. FIG. First, the input device of the poster terminal includes the keyboard 10, the OBR 11, the MCR 12, and the bar code information generated in the OBR 11 is started and OBR data. It consists of a number of bytes including bytes. Therefore, the CPU 30 should be able to process the data of the OBR 11 by not receiving an interrupt request signal from another input device when receiving the data of the OBR 11. First, an operation process when an interrupt request signal (hereinafter referred to as KBDREQ) is generated in the keyboard 10 will be described. When a KBD REQ signal is generated in the keyboard 10, the signal is transferred to the interrupt control unit 14 and the tri-state buffer 19. Is approved. In this case, since the third control buffer 19 generates the second control signal of the "high" state in the flip-flop 25, the KBDREQ signal has one input of the AND gate 18 through the oragate 17. do. In addition, the interrupt control unit 14 generates a KBDACK signal in response to the KBD REQ signal, whereby the KBD ACK signal outputting the decoder 15 is transmitted to the other input of the AND gate 18 through the oragate 16. Is approved.

Thus, the AND gate 18 generates an interrupt signal to the CPU 30.

Secondly, when an interrupt request signal (hereinafter referred to as "MCR REQ") of the MCR 12 is generated, the OBR REQ signal is applied to the one side input of the AND gate 18 through the oragate 17 and at the same time the interrupt control unit ( 14), the interrupt control unit 14 generates an OBR ACK signal by the OBR REQ signal. The decoder 15 then applies the OBR ACK signal to the other input of the AND gate 18 through the oragate 16, so that the CPU 20 is supplied with an interrupt signal.

In addition, since the OBR ACK signal of the decoder 15 is applied to the clock end of the flip-flop 25, the flip-flop 25 is operated by the OBR ACK signal to convert the first control signal of the "low" state to the inverted output terminal. Output as (Q). Thus, the tri-state buffer 19 is disabled to block the passage of the KBD REQ signal and the MCR REQ signal.

Therefore, whenever the data is generated in the OBR 12, the AND gate 18 generates an interrupt signal, and the sales information of the keyboard 10 and the MCR 11 is temporarily interrupted. At this time, the serial data outputting the OBR 11 is applied to a serial input / parallel output unit 13, and is serially converted by the clock CK1 and loaded on the data bus. At this time, the data loaded on the data bus is applied to the NAND gate 21 through the inverter 20, in order to detect the AND data of the OBR. At this time, if the end data of the OBR 11 is 40H (0100.0000), it is converted into FF _H through the inverter 20, whereby the NAND gate 21 outputs a "low" signal. At this time, the hexadecimal counter 23 counts the same clock CK1 as the clock CK1 of the serial / parallel conversion unit 13, which is a tri-state buffer (8-bit serial data) after being completely converted into parallel data. 22) to open the OBR and data detection signal.

This is because the serial / parallel conversion unit 13 enables the passage at the end of the parallel conversion, so that 40H data that may occur in the conversion process is not treated as OBR end data. Therefore, when the tri-state buffer 22 is enabled at the time of OBR and data generation, a signal of the "low" state is applied to the clear terminal of the flip-flop 24. The output of the inverted output terminal Q of the flip-flop 24 then transitions from the first control signal in the "low" state to the second control signal in the "high" state, thereby enabling the three-state buffer 19 to be enabled. It forms the passage of KBD REQ and MCR REQ. Here, as shown in (5e) of FIG. 5, the sales order is in the order of single item → OBR → subtotal → cash close. At the time t1, the flip-flop 24 generates the second control signal in the “high” state. to be.

Accordingly, the KBD REQ signal of the keyboard 10 such as 5a is applied to the AND gate 18 through the tri-state buffer 19 and the oragate 17, and the interrupt controller 14 is connected to the KBD REQ signal. This generates a KBD ACK signal and applies it to the AND gate 18. Therefore, the AND gate 18 generates an interrupt signal such as 5c to the CPU 30. At this time, the 8-bit serial data outputting the keyboard 10 is converted into 8-bit parallel data through the serial / parallel converter 13 and loaded on the data bus as 5d, and the CPU 30 transmits the interrupt signal. This process reads the part information on the data bus, stores it in a buffer, and processes it. At this time, when the OBR REQ signal is generated as shown in (5b) at the time t2, this signal is applied to the AND gate 18 and to the interrupt control unit 14, and the interrupt control unit 14 generates the OBR ACK signal by this signal. Is generated and applied to the AND gate 18 through the decoder 15 and the oragate 16. At this time, since the OBR ACK signal outputting the decoder 15 is applied to the clock of the flip-flop 24, the flip-flop 24 generates a first control signal for disabling the three-state buffer 19, and thus As a result, the generation of the KBD REQ and OBR REQ signals is blocked. Therefore, the AND gate 18 continuously generates an interrupt signal such as 5c by an OBR REQ signal such as (5b) generated by the OBR 11, and the CPU 30 generates an interrupt signal on the data bus by the interrupt signal. Continuously receive data such as (5d). At this time, the inverter 20 and the NAND gate 21 detect the presence or absence of the end data of the OBR. When the end data 40H is detected, the inverter 20 and the NAND gate 21 generate a "low" state. Therefore, when the AND data 40H is completely loaded on the data bus, the counter 23 enables the tri-state buffer 22, whereby the low signal (OBR data end signal) of the NAND gate 21 is flipped. The flop 24 will be cleared. In this case, the flip-flop 24 transitions from the first control signal to the second control signal of the "high" state, thereby enabling the tri-state buffer 19 to enable passage of KBD REQ and MCR REQ which may occur next. Form.

Therefore, the OBR data can be processed continuously from the time point T2 to the time point T3, thereby maintaining the sales order. At this time, the CPU 30 performs the flow as shown in FIG. 6 every time an interrupt occurs, analyzes the interrupt type (KBD REQ, OBR REQ, MCR REQ) in step (A2), and then executes (A3) at the time of KBD REQ or MCR REQ. Store in a buffer in a step. In step (A4), the OBR flag is checked to process the corresponding received data in the reset state, and returned without processing to receive the OBR data in the set state. In addition, the OBR flag is analyzed in the step (A5) at the OBR REQ date and time, and the OBR start data is entered in the reset state, so set the OBR flag in the step (Ae), save the data in the buffer, and return. In this case, the data is continuously stored in the buffer until the OBR end data is received. However, in step (A6), OBR end data is detected, and in step (A7), the end data is stored in the buffer, the OBR flag is reset, and the OBR data stored in the buffer are read and processed.

In the poster terminal using a plurality of input devices as described above, it is possible to maintain the input sales information to be processed in the order of occurrence, thereby eliminating the registration errors that may occur during the sales process to re-registration or information There is an advantage that can prevent confusion.

Claims (1)

An input device such as a keyboard, OBR, MCR, a sales information generating device, a control unit that reads and processes information on a data bus by means of an interrupt signal, and generates an acknowledgment signal for an interrupt request signal generated from the input devices. In the sales order maintaining circuit of Foster Terminal, which has an interrupt control unit for notifying the CPU of the same, and means for generating an interrupt signal to the CPU when the interrupt request signal and acknowledgment signal are generated, the sales information data on the data bus is inputted. Means for generating an OBR end signal upon detection of OBR end data, means for enabling the passage of the OBR end signal by counting a period in which serial data of the input device is carried as parallel data on a data bus, and When the interrupt acknowledgment signal is generated, the first control signal is latched, and when the OBR end signal is generated, the first control signal is latched. Means for translating a signal to a second control signal, and connected between the keyboard and the MCR and an interrupt signal generating means to form an interrupt passage when the second control signal is generated and to block when the first control signal is generated; A sales order maintenance circuit for poster terminal, characterized in that it operates to process information by maintaining a generation order regardless of the length of sales information that occurs.

Images