JPS6398081A - Bar code reader - Google Patents

Abstract

PURPOSE:To easily perform the change or the correction of the logic of recognition, by processing only detection whether information is bar code information or not by a hardware, and performing the recognition processing of a bar code by a microcomputer in a software way. CONSTITUTION:A bar code pattern detection circuit 29 detects a bar code pattern by using an inputted binarization signal, and a digital data, and informs the fact that the bar code information is stored in a FIFO register 28 to the microcomputer 30 by a bar code detecting signal. The computer 30, at the time of receiving the input of the bar code detecting signal from the circuit 29, reads the data of the register 28 by applying interruption, and performs the recognition processing of the bar code. Thereby, at the time of changing or correcting the logic of the recognition such as decode, or algorithm, etc., the circuit 29 can be used without applying any change, and a part to be changed is limited only to the program of the computer 30, therefore, a changing work can be facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a barcode reading device for reading barcodes attached to products, for example.

[Prior Art] Barcode reading II includes those using a hand scanner and those using a stationary scanner.

Conventionally, as shown in FIG. 10, when a hand-held scanner is used, a barcode is scanned and read by, for example, a pen-type scanner 1, and then the signal is processed and binarized by a binarization circuit 2. The binary signal is subjected to software processing by the microcomputer 3 to create a barcode ill.

Since the pen-type scanner 1 is operated manually, the scanning speed of the barcode is slow, and therefore software processing by the microcomputer 3 is sufficient.

On the other hand, as shown in FIG. 11, a stationary scanner uses a laser light source 5 installed in a box-shaped table 4, and the laser beam from the light source 5 is deflected by a rotating polygon mirror 6. to scan the reading window 7 on the stage 4. When the barcode is located on the window 7, the reflected light is received by the light receiver 8, and the signal from the light receiver 8 is amplified and processed by the binarization circuit 9.
The binarized signal is quantized into a digital amount corresponding to the width of the bar by a run length counter 10, and the digital signal is processed by a barcode KLiE circuit 11 to determine the margin, guard bar, and whether or not it is a barcode. It is known that a microcomputer 12 executes character determination and character decoding in real time at high speed, and then executes character editing, checking (parity check, modulus check), and interface at relatively low speed. In other words, in those that use a stationary scanner, barcodes are scanned at high speed using a laser beam, so it is not necessary to input the data processed by the run-length counter 10 directly into the microcomputer 12 and process it using software. Since speed is required, this is not possible, so the bar code recognition circuit 11 is used to perform the high-speed processing part in hardware, and then the microcomputer 12 processes it.

[Problems to be Solved by the Invention] However, the conventionally used barcode recognition circuit 11 cannot judge margins, guard bars, judge whether or not it is a barcode, etc.
Since it has a logic circuit configuration that performs all character decoding, the circuit configuration becomes quite complex, and
Change recognition logic such as decoding and algorithms,
If such a correction is made, the logic circuit configuration of the barcode recognition circuit 11 must be changed, resulting in a problem that the work becomes extremely troublesome.

In this invention, only the detection of whether or not it is barcode information is performed by hardware processing, and the barcode recognition processing is performed by software by a microcomputer. Changes or modifications to the tWA logic can be handled by simply changing the program.
It is an object of the present invention to provide a barcode reading device in which the recognition logic can be changed and modified relatively easily, and the logic circuit configuration of the hardware part can be relatively simple.

[Means for Solving the Problems] The present invention provides a barcode detection section, a binarization circuit that processes a signal from the barcode detection section and outputs a binarized signal, and this binarization circuit. A run-length counter that converts the binary signal from the binary circuit into run-length data, one or more shift registers that store the output of this counter, and inputs the 211-coded signal from the binary circuit and the data from the run-length counter. a barcode pattern detection circuit that detects a barcode pattern; and a barcode pattern detection circuit that reads data from one or more shift registers in response to a barcode detection signal from this barcode detection circuit and detects the barcode pattern. ! ! The barcode pattern detection circuit includes one or more microcomputers that perform identification processing, and the barcode pattern detection circuit includes a plurality of counters that perform counting operations sequentially in response to changes in the binary signal and in one character period of the barcode; a plurality of latch circuits that latch the data of each counter, a character width variation detection circuit that detects a variation in character width in response to each latch circuit output and each counter output;
A determination circuit responds to the output of this detection circuit and determines whether the character width fluctuations are continuous within a specified range, and when this determination circuit determines continuity, a constant value is assigned to the data for one character at that time. A data holding circuit that holds the same data, compares the data held in this data holding circuit with the run length counter data, and outputs a barcode detection signal when the counter data is greater than the holding circuit data. It consists of a comparison output circuit.

[Operation] In the present invention having such a configuration, barcode read data that has been binarized by the binarization circuit is converted into m children by the run-length counter to become run-length data, and is stored in the shift register.

On the other hand, in response to changes of 0 and 1 in the binary signal, a plurality of counters sequentially perform a counting operation in one character cycle of the bar code, and the count data of each counter is latched by a latch circuit. Fluctuations in the character width are detected based on the outputs of each latch circuit and the outputs of each counter, and it is determined whether the fluctuations are continuous within a specified range.

Then, it is determined that the fluctuation is continuous within the specified range, and then the data obtained by multiplying the data for one character by a certain value is compared with the run length counter data, and if the counter data is larger, the bar code information A barcode detection signal is output to the microcomputer to inform the microcomputer that the barcode has been stored in the shift register.

As a result, the microcomputer reads the data stored in the shift register and performs barcode recognition processing.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, a laser light source 22 is installed inside a box-shaped stand 21.
A laser beam from the light source 22 is deflected by a rotating polygon mirror 23 to scan the surface of a reading window 24 provided on the table 21. For example, when a bar code attached to a product is located on the upper surface side of the window 24, the laser beam is reflected by the bar code, and the reflected light is received by the light receiver 25.

The output signal from the photoreceiver 25 is input to a binarization circuit 26, which performs amplification, signal processing, etc., and converts it into a binary signal. 2 from this binarization circuit 26
The value signal is input to a run length counter 27, and the counter 27 quantizes it into a digital amount corresponding to the width of the bar.

The digital data quantized by the run-length counter 27 is supplied to a FIFO (first-in-first φ-out) register 28, which is a type of shift register and has a storage capacity of, for example, 256 bytes.

Further, the binary signal from the binarization circuit 26 and the digital data from the run length counter 27 are supplied to the barcode pattern detection circuit 29. This barcode pattern detection circuit 29 detects a barcode pattern using the input binary signal and digital data, and
The microcomputer 3 uses a barcode detection signal to confirm that barcode information is stored in the O register 28.
I am trying to notify 0.

When the microcomputer 30 receives a barcode detection signal from the barcode pattern detection circuit 29, it uses an interrupt to read data from the FIFO register 28 and perform barcode recognition processing.

The run length counter 27, FIFO register 28
Specifically, the circuit including the barcode pattern detection circuit 29 is constructed as shown in FIG.

That is, the 2IIi signal from the binarization circuit 26 is passed through the two-stage D-type flip 70 tube 31, 32 and the exclusive OR circuit 3.
3 and generates an etch signal EDG. Further, the etch signal EDG is inputted to a D-type flip-flop 34 to generate an etch signal EDG'. Note that the clock CLK generated from the clock generator 35 is input to the clock input terminal OK of each of the seven lip-flops 31, 32, and 34.

That is, when the binary signal is inputted as shown in FIG. 3(a), the flip-flop 31 receives the clock CLK shown in FIG. 3(b) and outputs the signal in FIG. 3(C). At the same time, the flip 70 tube 32 operates at the timing shown in FIG. 3(d) by receiving the output of the flip-flop 31 and the clock CLK, and the exclusive OR gate 33 operates at the timing shown in FIG. 3(e). Edge Shinji shown in J! EDG is output. And this sex signal ED
G and the clock CLK are input to the flip-flop 34, and the flip-flop 34 outputs the third factor, the etch signal EDG' shown in (, f).

The edge signal EDG is ANDed with the write enable from the microcomputer 30 and is supplied to the FIFO register 28 as a write signal. Note that data is read from the FIFO register 28 using a read clock from the microcomputer 30.

The edge signal EDG' is applied to the run length counter 2.
It is supplied to the clear terminal CLR of No.7.

This run length counter 27 is, for example, a 9-bit counter, which inputs the clock CLK from the clock generator 35 to the clock input terminal GK and counts it, thereby converting the width of the bar into digital data whose minimum unit is the clock CLK. I try to do that.

The edge signal EDG is also input to the G input terminal of the 2-bit counter 36 and decoder 37. The Q^ and QB ratio outputs of the counter 36 are input to the A and B input terminals of the decoder 37, respectively, and the A of the 7-bit multiplexer 38.39.

Each is input to the B input terminal.

That is, the counter 36 receives the edge signal EDG shown in FIG. 4(b) and sends out the QA ratio output shown in FIG. 4(C), as well as the Qa ratio output shown in FIG. 4(d). . The decoder 37 receives the edge signal EDG and the QA ratio output and QB ratio output from the counter 36, and outputs the output terminals Yo and Yl.

Output Eo shown in FIG. 4(e) from Y2 and Yl.

The output Es shown in (f) of FIG. 4, the output E2 shown in (Q) of FIG. 4, and the output E3 shown in (h) of FIG. 4 are output, respectively.

Each output EO, Et from the decoder 37.

E2, Ei are four 7-bit counters 38.39°4
0.41 is supplied to the clear terminal CLR.

The clock input terminal OK of each of the counters 38 to 41 receives 1/4 of the clock CLK from the clock generator 35.
A clock CLK' whose frequency is divided by 174 by a frequency divider 42 is inputted.

The counter data of each counter 38, 39, 40, 41 is transferred to four 7-pit latch circuits 43, 44, 45, 46.
I try to latch each one. The clock input terminal GK of each latch circuit 43 to 46 is connected to the decoder 3.
7 each output EO.

Es, E2, and E3 are each input.

The data latched by each of the latch circuits 43 to 46 is transferred to the input terminals Xo and Xl of one of the multiplexers 38 mentioned above.
, X2 *
, is input to X3. Each of these multiplexers 38.3
9 is an input terminal Xa to which the outputs Q^ and Qe of the counter 36 are input.

The data input to Xl, X2, and X3 are selectively output from output terminal Y.

The output data from the multiplexer 38 is divided into 28/32
It is supplied to a multiplier 47 and a 36/32 multiplier 48. The 28/32 multiplier 47 is, for example, a 7-pit subtracter as shown in FIG. 6, and the output F is A-8, which is Aa.
By connecting ~A6 and Bn~B6 as shown in the figure, it becomes A-A/8-7/8A-28/32A. By using a subtractor in this way, multiplication can be performed in real time. The 36/32 multiplier 48 can be realized by replacing the subtracter used in the 28/32 multiplier 47 with an adder.

That is, it becomes F-A+A/8-9/8A-36/32A.

The output of the 28/32 multiplier 47 is supplied to a 7-bit converter 49 as data A, and is also supplied to a 7-bit latch circuit 50. Further, the output of the 36/32 multiplier 48 is supplied as data A to a 7-pit comparator 51. The output from the multiplexer 39 is also input as data B to the comparators 49 and 51.

The comparator 49 compares data A and data B and outputs a signal when A≦B, and the comparator 51 compares data A and data B and outputs a signal when A≧B. Then, the output signal from the comparators 49 and 51 and the write enable from the microcomputer 30 are ANDed. This detects whether the ratio between the current character width and the previous character width is within the range of ±12.5%.

JK flip 70 tube 52, 53.54 and 55.56
．． The circuit composed of 57, 58, 59, 60, 61, 62, 63 inputs the AND output, and the variation in character width of consecutive characters is within the specified range (±12.5%).
This is a judgment circuit that judges whether 4 characters continue in (in).
The flip-flops 52-63 operate in synchronization with the output E3 of the decoder 37, and the flip-flops 55-57 operate in synchronization with the output E3 of the decoder 37.
The flip-flop 58 operates in synchronization with the output E2 of the flip-flop 58.
~60 is the output E! of the decoder 37! The flip-flops 61 to 63 operate in synchronization with the decoder 37.
It operates in synchronization with the output Ea of.

The barcodes called UPC and JAN codes for -M are the standard version shown in Figure 8(a) and the 8th factor (
A shortened version shown in b) is known, but these express one character X with seven modules.

Note that 1 module indicates the minimum dimension constituting a bar or space. Therefore, to distinguish barcodes from other information or noise, look for this regularity (one character, i.e. 4 consecutive bars, space length approximately equal to the length of the adjacent character for 4 or more characters). It's a good thing.

This is done by the aforementioned determination circuit.

For example, if we consider the case where the barcode is the shortened version shown in FIG. 8(b), the barcode shown in FIG.
When the digitized signal is input, the decoder 37 outputs the signal (b) in FIG.
), (C), (d), and (e) output Eo,
El, E2, and El are output. Now considering the flip-flops 52 to 54, the flip 70 block 52 operates in synchronization with the output E3 as shown in the fifth factor (f).

The flip-flop 53 responds to the output of the flip-70 knob 52 and outputs the signal shown in (Q) in FIG. A signal shown in (h) of FIG. 5 is outputted by ANDing with . That is, at the time point ■ of the output E3 of the decoder 37, there is a possibility that the AND output of each comparator 49°51 is at a high level, but at the next point ■, the margin (7 modules) + guard par (3 modules)>1 Since it becomes a character (7 modules), the AND output becomes a low level, and the flip 70 knobs 52 and 53 are cleared. Since the current character width and the previous character width are approximately equal at the time point (2), the AND output becomes high level, and the flip 70 knob 52 is set at the rising edge of the output E3. Similarly, at the time point ■, the current character width and the previous character width are approximately equal, so the AND output becomes high level, and at the rise of the output E3, the 7 flip-flop 52 is inverted and reset, and the flip-flop 53 is changed instead.
is set. The same thing happens at the time point (2), where the flip-flop 52 is set and the 7-lip flop 54 is set. The same holds true at point (2), where the flip-flop 52 is reset and the flip-flop 53 is reset.

In this way, the flip 70 knob 54 is set when the character widths of four consecutive characters are substantially equal, and outputs a set signal to the AND gate 65 via the OR gate 64.

The latch circuit 50 latches the output of the 28/32 multiplier 47 when the output of the OR gate 64 rises. That is, data with a width of approximately 6 modules, which is 28/32 of the determined character width of 7 modules, is latched into the latch circuit 50. The data of this latch circuit 50 is then supplied to a 7-bit converter 66 as B data. The count data of the run length counter 27 is also input to the comparator 66 as A data. And this comparator is A
>8, that is, when the width indicated by the data of the run length counter 27 becomes larger than the width indicated by the data of the latch circuit 50, a signal is output to the AND gate 65. At this timing, a barcode detection signal is output from the AND gate 65 to the microcomputer 30, and an interrupt is generated to the microcomputer 30. At this time, run length data corresponding to the margin is stored in the last byte of the FIFO register 28, and data determined to be barcode information is stored before that.

The microcomputer 30 has a FIFO register 28
When the data stored in is read, the bar code recognition process shown in FIG. 7 is performed. This first searches for the position of the margin and guard bar. Next, the first half of the barcode is decoded character by character, and after checking the center bar, the second half of the barcode is further decoded character by character. Finally, margins and guard bars on the opposite side are detected, followed by a parity check, and then a modulus check. If there is any abnormality in these two checks, it will be treated as an error. If both of these checks are OK, the decoded data is transferred to, for example, a product sales data processing section.

In this embodiment having such a configuration, the barcode pattern detection circuit 29 performs run-length processing on the read signal based on the 2 (ii) multiplication signal, and the information stored in the FIFO register 28 is converted into barcode information. When it is determined that the barcode is likely to be information, it interrupts the microcomputer 3o and sends an FIF
Control is performed to read the information stored in the O register 28, and the subsequent barcode f! '! Since the II processing is performed by program processing by the microcomputer 30, parts that require high-speed processing can be processed by the hardware circuit of the barcode pattern circuit 29.
Since the microcomputer 30 only needs to perform barcode recognition processing, it can handle the problem satisfactorily. When changing or modifying the recognition logic such as decoding or algorithm, the barcode pattern detection circuit 29 can be used without changing the answer, and the only part to be changed is the program of the microcomputer 3o, so there is no need to rebuild the hardware circuit. This makes changes extremely easy.

In addition, the barcode pattern detection circuit 29 only needs to have a circuit configuration for detecting whether or not it is pattern information, and there is no need to perform barcode recognition processing or character decoding as in the past, so the hardware circuit is not required. The configuration can be simplified.

In the above embodiment, one FIFO register and one microcomputer are used, but the invention is not limited to this. For example, as shown in FIG. 9, two FIFO registers 2 are used.
81.282 and master microcomputer 301,
If a slave microcomputer 302 is provided and the microcomputer 301 controls the switch 71 to alternately load information into each register 281 and 282, it is possible to sufficiently cope with the use of a microcomputer with a slow processing speed. can. In this case, the master microcomputer 301 edits the read data.

In the above embodiment, the clock CLK used by the run length counter to count the character width is set to 1.
Although the clock CLK' whose frequency was divided by /4 was used, it is needless to say that the present invention is not limited to this.

Further, in the above embodiment, a multiplexer was used to select data and data from each latch circuit, but the selection is not limited to this, and the multiplexer is not used to select the data and data from each latch circuit.
A circuit having similar functions can be realized even if an 8/32 multiplier, a 36/32 multiplier, and a 7-bit converter 49.51 are individually provided for each output EO to E3.

Furthermore, in the above embodiment, the return of character width variation is ±1.
Although it is set within 2.5%, this value is not necessarily limited to this, and may be set arbitrarily depending on the conditions.

[Effects of the Invention] As described in detail above, according to the present invention, only the detection of whether or not it is barcode information is performed by hardware processing, and the barcode Him processing is performed by software by a microcomputer. Changes or modifications in the recognition logic can be dealt with by simply changing the program, and it is possible to provide a barcode reading device in which the recognition logic can be changed or modified relatively easily, and the logic circuit configuration of the hardware part can be relatively easily configured. It is something.

[Brief explanation of the drawing]

1 to 8 show one embodiment of the present invention. FIG. 1 is a block diagram including a partial schematic configuration, and the second factor shows a specific circuit configuration of the barcode pattern detection circuit in FIG. 1. 3, 4, and 5 are timing waveform diagrams showing the operation timing of each part in FIG. 2. FIG. 6 is a diagram showing the configuration of the 28/32 multiplier in FIG. Figure 7 is a flowchart showing barcode recognition processing by a microcomputer, and factor 8 shows an example of a barcode, where (a) is a standard version barcode diagram, (b) is a shortened version barcode diagram, FIG. 9 is a block diagram showing another embodiment of the present invention, and FIGS. 10 and 11 are block diagrams showing conventional examples. 22... Laser light source, 25... Light receiver, 26...
Binarization circuit, 27... Run length counter, 28.
... FIFO register, 29... Barcode pattern detection circuit, 30... Microcomputer, 36...
・2 pit counter, 37...decoder, 38-41
...7 pit counter, 43-46...7 pit latch circuit, 47...28/32 multiplier, 48...3
6/32 multiplier, 49.51...7 bit comparator, 50...7 pit latch circuit, 52-63...
JK flip-flop, 66...7 bit converter. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 7 (a) (b) Figure 8 Figure 10 Figure 11

Claims (1)

[Claims] A barcode detection section, a binarization circuit that processes a signal from the barcode detection section and outputs a binary signal, and
A run-length counter that converts a binary signal from the digitizing circuit into run-length data, one or more shift registers that store the output of this counter, and a digitized signal from the binarizing circuit and a run-length counter. a barcode pattern detection circuit that detects a barcode pattern by inputting data from the barcode; and a barcode pattern detection circuit that receives data from the one or more shift registers in response to a barcode detection signal from the barcode detection circuit and recognizes the barcode. Processing 1
or a plurality of microcomputers, and the barcode pattern detection circuit includes a plurality of counters that sequentially perform counting operations in one barcode character period in response to changes in the binary signal, and a plurality of counters for each of the counters. multiple latch circuits that each latch data;
A character width variation detection circuit that detects variations in character width in response to each of the latch circuit outputs and each of the counter outputs; A judgment circuit that makes a judgment; a data holding circuit that holds data obtained by multiplying the data for one character by a certain value when this judgment circuit judges continuity; 1. A barcode reading device comprising a comparison output circuit that compares length counter data and outputs a barcode detection signal when the counter data becomes larger than the holding circuit data.