KR920004419B1 - Interrupt control processing circuit - Google Patents

Abstract

The interrupt signal control circuit processes request signals generated by a number of interrupt sources independently according to the priorities of the request signals. The circuit includes an interrupt source generator (200) for generating interrupt request signals, a clock signal generator (300) for generating interrupt priority clock pulses by receiving the operation clock signal, an interrupt request detector (400) for selecting one interrupt request signal according to the control signal transmitted from the CPU (100), and an interrupt signal generator (500) for synchronizing the selected interrupt request signal to the interrupt priority clock signal and for generating interrupt signal according to the control signal transmitted from the CPU.

Description

Interrupt Control Processing Circuit

1 is a conventional system block diagram.

2 is a circuit diagram according to the present invention.

3 is a waveform diagram of operating parts of FIG. 2;

* Explanation of symbols for main parts of the drawings

100: microprocessor 200: interrupt generator

300: clock generator 400: interrupt request detector

500: interrupt generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control processing circuit in an interface device of a microprocessor, and more particularly, to an interrupt control processing circuit for preventing an error occurring in service in one microprocessor when several interrupts operate independently from each other.

In order to satisfy a plurality of interrupts generated independently from each other and serviced by one microprocessor, as shown in FIG. 1, it is ideal that the microprocessor 10 has interrupt inputs as many as the number of interrupt requests. Even if each interrupt occurs independently at any time, these interrupts are serviced with priority provided by the microprocessor 10 in hardware. For example, if the service priority provided by the microprocessor 10 is INT1> INT2> INT3, INT2 and INT3 are randomly generated, and the interrupt source generation unit 20 requests INT1 from the interrupt source generation unit 20 even during service. If so, the microprocessor 10 stops INT2 or INT3 and prioritizes the service for INT1. When the service of INT1 ends, the service of INT2 or INT3 which has been interrupted continues to be terminated.

Conventional circuits such as the first diagram may be used when one interrupt is being served while another interrupt comes in. When the current interrupt service is finished, the next request may be serviced or when several interrupts are serviced by one interrupt request line. There was an issue that could not service.

Accordingly, an object of the present invention is to provide an interrupt control processing circuit which can prevent the service from being interrupted by priority in processing a request in which several interrupts are independently generated.

It is still another object of the present invention to provide a control processing circuit capable of preventing a request from being lost by processing a request in which several interrupts are generated independently through one interrupt line.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram according to the present invention, which is composed of a microprocessor 100 for controlling a system, an interrupt source generator 200 for generating an interrupt request signal, and a flip-flop FF1-FF3. A clock generator 300 for generating and outputting priority clock pulses respectively, and flip-flops FF21-FF23 and logic gates G11-G13. An interrupt request detection unit 400 for inputting the generated interrupt request signal and selectively outputting one interrupt request signal according to a control signal of the microprocessor 100, a flip-flop FF31-FF33, and a logic gate G21- G23) and (G31), and input predetermined interrupt request signal of the interrupt request detection unit 400 to generate predetermined priority respectively generated by the clock generation unit 300. In synchronization with the above clock signal it is configured as an interrupt generating unit 500 for generating an interrupt signal by the control signal of the microprocessor 100.

In the above configuration, it is assumed that there are three interrupt requests. However, the clock generation unit 300 of the above configuration can be expanded to N flip-flops (FF11-FF1N) to generate N priority clocks, and the interrupt request detection unit. 400 also extends to N flip-flops FF21-FF2N and logic gates G11-G1N, and the interrupt generator 500 extends to N flip-flops FF31-FF3N and logic gates G21-G2N. Can be configured to handle N interrupt requests.

FIG. 3 is an operation waveform diagram of each part of FIG. 2 and one embodiment of the present invention will be described in detail with reference to FIGs.

First, in the present invention, each interrupt has a priority, and an arbitrary request is selected by time priority when several interrupts occur at the same time without interrupting another interrupt request service.

When the operation clock signal as shown in FIG. 3a is applied to the clock terminal of the flip-flops FF1 to FF13, the flip-flop FF-12 outputs the same clock signal as the 3b degree to the output terminal Q and the flip-flop An output terminal Q outputs a clock signal equal to the third c degree, and the flip-flop FF11 outputs a clock signal equal to the third d degree to the output terminal Q.

In addition, the interrupt source generator 200 generates the first interrupt request signal as shown in the 3e-g diagram, and applies the interrupt source clock to the clock position of the flip-flop FF11-FF23 to the first position of each interrupt request signal. . At this time, the interrupt mask MASK signal is applied from the microprocessor 100 to the logic gates G12-G13 to pre-slip the flip-flops FF22-FF23 to prevent the interrupt logic from operating. Accordingly, the interrupt request signal generated by the interrupt source clock generated by the interrupt source generator 200 becomes the first interrupt request signal to the output terminal Q of the flip-flop FF21 and is output. The flip-flop FF31 for inputting the first interrupt request signal output to the output terminal Q of the flip-flop FF21 to the data terminal D is output to the output terminal Q of the flip-flop FF12. The first interrupt signal is generated by the clock signal and output through the logic gate G31. The output first interrupt signal presets the other flip-flops FF32 and FF33.

The interrupt signal operating in the preset manner stops the operation of the flip-flop FF31 by presetting the flip-flop F21 according to the interrupt acknowledge ACK1 signal of the microprocessor 100, and finally the flip-flop F32. ) Is enabled to output the second interrupt signal to the output terminal (Q).

The flip-flop FF32, which inputs the signal output to the output terminal Q of the flop-flop FF22, to the data terminal D, generates a second interrupt signal by the clock signal generated by the flip-flop FF13. It is output through the logic gate G31.

As described above, the interrupt request clock signal generated by the interrupt source generator 200 sequentially outputs the interrupt signal by the clock signal of the clock generator 300 as shown in FIG. 3h. Logical gates G21 to G23, which are not described herein, control not to operate the unselected interrupt request signal. In addition, P1-P4 in FIG. 3 is an interrupt pending time, S1-S4 is an interrupt service time, and INT1-INT3 is an interrupt request source detected by the microprocessor 100.

As described above, in processing request signals generated independently from each other, the interruption of service is prevented by priority, and the processing of multiple requests through one interrupt line can prevent loss of request signals. There is an advantage.

Claims (1)

In an interrupt control processing circuit having a microprocessor (100) for controlling a system and an interrupt source generator (200) for generating an interrupt request signal, a clock for inputting an operation clock signal to generate an interrupt priority clock pulse An interrupt request detector 400 for inputting an interrupt request signal generated by the generator 300 and the interrupt source generator 200 to selectively output one interrupt request signal according to a control signal of the microprocessor 100. And the interrupt request signal output by the interrupt request detector 400 to control the microprocessor 100 in synchronization with a predetermined interrupt priority clock signal generated by the clock generator 300. It consists of an interrupt generator 500 for generating an interrupt signal by the signal Interrupt control processing circuit.

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