JPS61136115A - Basic clock generating circuit of microcomputer system - Google Patents

Abstract

PURPOSE:To decrease the power consumption of a system where plural processing programs are carried out just with a single microprocessor, by securing an automatic switch to a basic clock which is slow enough to satisfy the requested performance when a processing program which suffices for a low speed is carried out. CONSTITUTION:A clock signal e0 on a signal line 10 produced from a clock oscillation circuit 4 is supplied to a dividing circuit 5. Then clock signals e1-en of (n) types of frequencies (n: integer) are delivered from the circuit 5. The signal e1 has the highest speed for actuation of this microcomputer system; while the signal e- has the lowest speed. When an instruction is delivered from a microprocessor 1, the state of this instruction is set to a clock selection register 7 by a data bus signal (a) on a signal line 14 and a clock selection register set instruction signal (g) on a signal line 13 decoded by an instruction decoder 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a basic clock generation circuit used in a microcomputer system.

(Prior Art) In general, the power in a microcomputer system with the same Do path structure D2 increases as the instruction cycle of the microprocessor becomes shorter, that is, as the operation speed increases. Instruction cycles are proportional to the basic clock cycles presented to the microprocessor. This trend is
This is becoming more prominent now that dynamic B, AM and 0M0S logic ICs are being used more and more. The basic clock of a microcomputer system is
It is common to choose values that will be as fast as possible within various limitations such as the microprocessor standard, memory access time, and peripheral circuit operating standards. Among the various types of processing required of the system, in processing that requires high speed, short processing time is a factor that determines high performance.

Even in the same system, there are usually processes that do not require high speed. At that time, it would be possible to reduce the power consumption of the above system if it could be operated at a basic clock cycle commensurate with that.

Such a conventional microcomputer system includes a typical microprocessor 1, a memory and input/output device 2, an initial reset generation circuit 3, and a clock generation circuit 4.

(Problem to be Solved by the Invention) However, very few of the conventional microcomputer systems as described above have a means for switching the basic clock, and even if such a means is provided, it is not possible to switch the basic clock (using a switch, etc.). The disadvantage is that a method is adopted in which the operation of the processor is stopped and specified, and the change cannot be made while the operation is being executed.

An object of the present invention is to provide a system in which a plurality of processing programs are executed by a single microprocessor, and to perform processing that is necessary and sufficient to satisfy the requirements during the execution of a processing program that requires low speed processing. The six microcomputer system basic clocks are configured to eliminate the above drawbacks by automatically switching to a slower basic clock, do not delay the processing time of processing programs that require high speed, and reduce the power consumption of the entire system. The purpose is to provide a generating circuit.

(No Means for Solving the Problems) A basic clock generation circuit for a microcomputer system according to the present invention is applicable to a microcomputer system in which the instruction cycle time of the microprocessor is determined by the basic clock input to the microprocessor. The device is configured to include clock oscillation means, clock selection means, and processing means including the above-mentioned microprocessor.

The clock oscillation means is for generating a plurality of clocks having different frequencies that can be used as basic clocks.

The clock selection means is for selecting any one of the plurality of clocks as a basic clock by executing a specific instruction.

The processing means includes a microprocessor, and when an interrupt request is received, it sends out an interrupt acknowledge signal and uses the clock with the highest frequency among the plurality of clocks as the basic clock.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a microcomputer system to which a basic clock generation circuit for a microcomputer system according to the present invention is applied. , in FIG. 1, 1 to 4 are the same elements as in FIG. 3, and 5 is a frequency divider circuit, a 6-digit clock select circuit,
7 is a clock select register circuit, 8 is an instruction decoder, and 9 is an interrupt acknowledge detection circuit.

In FIG. 1, the clock signal C6 on the signal line 10 generated by the clock oscillation circuit 4 is input to the frequency dividing circuit 5, and
Clock signal e of Shinbo number of fiII class (n: positive integer)
l-en is output from the divider circuit 5. Clock compensation-'
j+eL is the fastest basic clock with which this microcomputer system operates, and clock signal en is the slowest basic clock. When the microprocessor 1 outputs an instruction to select any one of the clock signals e1 to en, the instruction decoder 8 decodes the clock select register set instruction signal g on the signal line 13 and the signal line 14. The state of the instruction output from the microprocessor 1 is stored in the clock select register 7 by the above data bus signal a.

Further, when a signal C indicating that the microprocessor 1 has accepted an interrupt request is output onto the control bus signal line 17, the interrupt acknowledge signal is detected on the signal line 14 by the interrupt acknowledge detection circuit 9. . When the interrupt acknowledge signal is output or when the initial reset signal d is output, the clock select register 7 is set to select the clock e1. The clock select state signal fl-f set in the clock select register 7 is output to the clock select signal line. That is, any one of fl-f becomes active depending on the instruction for selecting the clock, and fl becomes active when an interrupt is accepted and when running after initial reset. The clock el is activated by the active clock select signal.
-en is selected by the clock select circuit 6 and output onto the signal line 12 as the basic clock e. The microprocessor 1 operates according to this basic clock eK.

FIG. #'2 is an explanatory diagram showing the timing of basic clock generation in the embodiment of FIG. 1. In FIG. 2, the clocks e1 to e shown in FIG. 1 are el.

This is an example where n=3 of e2 + e3, and from a state where clock e3 is operating as the basic clock e due to clock select signal f3, clock select signal f! shows the timing at which the clock e1 becomes the basic clock e1.

(Effects of the Invention) As explained above, according to the present invention, in a system in which a plurality of processing programs are executed by one microprocessor, when executing a processing program that requires low-speed processing, the required performance can be satisfied. By automatically switching to a necessary and sufficiently slow basic clock, there is no need to stop the operation of the microcomputer system in response to the required processing speed of the processing program to be executed.
The frequency of the basic clock input to the microprocessor can be selected by programming, which has the effect of reducing power consumption during low-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microcomputer system to which a basic clock generation circuit of a micro combinator system according to the present invention is applied. FIG. 2 is an explanatory diagram showing an example of the timing of basic clock generation in FIG. 1. FIG. 3 is a block diagram illustrating an example of a typical microcomputer system according to the prior art. 1... Microprocessor 2... Memory and input/output device 3... Initial reset generation circuit 4... Clock oscillation circuit 5... Frequency divider circuit 6...
・Clock select circuit 7...Clock select register 8...Instruction decoder 9...Interrupt accrual detection circuit lO~17...Signal line

Claims (1)

[Claims] To generate a plurality of clocks with different frequencies usable as the basic clock in a basic clock generation circuit of a microcomputer system in which the instruction cycle time of the microprocessor is determined by the basic clock input to the microprocessor. clock oscillation means, clock selection means for selecting any one of the plurality of clocks as a basic clock by executing a specific instruction, and sending out an interrupt acknowledge signal when an interrupt request is accepted. 1. A basic clock generating circuit for a microcomputer system, comprising processing means including the microprocessor for selecting the clock with the highest frequency among a plurality of clocks as the basic clock.