KR910005328B1 - Mosaic image generation for tv or vcr - Google Patents

Abstract

The circuit modulates the image data to the mosaic image data with a dual port memory so that the non-educational scene of the adult movie is covered by the mosaic pattern. The method comprises steps; (a) converting the analog signla of the colour difference with sequence of Y, R-Y, B-Y to the n bit digital signal with sequence of R-Y, Y, Y, B-Y, Y, Y and the L bit digital one once more; (b) storing the converted signal to a memory (50); (c) reading the digital signal having the 7th unit corresponding to the 1 horizontal scanning period from the memory repeatedly during the (b) step; (d) convertering and providing the one of read data to the analog signal of the colour difference with sequence of Y, R-Y, B-Y for the 6th period corresponding to the periods for a few dot data.

Description

Mosaic screen generating circuit and method for TV or video tape recorder

1 is a circuit diagram of the present invention.

2 is a data format of the present invention.

* Explanation of symbols for main parts of the drawings

10: keyboard 20: micom

30: A-D converter 40, 41: first and second data conversion unit

50: dual port memory 60: control decoder

70: address controller 80-82: 1-3 D-A converter

SW1: analog switch

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a television (hereinafter referred to as a television) or a video tape recorder (hereinafter referred to as a VTR) in an image processing apparatus, and more particularly to a circuit and a method for converting image data into mosaic image data. will be.

The MOSAIC screen extracts any one dot data among dot data that should be displayed on the dots of the screen among dot data without displaying dot data to be displayed on each dot of the screen. It is to display the image distortion in the form of a mosaic picture by repeatedly displaying on the dots of the predetermined period. The mosaic screen has been broadcast by changing the make-up signal to a mosaic screen in the broadcasting station, but in the TV or VTR As a result, a function of modulating and displaying a normal image into a mosaic image was not possible.

Accordingly, an object of the present invention is to provide a mosaic screen generating circuit and a method for modulating and displaying a normal screen into a mosaic screen on a TV or a VTR.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

)신호 및 리드클럭과 어드레스 및 어드레스제어신호를 발생하는 콘트롤디코더부(60)와, 상기 콘트롤디코더부(60)의 리드/라이트바(이하 R/

라함) 및 리드클럭과 어드레스 어드레스제어신호를 입력하여 어드레스제어신호에 의해 제7소정데이터량을 반복독출 할 수 있고 데이터를 순차적으로 저장할 수 있도록 듀얼포트메모리(50)에 어드레스를 인가하고 저장과 데이터의 저장과 출력을 동시제어하기 위해 리드클럭과 R/

를 동시에 듀얼포트메모리에 인가하는 어드레스제어부(70)과, 상기 제2데이터변환부(41)의 제1출력포트의 디지털 Y 신호 출력을 아날로그 Y 신호로 변환하여 칼러 합성부로 출력하는 제1디지탈-아날로그(Digital-Analog : 이하 D-A 라함)변환기(80)와, 상기 제2디지탈변환부(41)의 제2출력포트의 디지털 R-Y 신호 출력을 아날로그 R-Y 신호 변환하여 컬러 합성부로 출력하는 제2D-A 변환기(81), 상기 제2디지탈변환부(41)의 제3출력포트의 디지털 B-Y 신호출력을 아날로그 B-Y 신호로 변환하여 칼러합성부로 출력하는 제3D-A 변환기(82)로 구성하며, 제2도는 데이터포멧으로 제2도중 MFW는 듀얼포트메모리(50)에 저장된 데이터포멧이고, MFO는 듀얼포트메모리(50)의 출력하는 데이터포멧이며, MFD는 제2데이터변환부(41)의 출력 데이터 포멧이다.1 is a circuit diagram of the present invention, which includes a keyboard 10 for generating a function selection signal for a function selected by a viewer and a microcomputer for controlling the entire system by inputting the function selection signal of the keyboard 10. 20) and an analog-digital (AD) converter 30 for converting an analog color difference signal into a digital signal of a first predetermined bit n, and a switching control signal applied from a switching control signal generator. By the switching operation to sequentially transmit the Y, RY and BY signals, which are the color difference signals of the chrominance separation circuit, to the AD converter 30 and the output of the AD converter 30 by a second predetermined signal. The first data converter 40 converts the digital data of the bit L into a fourth predetermined period, and inputs and stores the output of the first data converter 40 through the first port. Second maintenance by repeatedly reading the data amount of A dual port memory 50 for outputting the read data through a second port and a second port of the dual port memory 500 to convert the data into digital data of a first predetermined bit n. A second data converter 41 for sequentially outputting to the fifth predetermined period or sequentially outputting to the first to third output ports at the sixth predetermined period, and the synchronization separating unit by decoding and decoding the mosaic control signal applied from the microcomputer 20. The first click and the second clock of the ninth predetermined frequency (bfsc) of the eighth predetermined frequency (afsc) applied from the clock divider in accordance with the correction and the vertical synchronization signal applied from the divided by the first and second digital conversion Transmission control signals and reads for controlling the read cycles of the first and second latch signals for controlling the output cycles of the units 40 and 41 and the seventh predetermined unit data amount of the dual port memory 50. / Lightbar (

Control decoder 60 for generating a signal, a read clock, an address and an address control signal, and a read / write bar (hereinafter R //) of the control decoder 60;

And a read clock and an address address control signal to repeatedly read the seventh predetermined amount of data according to the address control signal and apply an address to the dual port memory 50 so that the data can be stored sequentially. Lead clock and R /

First digital output converting the digital Y signal output of the first output port of the second data conversion section 41 into an analog Y signal and outputting it to the color combining section. A second D-A for converting an analog RY signal from a digital RY signal output of an analog (Digital-Analog: DA) converter 80 and a second output port of the second digital conversion unit 41 to an analog RY signal; A converter 81 and a 3D-A converter 82 converting the digital BY signal output of the third output port of the second digital converter 41 into an analog BY signal and outputting the analog BY signal to the color synthesizer. In FIG. 2, MFW is a data format stored in the dual port memory 50, MFO is a data format output from the dual port memory 50, and MFD is an output data format of the second data conversion unit 41. to be.

Accordingly, the present invention will be described in detail with reference to FIGS. 1 and 2.

First, the AD converter 30 and the 1-3D-A converter 80-82 in the first diagram are conventional circuits, and the dual port memory 50 is also a commercially available memory device, the control decoder 60 and the keyboard 10. And the fact that the microcomputer 20 is known, and the first and second data converters 40 and 41 and the address controller 70 can also be implemented by those skilled in the art.

When the viewer operates the keyboard (10) to implement a mosaic screen on the screen by operating the keyboard (10), the keyboard (10) generates a function selection signal for selecting the implementation of the mosaic screen to generate a microcomputer ( 20).

Then, the microcomputer 20 outputs the control signal to the control decoder 60 through a line 101 composed of a control line, a pulse line, and a recognition line together with the data recognition signal by synchronizing a plurality of bits of the screen control signal with the generated pulse signal. do.

신호, 리드클럭, 전송제어신호, 하이 또는 로우 논리상태를 갖는 어드레스제어신호들 중, 제2래치신호의 클럭주기와 어드레스제어신호의 논리상태를 변경시켜 출력한다.In this case, the control decoder 60 recognizes and decodes the screen control signal input in synchronization with the pulse signal from the microcomputer 20 by using the data recognition signal to decode the screen control signal to implement a mosaic screen. The first clock of the eighth predetermined frequency afsc and the second clock of the ninth predetermined frequency bfsc are applied in advance through the horizontal and vertical synchronization signals applied to the two lines 104 and 105 from the synchronization separation unit 102 and 103. The third predetermined number of bits (m) consisting of the first and second latch signals generated by dividing and counting at a plurality of division ratios set, a row address, and a column address, R /

Among the signal, read clock, transmission control signal, and address control signals having a high or low logic state, the clock cycle of the second latch signal and the logic state of the address control signal are changed and output.

In this case, the three selective contacts 106-108 input the analog type luminance signal (hereinafter referred to as Y) and the blue signal (hereinafter referred to as B) -Y and the red signal (hereinafter referred to as R) -Y to the color difference separator. The analog switch SW1 is Y, BY, and RY signals of the three selection contacts 106-108 in the order of RY, Y, Y, BY, Y, and Y according to a switching control signal applied through the line 110. It is sequentially input and transmitted to the AD converter 30 through the reference contact 109. The AD converter 30, which inputs Y, BY, and RY in analog form, input from the reference contact point 109 of the analog switch SW1, converts the signal into a first predetermined number of bits (here, n = 6). The signal is converted into a signal and output to the data converter 40 through the bus line 111.

Then, the data converter 40 converts the digital data of the first predetermined number of bits (n = 6) of the AD converter 30 into a digital data of a second predetermined number of bits (here, L = 4) and controls the decoder. The second predetermined constant (L = 4) input terminal of the dual port memory 50 in the fourth predetermined period through the bus line 113 by latching by the first latch signal applied from the unit 60 through the line 112. The first latch signal is a clock signal having a period 1.5 times faster than the switching period of the analog squelch SW1, and is output to the first port configured of the first port. Is 1.5 times faster than the switching period of the analog switch SW1, which is determined by the ratio of the number of conversion bits of the AD converter 30 to the number of input terminals of the dual port memory 50.

신호중 미리 세팅된 적어도 2회이상의 일정수의 하이논리상태 리드싸이클(Read Cycle)동안은 상기 R/

신호와 함께 버스라인(115)를 통해 인가되는 어드레스중 로우어드레스를 동일하게 유지하도록 제어하고 라이트 싸이클(Write Cycle)이 올때에는 하나씩 증가되는 어드레스 및 라이트 싸이클 동안 0번지에서부터 순차적으로 증가하는 칼럼 어드레스를 갖는 제3소정 비트수(m)의 어드레스와 리드 싸이클 동안은 로우 논리상태를 갖도록 리드클럭을 제어하여 제어된 리드클럭 및 R/

를 버스라인(116)를 통해 듀얼포트메모리(50)의 제어포트로 출력한다.The address control signal of which the logic state is switched is input from the control decoder unit 60 through the line 114, while the address control unit 70 receives the bus line 115 from the control decoder unit 60 by the address control signal. R / authorized through

During the predetermined number of high logic state read cycles, the R /

Controls to keep the same low address among the addresses applied through the bus line 115 together with the signal, and increases the address one by one when the write cycle comes, and the column address which sequentially increases from address 0 during the write cycle. The read clock and R / controlled by controlling the read clock so as to have a low logic state during the address and read cycle of the third predetermined number of bits (m)

Is output to the control port of the dual port memory 50 through the bus line 116.

의 라이트싸이클 동안에 R/

와 함께 인가되는 어드레스에 따라 상기 제2소정비트수(L=4)의 디지털데이터를 제2도 MFW와 같이 로우 어드레스에 해당하는 번지수와 칼럼 어드레스에 해당하는 번지수에 저장하는 반면 콘트롤디코더부(60)으로부터 라인(117)을 통해 제어포트로 인가되는 전송제어신호와 버스라인(116)을 통해 인가되는 R/

리드싸이클에 의해 로우 어드레스에 해당하는 번지내의 제7소정단위의 데이터량을 R/

라이트싸이클 동안 어드레스제어부(70)로부터 버스라인(116)을 통해 제어버스로 인가되는 리드클럭에 의해 제2소정비트수(R=4)단위로 제2포트와 버스라인(118)을 통해 제2데이터변환부(41)로 출력하는데 이때 출력되는 데이터포멧은 제2도 MFO와 같으며 상기 제7소정단위의, 데이터량은 스크린의 1수평주사기간에 해당하는 각 돗트데이터들이다.At this time, the dual port memory 50 for inputting the second predetermined number of bits (L = 4) of digital data from the first data converter 40 through the bus line 113 to the first port is the bus line 116. R / authorized through

R / during the light cycle

According to the address applied along with the second predetermined number of bits (L = 4) digital data stored in the address number corresponding to the row address and the column address, such as the second degree MFW while the control decoder Transmission control signal applied from 60 to the control port via line 117 and R / applied via bus line 116

Read / write the data amount of the seventh predetermined unit in the address corresponding to the row address by the read cycle.

Through the second port and the bus line 118 in the second predetermined number of bits (R = 4) by a read clock applied from the address controller 70 to the control bus through the bus line 116 during the write cycle. The data format outputted to the data conversion unit 41 is the same as that of the MFO of FIG. 2 and the data amount of the seventh predetermined unit is each dot data corresponding to one horizontal scanning period of the screen.

Then, the second data conversion unit 41 for inputting the second latch signal having the changed clock cycle from the control decoder unit 60 through the line 119 receives the second latch signal of the dual port memory 50 through the bus line 118. The second predetermined number of digital data sequentially applied from two ports is converted into Y, BY, and RY digital data of the first predetermined number of bits (n = 6) and latched by the second latch signal whose clock period is changed. Y digital data is transferred to the first D-A converter 80 through the first output port and the bus line 120, and BY digital data is transferred to the second D-A converter 81 through the second output port and the bus line 121. The RY digital data is output to the 3D-A converter 82 through the third output port and the bus line 122. The changed clock period is at least twice as many times as the clock period before the change, that is, the fifth output period. Period (in this case, three times) due to the clock period, the second data converter 41 Ryeokdoen 2 be changed to a data format such as MFO and the third degree MF is generated for the image signal to implement the mosaic image to the screen.

At this time, the 1-3D-A converter 80-82 converts Y, BY, and RY digital data input through the bus lines 120-122 into analog Y, BY, and RY, respectively, to a color synthesis unit. Output via lines 123-125.

As described above, the present invention can display a mosaic screen on a screen by modulating an image signal using a dual port memory, and by implementing the image signal on the screen as a mosaic screen, There is an advantage that can prevent viewing.

Claims (2)

A color difference separator, a frequency divider circuit, a sync separator, a color synthesizer, a keyboard 10 for generating a function selection signal for a function selected by the viewer, and a function selection signal of the keyboard 10 for input to the system In a television or video tape preorder having a microcomputer 20 for controlling the whole and an AD converter 30 for converting an analog color difference signal into a digital signal of a first predetermined bit n, a switching control signal generating unit. An analog switch SW1 for sequentially transmitting the Y, RY, and BY signals, which are color difference signals of the color difference separation circuit, to the AD converter 30 by the switching control signal applied from the AD converter 30; A first data converter 40 for converting the output of the second predetermined bit L into digital data and outputting the fourth data at a fourth predetermined period, and the output of the first data converter 40 to the first port. Of the seventh predetermined unit A dual port memory 50 for repeatedly reading out the amount of data and outputting the read data through a second port in a second predetermined bit unit, and inputting the output of the second port of the dual port memory 50 to a first port; A second data converter 41 for converting the predetermined bit n into digital data and outputting the data at a fifth predetermined cycle or sequentially at the third output port at the sixth predetermined cycle, and applying from the microcomputer 20; The first clock of the eighth predetermined frequency afsc and the second clock of the ninth predetermined frequency bfsc are applied from the clock divider according to the horizontal and vertical synchronization signals applied from the synchronization separator by decoding and decoding the mosaic control signal. To read the first and second latch signals and the seventh predetermined unit data amount of the dual port memory 50 to control the output periods of the first and second digital converters 40 and 41. Transmission control signal and read / The teuba (

Control decoder 60 for generating a signal, a read clock, an address and an address control signal, and the control decoder 60

And inputting a read clock and an address and an address control signal to repeatedly read the seventh predetermined data amount by the address control signal, and apply an address to the dual fork memory 50 so that the data can be stored sequentially. Lead clock to control output simultaneously

1D-A for converting the digital Y signal output of the first output port of the second data converter 41 and the analog Y signal to the color synthesis unit A converter 80, a second D-A converter 81 for converting the digital RY signal output of the second output port of the second digital converter 41 into an analog RY signal and outputting the analog RY signal to the color synthesizer; And a 3D-A converter (82) for converting the digital BY signal output of the third output port of the digital converter 41 into an analog BY signal and outputting the analog BY signal to the color synthesizer. In a television or video tape recorder, the analog color difference signals Y, RY, and BY are converted into digital signals having the first predetermined bit n in the order of RY, Y, Y, BY, Y, and Y. A data storage process of converting a predetermined bit L and storing the same into a memory; and converting a digital signal of a seventh predetermined unit corresponding to one horizontal scanning period out of several randomly in one horizontal scanning period during the data storage process. A data reading process of repeatedly reading from the data, and converting the data read by the data reading process into data of the first predetermined bit, and converting the digital data corresponding to the dot data of the random number of dot data into an arbitrary number of dots. And a data output process of converting and outputting the analog color difference signals Y, RY, and BY at a predetermined period, that is, a sixth predetermined period.

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