KR900006720Y1 - Vignetting compensating circuit for video camera - Google Patents
Vignetting compensating circuit for video camera Download PDFInfo
- Publication number
- KR900006720Y1 KR900006720Y1 KR2019870019978U KR870019978U KR900006720Y1 KR 900006720 Y1 KR900006720 Y1 KR 900006720Y1 KR 2019870019978 U KR2019870019978 U KR 2019870019978U KR 870019978 U KR870019978 U KR 870019978U KR 900006720 Y1 KR900006720 Y1 KR 900006720Y1
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- South Korea
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- signal
- video camera
- output signal
- vignetting
- adder
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
- H04N23/81—Camera processing pipelines; Components thereof for suppressing or minimising disturbance in the image signal generation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/61—Noise processing, e.g. detecting, correcting, reducing or removing noise the noise originating only from the lens unit, e.g. flare, shading, vignetting or "cos4"
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Picture Signal Circuits (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안의 비그네팅 보상회로도.1 is a vignetting compensation circuit diagram of the present invention.
제2도 및 제3도의 (a)~(e)는 제1도 각부의 파형도.(A)-(e) of FIG. 2 and FIG. 3 are the waveform diagrams of each part of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 21 : 모노멀티 12, 22 : 적분기11, 21: monomulti 12, 22: integrator
13, 23 : 클램프 14, 24 : 형형정형기13, 23: Clamp 14, 24: Molding Machine
15, 25 : 버퍼 30 : 가산기15, 25: Buffer 30: Adder
40 : 전압제어증폭기 HS : 수평동기신호40: voltage controlled amplifier HS: horizontal synchronous signal
VS : 수직동기신호 OP11, OP12: 연산증폭기VS: Vertical Synchronization Signal OP 11 , OP 12 : Operational Amplifier
본 고안은 비디오 카메라에 있어서, 줌렌즈에 의하여 발생되는 비그네팅(VIGNETTING)현상 즉, 영상의 중앙부의 밝기에 비하여 주변부의 밝기가 어두워지는 현상을 보상하는 비디오 카메라의 비그네팅 보상회로에 관한 것이다.The present invention relates to a vignetting compensation circuit of a video camera, which compensates for a vignetting phenomenon generated by a zoom lens, that is, a brightness of a peripheral portion becomes dark compared to a brightness of a center portion of an image.
종래에는 비그네팅 현상을 보상하지 않고 비디오 카메라가 촬영한 영상신호를 그대로 출력시켰으므로 모니터 또는 텔레비젼 수상기로 시청할 경우에 화면의 중앙부보다 주변부의 밝기가 어두워 시청자에게 불쾌감을 주는 결함이 있었다.Conventionally, since the video signal output by the video camera is output as it is without compensating the vignetting phenomenon, the brightness of the peripheral part is darker than the center part of the screen when viewing with a monitor or a TV receiver.
본 고안은 이와같은 종래의 결함을 감안하여, 수평 및 수직동기신호를 이용하는 간단한 회로의 구성으로 비그네팅 현상을 보상하게 안출한 것으로 이를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.The present invention is designed to compensate for the vignetting phenomenon in a simple circuit configuration using horizontal and vertical synchronization signals in view of the conventional defects as described above in detail with reference to the accompanying drawings.
제1도는 본 고안의 비그네팅 보상회로도로서, 이에 도시한 바와 같이 수평 및 수직동기신호(HS)(VS)각기HT(여기서, HT는 수평동기신호의 주기임) 및VT(여기서, VT는 수평동기신호의 주기임) 폭의 펄스신호를 출력하는 모노멀티(11)(21)와, 상기 모노멀티(11)(21)의 출력신호를 기준전압(Vref)과 비교증폭하는 연산증폭기(OP11)(OP21)와, 상기 연산증폭기(OP11)(OP21)의 출력신호를 적분하는 연산증폭기(OP12)(OP22), 저항(R11)(R21) 및 콘덴서(C11)(C21)로된 적분기(12)(22)와, 상기 적분기(12)(22)의 출력신호의 최소값이 OV로 되게하는 클램프(13)(23)와, 상기 클램프(13)(23)의 출력신호를 정형하여 포물선파로 만드는 파형정형기(14)(24)와, 상기 파형 정형기(14)(24)에서 출력되어 버터(15)(25)를 통한 신호를 가산하는 저항(R31R35) 및 연산증폭기(OP31)로 된 가산기(30)와, 상기 가산기(30)의 출력전압에 따라 촬영한 영상신호를 증폭하는 전압제어증폭기(40)로 구성한 것이다.1 is a vignetting compensation circuit diagram of the present invention, as shown in the horizontal and vertical synchronization signal (HS) (VS), respectively HT (where HT is the period of the horizontal synchronization signal) and The monomulti 11 and 21 outputting a pulse signal having a width of VT (where VT is a period of a horizontal synchronization signal) and the output signal of the mono multi 11 and 21 are compared with a reference voltage Vref. amplifying operational amplifier (OP 11) (OP 21) and the operational amplifier (OP 11) an operational amplifier for integrating the output signal of the (OP 21) (OP 12) (OP 22), a resistance (R 11) (R 21 ) And an integrator (12) (22) consisting of a capacitor (C 11 ) (C 21 ), a clamp (13) (23) for causing the minimum value of the output signal of the integrator (12) (22) to be OV, and Waveform shapers 14 and 24 that shape the output signals of the clamps 13 and 23 to form parabolic waves, and are added by the waveform shapers 14 and 24 to add signals through butters 15 and 25. The adder 30 includes a resistor R 31 R 35 and an operational amplifier OP 31 , and a voltage control amplifier 40 that amplifies the image signal photographed according to the output voltage of the adder 30.
이와같이 구성된 본 고안의 작용효과를 첨부된 제2도 및 제3도의 파형도를 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the waveform diagram of the second and third attached to the effect of the present invention configured as described above.
제2도 및 제3도의 (가)에 도시한 수평 및 수직동기신호(HS)(VS)가 모노멀티(11)(21)에 입력되면, 모노멀티(11)(12)는 그 수평 및 수직동기신호(HS)(VS)에 따라 제2도 제3도의 (나)에 도시한 바와 같이HT 및VT의 펄스신호를 출력하고, 그 출력한 펄스신호는 연산증폭기(OP11)(OP21)를 통해 증폭된 후 적분기(12)(22)에 입력되어 제2도 및 제3도의 (다)에 도시한 바와같이 적분된다.When the horizontal and vertical synchronization signals HS (VS) shown in FIGS. 2 and 3 are input to the mono multi 11 and 21, the mono multi 11 and 12 are horizontal and vertical. As shown in (b) of FIG. 2 and FIG. 3 according to the synchronization signal HS (VS) HT and The pulse signal of the VT is outputted, and the output pulse signal is amplified through the operational amplifier OP 11 (OP 21 ) and input to the integrators 12 and 22 to (d) in FIGS. 2 and 3. Integrate as shown.
이때, 적분신호의 기울기는 저항(R11)(R21) 및 콘덴서(C11)(C12)의 값으로 결정되며, 그 크기는 최대 값이 OV이다.At this time, the slope of the integrated signal is determined by the values of the resistors R 11 (R 21 ) and the capacitors C 11 (C 12 ), the maximum value of which is OV.
그리고, 적분기(12)(22)의 출력신호는 클램프(13)(23)를 통해 제2도 및 제3도의 (라)에 도시한 바와같이 최저값이 OV로 클램핑되고, 파형정형기(14)(24)를 통해 제2도 및 제3도의 (e)에 도시한 바와같이 포물선파로 정형된 후 버터(15)(25)를 통해 가산기(30)에 입력되어 가산되며, 가산기(30)의 출력신호는 전압제어증폭기(40)의 제어단자에 인가되어 촬영한 영상신호의 증폭도를 조절하게 된다.The output signals of the integrators 12 and 22 are clamped to OV with the lowest values as shown in FIGS. 2 and 3 through clamps 13 and 23, and the waveform shaper 14 ( 24 and after being shaped into a parabolic wave as shown in (e) of FIG. 2 and FIG. 3, it is inputted to the adder 30 through the butters 15 and 25 and added, and the output signal of the adder 30 is added. Is applied to the control terminal of the voltage control amplifier 40 to adjust the amplification degree of the captured image signal.
이때 가산기(30)의 출력전압은 전압제어증폭기(40)에 화면의 중앙부의 영상신호가 입력될 경우에는 낮고, 주변부의 영상신호가 입력될 경우에는 높아 비그네팅이 보상 즉, 화면의 수평측으로는 제2도의 (e)에 도시한 포물선파에 따라 중앙부보다 양측의 증폭도가 높게되고, 수직측으로는 제3도의 (e)에 도시한 포물선파에 따라 중앙부 보다 상하부의 증폭도가 높게 되어 화면의 전체적으로 중앙부보다 주변부의 밝기가 어두워지는 현상을 보상하게 된다.At this time, the output voltage of the adder 30 is low when the video signal of the center portion of the screen is input to the voltage control amplifier 40, and high when the video signal of the peripheral portion is input. The amplification degree of both sides is higher than the center part according to the parabolic wave shown in (e) of FIG. 2, and the amplification degree of the upper and lower parts is higher than the center part according to the parabolic wave shown in (e) of FIG. The brightness of the peripheral area becomes darker.
이상에서 상세히 설명한 바와같이 본 고안은 비디오 카메라로 촬영한 영상신호의 비그네팅 현상을 간단한 회로의 구성으로 보상하므로 화면의 전체에 걸쳐 밝기가 일정하게 되는 효과가 있다.As described in detail above, the present invention compensates the vignetting phenomenon of an image signal photographed by a video camera with a simple circuit configuration, so that the brightness is constant over the entire screen.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870019978U KR900006720Y1 (en) | 1987-07-18 | 1987-07-18 | Vignetting compensating circuit for video camera |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870019978U KR900006720Y1 (en) | 1987-07-18 | 1987-07-18 | Vignetting compensating circuit for video camera |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR890011989U KR890011989U (en) | 1989-07-15 |
| KR900006720Y1 true KR900006720Y1 (en) | 1990-07-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019870019978U KR900006720Y1 (en) | 1987-07-18 | 1987-07-18 | Vignetting compensating circuit for video camera |
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|---|---|
| KR (1) | KR900006720Y1 (en) |
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1987
- 1987-07-18 KR KR2019870019978U patent/KR900006720Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR890011989U (en) | 1989-07-15 |
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