KR900006187B1 - Synchronizing signal generating circuit of digital video signal process for digital audi tape system - Google Patents

Abstract

The generator for recording the synchronous signal on the digital andio tape before recording the digital video signal to identify the video tape includes a video data write enable signal generating circuit (10) generating enable signals for switch signal writing digitised video data stored in a RAM on the digital audio tape, output and initial reset signal of a clock input circuit (11), and synchronus signal writing the data after addressing the memory. With the output of the circuit (10), the synchronous data of 7FFF and 8 are provided from a synchronous signal generating circuit (4).

Description

Synchronization Generation Circuit for Digital Video Signal Processing in Digital Audio Tape System

1 is a block diagram according to the present invention.

2 is a concrete circuit diagram of FIG. 1 according to the present invention.

3 is an audio data distribution waveform diagram of a general digital audio tape.

4 is a digital video synchronization data extraction waveform diagram according to the present invention.

Figure 5 shows the clock waveform from a typical digital audio tape system.

6 is a data recording waveform diagram of a typical digital audio tape system.

7 and 8 are operational waveform diagrams according to the present invention.

* Explanation of symbols for main parts of the drawings

4 synchronization signal generating circuit 5 first selection unit

6: second selector 7: third selector

10: video data recording enable signal generating circuit

11: clock input unit

The present invention relates to a synchronization generating circuit according to digital video signal processing in a digital audio tape system. In general, the technique of digitizing analog signals, storing them in memory, and re-reading them to reproduce them as analog signals is used in HQVTR (High Quality Video Tape Recorder) or video telephone still camera. However, there is no processing technique for recording and reproducing a digital signal on a recording medium for a digital audio tape. In all signal processing, synchronization signals are used a lot, and synchronization and detection are performed in one system. The necessity of the synchronization process is that the original signal can be satisfactorily reproduced in any system at any time during reproduction or reception only when the signal is generated and applied exactly according to the standards and regulations.

It is therefore an object of the present invention to provide a synchronization generating circuit which generates a synchronization signal so as to record a synchronization signal before recording video digital data on a recording medium for a digital audio tape to accurately determine that it is video data.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram according to the present invention, which stores digital data from a clock input unit 11 that receives a clock from a system, and a memory from a random access memory (RAM) storing digitalized video data. Video data for generating a synchronization signal generation enable signal for recording in accordance with a switch signal for recording in " DAT ", an output signal of the clock input unit 11, an initial reset signal, and the memory addressing completion signal. A synchronization signal generation circuit for generating 7FFF and 8 ° data, which are synchronization data, by a write enable signal generation circuit 10, an output enable signal of the video data recording enable signal generation circuit 10, and recording of the video data The signal of the clock input unit 11 is counted from the output enable signal of the enable signal generating circuit 10 to generate the synchronization signal. Synchronization data of the synchronous signal generation circuit 4 by controlling the output of the first counter 8 and the first counter 8 for controlling the output of the furnace 4 to be alternately selected in plural numbers (7FFF and 8 øø). A predetermined number of synchronous data as a count of the output of the first counter 8 from the first selector 5 for selecting one of the outputs and the output enable signal of the video data write enable signal generation circuit 10; And a second counter 9 for controlling a memory address and generating a control signal indicating that data is being written to the digital tape and the output of the second counter 9 according to the output of the second counter 9. A second selector 6 which selects and outputs data output from memory having embedded output synchronization data and video data; and the second selector by outputting the video data write enable signal generation circuit 10; 6, output and digital oh And a third selector 7 for selecting an audio signal output from the analog / digital converter of the video tape.

According to the above configuration, an embodiment of the present invention will be briefly described. A signal generated from the DAT system is input through the clock input unit 11, and a signal according to memory addressing is input to the video data write enable signal generation circuit 10. By operating a selector switch for recording video data on a digital digital audio tape, the video data recording enable signal generation circuit 10 generates an enable signal for recording video data on the tape to synchronize the signal generation circuit 4, Inputs are made to the first and second counters 8 and 9 and the third selector 7. At this time, the synchronization signal generation circuit 4 generates data of 7FFF corresponding to the highest sound of the data distribution used for the digital audio tape recorder and 8 øøø corresponding to the lowest sound. This is a signal for distinguishing the audio from the audio before recording the video data and then clearing it.

The second selector 6 is prepared to select and input the synchronous data as a job before recording video data on the tape, and the third selector 7 selects and inputs the output of the second selector 6. Ready The cleared first counter 8 is a binary count of a predetermined clock of the clock input unit 11 so that the counted output is input to the first selector 5 to be an output of the synchronization signal generating circuit 4. Occurs by alternately selecting 7FFF and 8øøø data twice. Then, the output of the first counter 8 is counted in five digits, and the synchronous data 7FFF and 8 øø outputted by the first selector 5 under control of the second selector 6 by the five-count output. Synchronous data format is made by repeating 16 times (8 8 8 øøø 8 inputs), and memory addressing enable signal and video data stored in the memory are being recorded on the tape through the control stage (CTL, CTL2). Notify generates a control signal. That is, the 16 synchronization data are alternately recorded on the digital audio tape through the selected third selecting unit 7, and the data patterns to be recorded are distinguished from each other so that the video data is recorded. Therefore, when a predetermined number of synchronous data are all input by counting the second counter 9, the second selector 6 selects and selects video digital data read into the memory by an address signal according to the memory addressing enable. The third selection unit 7 records the data on the tape. Since the synchronous data recorded on the tape at the time of reproduction from the tape does not exist in the audio pattern, it is detected as video data upon detection and the video data is reproduced and processed.

)으로 동기신호를 발생하도록 구성된 부분이 동기신호 발생회로(4)에 대응하고, 상기 제1병/직렬 쉬프트 레지스터(41)의 출력단(Qh,

)을 멀티플렉셔(51)의 입력단(A,B)에 연결되도록 구성된 부분이 제1선택부(5)에 대응하고, 상기 제2클럭단(32)의 신호를 디플립플롭(81)의 클럭단(CLK)에 연결되고 상기 익스클루시브 오아게이트(20) 출력단이 클리어단(CLK)에 연결되며 출력단(Q)이 데이타단(D) 연결되어 출력단(Q)으로 입력클럭을 2진카운트하여 상기 멀티플렉셔(51)의 선택제어단(S)에 인가됨과 동시에 출력되도록 구성된 부분이 제1카운트(8)에 대응하며, 상기 제1카운터(8) 디플립플롭(81)의 출력단(Q)이 디플립플롭(91-93)의 클럭단(CLK)에 연결되고 상기 디플립플롭(91-93)의 클리어단(CLK)에 상기 익스클루시브 오아게이트(20)의 출력단이 연결되며 상기 디플립플롭(91-92)의 각 출력단(Q)을 데이타단(D)에 직렬로 연결되어 상기 디플립플롭(91,92)의 출력단(Q)을 앤드게이트(94) 입력단에 연결되고 상기 디플립플롭(93)의 출력단(Q)과 상기 앤드게이트(94) 출력단을 앤드게이트(95)의 입력단에 연결하며 상기 앤드게이트(95)의 출력단을 디플립플롭(96)의 클럭단(CLK)에 연결하며 상기 디플립플롭(96)의 출력단(Q)을 상기 익스클루시브 오아게이트(20)의 입력단에 메모리 어드레스 인에이블 제어단(CTL1,CTL2) 연결되도록 구성된 부분이 제2카운터(9)에 대응하고, 상기 디플립플롭(96)의 출력단(Q)을 멀티플렉셔(61)의 선택제어단(S)에 연결하고 상기 멀티플렉셔(61)의 출력단(Q)을 상기 멀티플렉셔(61)의 A단에 연결하며 메모리로 부터 비디오 데이타단(62)을 B단에 연결하도록 구성된 부분이 제2선택부(6)에 대응하며, 상기 디플립플롭(22)의 출력단(Q)을 멀티플렉셔(72)의 선택제어단(S)에 연결하고 상기 멀티플렉셔(61)의 출력단(Q)을 B단에 연결하며 디지탈 오디오 데이타단(71)을 A단에 연결하여 출력단(Q)을 DAT의 신호처리부로 입력되도록 구성된 부분이 제3선택부(7)에 대응된다.FIG. 2 is a detailed circuit diagram of FIG. 1 according to the present invention, in which 3MHZ is input to the first clock stage 27 and 48KHZ is input to the second clock stage 32 from the DAT recorder system. 48 KHZ, which is the same clock frequency as the input clock of the second clock stage 32, is delayed by 15 clocks, and 48 KHZ delayed by 16 clocks than the input of the second clock stage 32 into the fourth clock stage 25 is obtained. A 96KHZ multiplied by the input clock 48KHZ of the second clock stage 32 is input to the fifth clock stage 26, and the third and fourth clock stages 24 and 25 are exclusive oragates. The first and fifth clock stages 27 and 26 are input to an input terminal of the AND gate 19, and the output terminal of the exclusive oracle 21 is connected to the AND gate 17. And an output terminal of the AND gate 19 to an input terminal of the AND gate 18, and an initial reset signal through the reset terminal 28. 16 is connected to an input terminal of the end gate 16 through an inverter 14 through an addressing completion signal terminal 29, and an output terminal of the end gate 16 is flip-flop. The resistor 31 from the power supply terminal VCC to the set terminal S of the flip-flop 22, and at the same time connect the switch SW1 and The output terminal Q of the flip-flop 22 is connected to the input terminal of the exclusive oragate 20, and the output terminal of the exclusive oragate 20 is connected to the clear terminal CLR of the flip-flop 23. The second clock terminal 32 is connected to the clock terminal CLK of the deflip-flop 23, and the output terminal Q of the deflip-flop 23 is connected to the input terminals of the AND gates 18 and 17. Connected to the output terminal of the end gate 17 and configured to be input to the inverter 15 Corresponding to the call generation circuit 10, the output terminal of the AND gate 18 is connected to the clock terminal CLK of the first and second parallel / serial shift registers 41 and 42, and the output terminal of the inverter 15 is It is connected to the shift / load end SH / LD of the first and second bottle / serial shift registers 41 and 42, and the input terminal ah of the first and second bottle / serial shift registers 41 and 42 is a power supply terminal. Is connected to a VCC and an output terminal Qh of the first bottle / serial shift register 42 is connected to a serial input terminal Sin of the second bottle / serial shift register 41, and the first bottle / serial shift is Output terminal Qh of register 41;

A portion configured to generate a synchronous signal corresponds to the synchronous signal generating circuit 4, and the output terminal Qh, of the first parallel / serial shift register 41,

) Is connected to the input terminals A and B of the multiplexer 51 to correspond to the first selector 5, and the signal of the second clock stage 32 is clocked by the flip-flop 81. Connected to the terminal CLK, the output terminal of the exclusive oragate 20 is connected to the clear terminal CLK, and the output terminal Q is connected to the data terminal D, so that the input clock is binary counted to the output terminal Q. The part which is applied to the selection control stage S of the multiplexer 51 and configured to be output at the same time corresponds to the first counter 8, and the output terminal Q of the deflected flop 81 of the first counter 8. The output terminal of the exclusive oragate 20 is connected to the clock terminal CLK of the deflip-flop 91-93, and the output terminal of the exclusive oar gate 20 is connected to the clear terminal CLK of the deflip-flop 91-93. Each output terminal Q of the flip-flops 91-92 is connected in series to the data terminal D, so that the output terminal Q of the flip-flops 91 and 92 is connected to the input terminal of the AND gate 94, The output terminal Q of the flop 93 and the output terminal of the AND gate 94 are connected to the input terminal of the AND gate 95, and the output terminal of the AND gate 95 is connected to the clock terminal CLK of the flip-flop 96. And a portion configured to connect the output terminal Q of the deflip-flop 96 to the input terminal of the exclusive orifice 20 and the memory address enable control terminals CTL1 and CTL2 to the second counter 9. Correspondingly, the output terminal Q of the deflip-flop 96 is connected to the selection control terminal S of the multiplexer 61 and the output terminal Q of the multiplexer 61 is connected to the multiplexer 61. A portion connected to the A stage and configured to connect the video data stage 62 from the memory to the B stage corresponds to the second selector 6, and the output stage Q of the deflip-flop 22 is multiplexed. 72 is connected to the selection control stage S, the output terminal Q of the multiplexer 61 is connected to the B stage, and the digital audio data stage 71 is connected to the A stage. The portion connected to the output terminal Q to be input to the signal processor of the DAT corresponds to the third selector 7.

FIG. 3 is a diagram illustrating an audio data distribution waveform on a digital audio tape, FIG. 4 is a diagram illustrating a synchronous data waveform according to the present invention, and FIG. 5 is a clock waveform diagram applied to the present invention. It is an input waveform diagram of stages 24, 25, 26, 27, and 32.

(5a) is an input 3MHZ signal example of the first clock stage 27, (5b) is an inverted waveform of (5b),

(5c) is an example of the 48KHZ signal of the second clock stage 32, (5d) is an example of an input signal of the third clock stage 24 by delaying the clock (48KHZ) of the signal (5c) by 15 clocks, 5e) is an example in which the signal 48KHZ of (5c) is delayed by 16 clocks, and is an example of an input signal of the fourth clock stage 25, and (5f) is a clock obtained by multiplying (5c) by the fifth clock stage ( 26) is an example of an input signal, and (5g) is an example of recording synchronization data according to the left and right (L, R) channels.

6 is a waveform of data write operation in DAT according to the present invention, where 6a is an input waveform of the fifth clock stage 26, 6b is an input waveform of the first clock stage 27, and 6c ) Is an example of input data, and 6d is a catch clock in the DAT.

7 and 8 are waveform diagrams for synchronizing operation according to the present invention, where (7a) and (7b) are input waveforms of the third and fourth clock stages 24 and 25, and (7c) is the first clock stage 27. ) Is an input waveform of (7d) is an input waveform of the fifth clock stage 26, (7e) is an output signal of the inverter 15, (7f) is a first, second bottle / series shift register 41 , 42 is an input signal of the clock terminal CLK, 7g is an output waveform of the output terminal Qh of the first parallel / serial shift register 42, and 7h is an inverted signal of 7c above. Catch clock at DAT.

8a is an input signal waveform of the second clock stage 32, 8b is an input signal waveform of the fifth clock stage 26, 8c is an example of output data of the multiplexer 51, 8d) is an output signal of the output terminal Q of the deflip-flop 1, (8e)-(8g) is an output signal of the output terminal Q of the deflip-flop 91-93, and (8h) is an AND gate. An example of the output signal of (95), (8i) is an output signal of the output terminal Q of the flip-flop 96, (8j) is an example of the output of the exclusive oragate 20, (8k) is An example of the input of the clear stage CLR of the flip-flop 22, 8l is an example of the output of the output stage Q of the dip-flop 22, and 8m is an output of the deflip-flop 23. This is an example of output of Q).

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 2-8. The signals (5a) and (5f) of FIG. 5 generated in the DAT system are input to the AND gate 19 and the (5c) signal is flipped. A signal inputted to the clock stage CLK of the flops 23 and 81 and delayed the (5c) signal by 15 and 16 clocks is input to the exclusive oragate 21 to output the output of the deflip flop 23 ( If the state of Q) is latched "high", in the "high" section of the (5f) signal of the fifth clock stage 26, the (5a) signal passes through the AND gates 18 and 19 for the first and second bottles /. The input gate 17 and the inverter 15 are connected to the clock stage CLK of the serial shift registers 41 and 42 by outputting the signals 5d and 5e from the exclusive oragate 21. By setting the shift / load (SH / LD) of the first and second bottle / serial shift registers 41 and 42 through the channel, the synchronization signal to be recorded before storing the video data on the digital audio tape is set for each channel. It generates a signal to be recorded as shown in (5g).

An example in which the reproduced signal is specifically recorded on the digital audio tape is shown in FIG. (6a) If the synchronization data is generated in the "high" section of the signal as shown in (6c) according to the (6b) clock, the data is processed by the signal processor according to the catch clock of the DAT system of (6d) so that the synchronization signal is recorded. . When the data is recorded in the memory section RAM and the DAT recorder enters the recording mode and the switch 30 is pressed, the set stage SET of the flip-flop 22 is set to " low " ) Becomes "high". At this time, the flip-flop 96 is ready to receive the input, the output stage (Q) state is "low", the output of the exclusive oragate 20 is "high", and the flip-flop operating as a binary counter Clearing and enabling the flip-flops 91-93 and the flip-flop 23 operating with the flop 81 and the binary counter.

The deflip-flop 23 latches the data terminal D high VCC according to the clock of 48 KHZ of the second clock stage 32 and outputs it to the output terminal Q and then inputs it to the AND gates 18 and 17. . At this time, the outputs of the AND gates 18 and 17 are connected to the clock stage CLK stage and the shift / load stage SH / LD of the first and second parallel / serial shift registers 41 and 42 according to the clock signal of FIG. 5. It is inputted to the clock stage and generates 7F and 8 [deg.] By the input terminal ah at the first parallel / serial shift register 41, and generates FF and [deg.] By the second parallel / serial shift register 42. When the output of the second bottle / serial shift register 42 is input to the serial input terminal Sin of the first bottle / serial shift register 41, the output terminal Qh of the first bottle / serial shift register 41 is 7FFF. When the output terminal Qh is generated as 8 ° ø 3 and 4 degrees, and the 48KHZ signal of the second clock stage 32 is input to the clock terminal CLK, binary counting is performed at the flip-flop 81. Since the output terminal Q is connected to the selection control stage S of the multiplexer 51, the output of the output terminal Q is input to the A and B stages to be selected and output. When the state of Q is "high", the output of the multiplexer 51 becomes 7FFF, and when "low", the output of the multiplexer 51 outputs 8 ° øø. That is, 48KHZ of FIG. 8 is binary counted in the flip-flop 81, and when generated as shown in (8b), the synchronization data are alternately selected twice such as for each channel (8c) to select the multiplexers 61 and 72 selected above. The generation synchronization data is input to the DAT signal processor through the passage.

On the other hand, the signal of the output terminal Q of the deflip-flop 81 is composed of a five-counter counter and is input to the clock terminal CLK of the de-flip-flop 91-93. After counting all 8 øøø, it exits and outputs it as shown in Fig. 8 (8e-8g) The signals of (8g) and (8f) are drawn from the AND gate 94 and the AND gate 9e. When the output of and the output of the output terminal Q of the deflip-flop 93 are ANDed to the AND gate 95, it is generated as (8h) and is input to the clock terminal CLK of the deflip-flop 96. The output of the output terminal Q of the flip-flop 96 is latched to " high " as shown by 8i, and selects the selection control terminal S of the multiplexer 61 to select and input the synchronous data. When the input video data of the input terminal 62 is prepared and input to the exclusive oracle 22, the output of the exclusive oragate 20 is equal to (8j). This becomes " low " to clear the deflip-flops 23, 81, 91-93, and is inputted as a memory addressing enable signal through the first and second control terminals CTL1 and CTL2 to address the memory. Accordingly, the output data is input to the B of the multiplexer 61 through the video input terminal 62, and the output is input to the DAT signal processor through the multiplexer 72. At this time, the second control terminal CTL2 is connected to the DAT. When the data is being recorded as data and the addressing of the memory is completed and the writing is completed through the multiplexers 61 and 72, the output of the AND gate 16 is output by the input signal of the addressing completion signal stage 29 (81). As shown in the figure, the low flip-flop 22 is cleared, and the output Q of the flip-flop 22 becomes low, so that the multiplexer 72 receives the audio signal received from the DAT recorder. After you've prepared your recording, write it to the tape as digital audio The rock. The synchronous data is not distinguished in the audio signal pattern becomes the synchronous data and video data recorded in the video signal is completed.

As described above, by generating a synchronization signal so that digital video data can be recorded on a digital audio tape and recording it before recording digital video data, it is easy to distinguish from audio during playback, and thus there is an advantage that it can be widely applied to video file management. .

Claims (1)

A circuit for recording video digital data in a digital audio tape recorder system, comprising: a clock input section (11) receiving a predetermined clock from the digital audio tape recorder system, a clock input section (11) receiving a clock from the system, and digitalized A switch signal for recording the stored data from a memory (RAM: Random Access Memory) storing the video data on a digital audio tape (hereinafter referred to as "DAT"), an output signal of the clock input unit 11, and an initial reset. A video data write enable signal generation circuit 10 for generating a synchronization signal generation enable signal for recording in accordance with a signal and the memory addressing completion signal, and an output enable of the video data write enable signal generation circuit 10. A synchronization signal generation circuit 4 for generating 7FFF and 8 ° data of synchronization data by the signal; Counting the signal of the clock input unit 11 from the output enable signal of the video data write enable signal generating circuit 10 to control the outputs 7FFF and 8øø of the synchronization signal generating circuit 4 to be alternately selected. A first selector 5 for selecting one of the synchronous data output of the synchronous signal generation circuit 4 by the first counter 8 and the output control of the first counter 8, and the video data Control to have a predetermined number of synchronous data from the output enable signal of the write enable signal generation circuit 10 to the count of the output of the first counter 8 and to inform the memory addressing and recording of the data to the digital tape. Data output from a memory incorporating the second counter 9 for generating a signal and the output synchronization data of the first selector 5 and the digital video data according to the output of the second counter 3. An analog / digital conversion of the output of the second selector 6 and the digital audio tape by the second selector 6 which selects and outputs a signal, and an output of the video data recording enable signal generation circuit 10. And a third selector (7) which selects an audio signal outputted from the input unit.

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