KR900003586Y1 - Self-timer circuit for camera - Google Patents

Abstract

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Description

Self-timer circuit of the camera

1 is a conventional self-timer circuit.

2 is a diagram illustrating the basic principle of the analog self-timer.

3 is a time relationship and timing relationship of the analog self-timer.

4 is a self-timer circuit diagram according to the present invention.

5 is an operational waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

50: oscillation circuit 60: warning and drive signal generation circuit

70: latch circuit 80: operation warning circuit

90: magnet drive circuit 1: battery

2, 3: power supply and start switch 4, 12: noah gate

5, 14, 16: resistor 6: capacitor

7 Inverter 8, 9 1-2 division circuit

10: counter 13: analog switch

15 light emitting diode 17 transistor

The present invention relates to a self-timer circuit used for automatic shooting of a camera. In particular, the self-timer mode signal, an operation warning display signal, and a shooting driving signal are output by counting a change period of a logic signal. It relates to a self-timer circuit.

In general, the self-timer function of a camera is a function of capturing an image of a subject after a certain time has elapsed when a shutter button is pressed after mounting a film inside the camera. It is also called a function.

Conventional self-timer device having the above object is largely divided into two.

The first is composed of a mechanical device by the operation of a mechanical lever, and the second is divided into a method consisting of a time constant circuit using electrical characteristics.

However, the method of configuration by the mechanical device like the former had to determine the start and end of the operation by the mechanical operation sound by using the mechanical spring force and the gear operation.

Therefore, when the distance is far or the surrounding noise is high, there is uncertainty of judgment, and because a large number of parts must be manufactured precisely, it has been a cost increase factor due to the difficulty of machining.

In addition, the analog self-timer circuit having a time constant circuit as shown in the latter has a battery 100 for supplying a power supply voltage VCC and a power source of the battery 100 as shown in FIG. A reference for generating a reference voltage (V) of a predetermined level by the first switch (S1) for switching, the second switch (S2) for generating the start signal, and the on-switching of the first switch (S1) A time constant part 102 for charging the first and second voltages V1 and V2 in a predetermined state according to the switching of the level part 101 and the first and second switches S1 and S2; The first detection unit 103 for detecting a warning signal by comparing the reference voltage V3 of the reference level unit 101 with the second voltage V2 of the time constant unit 102, and the reference level unit 101 The second detector 104 detects the magnet driving signal by comparing the reference voltage V3 with the first voltage V1 of the time constant 102, and the first detector 103 and 104 detect the magnet drive signal. On signal And a magnet driving and warning display portion 105 for driving (magnetizing) the magnet to display the operation warning state of the self-timer and to operate the mechanism portion (not shown) for the self-timer.

FIG. 2 is a diagram illustrating the basic principle of the analog timer of FIG. 1 and shows only the circuit of the time constant part 102, the battery 100, and the 1-2 switches S1-S2.

At this time, for ease of explanation, the voltage across the capacitor C is divided by the first voltage V1 and the resistors R1-R2, and the voltage adding the first voltage V1 is referred to as a second voltage. .

FIG. 3 is a diagram for explaining the time constant and timing relationship of the analog timer of FIG. 1, and the vertical axis makes reference voltage level by the resistors R7-R8 of FIG. This is the time constant by the resistors R1-R2 and the capacitor C.

The above self-timer of FIG. 1 will be described with reference to FIGS. 2 and 3 as follows.

In the initial operating state, the release is released, so that the first switch S1 is in the off state and the second switch S2 is in the on state.

When the first switch S1 is turned on in the above state, the power supply voltage VCC of the battery 100 is supplied to each part through the first switch S1.

At this time, at the connection node point N1 of the resistors R7 to R8 of the reference level unit 101, the reference voltage V3 having a constant resistance voltage division ratio is generated as shown in FIG. 3, so that each base resistor of the transistors Q2 and Q4 is generated. It is input to each base via (R6) (R11).

When the voltage is generated at the node point N1 of the reference voltage V3 of the reference level unit 101 as described above, the voltage division by the resistors R1-R2 and the capacitor C also occurs at the node point N2 of the time constant unit 102. Voltage is generated.

Since the initial second switch S2 is turned on, the second voltage V of the node point N2 is represented by a voltage having a predetermined level as shown in FIG. 3.

Therefore, as soon as the first switch S1 is turned on, the transistor Q1 of the first detector 103 is turned off, and the collector potential is driven by the magnet in the high voltage state by the resistor R4. And the base of the transistor Q5 of the warning display portion 105.

On the other hand, in the state where the second switch S2 is turned on as described above, as shown in FIG. 3, the both ends of the capacitor V have a potential of almost 0 volts, so that the transistor Q3 is turned off. Maintain state.

Therefore, the transistors Q5 and Q6 have a state of turning off, so that the light emitting diode LED is turned off and a current flows in the magnet coil M, which is not shown. Is magnetized from the beginning to stabilize the mechanism operating state, not shown.

Subsequently, upon release, the second switch S2 is opened to open the capacitor C, thereby charging the capacitor C to a predetermined voltage.

The voltage V1 between the both ends of the capacitor C of the time constant part 102 gradually increases as shown in FIG. 3 so that the second voltage V2 caused by the resistors R1 and R2 becomes a reference by the resistors R7 through R8. When the voltage is greater than the voltage V3, the transistor Q1 is turned on, the transistor Q5 is turned on, the light emitting diode LED is turned on, and a warning display is performed as shown in (200) of FIG.

That is, it turns on after a certain time, and thus alarms that the shooting time has elapsed after a predetermined time has elapsed after the automatic shooting mode is activated.

When the first voltage V1 in the charged state of the capacitor c gradually increases and becomes larger than the reference voltage V3 level, the transistor Q3 is turned on, thereby turning off the transistor Q6.

Therefore, the current flowing in the magnet coil M is cut off, and the magnet (not shown) loses its magnetic force.

At this time, the magnet is operated to release the film by the operation of the mechanism (not shown) and release it at the same time to turn off the first switch S1 to cut off the power supply.

In addition, the second switch S2 interlocked with the release is turned on as in the initial state to prepare for self-photographing.

However, the analog self-timer circuit as described above sets the reference level by detecting the divided voltage by connecting two resistors in series.

Therefore, when using a resistor having an error of 5% in general, the partial pressure residual pressure level has a 5% variation, which affects the first and second detection units 103 and 104.

In addition, since the transistors Q1 to Q4 of the first and second detectors 103 and 104 also have errors of several percent in response characteristics, the first and second detectors 103 and 104 are generally known. As a result of the magnet drive and warning display 105 by the components of the level portion 101, there is a problem that a variation occurs for a set time of about 30-40%.

On the other hand, it was difficult to accurately determine whether the current shooting mode was the self-timer mode at a long distance by performing only the automatic shooting warning display.

Accordingly, an object of the present invention is to generate a logic signal having a change of a certain period when the self-timer mode is selected, and to output a photographing driving signal after outputting an operation warning display signal by counting the predetermined number, and then operating a digital self-timer. In providing a circuit.

Another object of the present invention is to provide a circuit that can display the self-timer mode when selecting the self-timer mode.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.

4 is a circuit diagram according to the present invention, a mode for switching the battery (1) for supplying the power (VCC) and switching for supplying the positive (+) power of the battery (1) to the first power line (VL1) Second power line VL2 receiving positive power (+) of first power line VL1 or negative power of battery 1 by selection switch 2 and mode selection switch 2. Is composed of a start switch (3), a switch (4), a resistor (5), a capacitor (6), and an inverter (7) for selective switching of the power supply according to the release state. An oscillation circuit 50 configured as an unstable multivibrator to oscillate a logic signal of a predetermined period in accordance with the switching to oscillate the mode selection signal and the logic clock, and the first and second division circuits 8, 9, and the counter 10. Is configured to divide the oscillation output of the oscillation circuit 50 into a predetermined state and count a predetermined number to output an operation warning display signal, A warning and drive signal generation circuit 60 for outputting a magnet drive signal as a signal, a latch circuit 7 for latching an operation warning display signal of the warning and drive signal generation circuit 60 to generate a warning generation control signal; And a no-category 12, an analog switch 13, a resistor 14, and a light emitting diode (LED) to output a mode state signal of the oscillation circuit 50 during active switching of the start switch 3 Displaying and outputting an operation warning display when the output of the latch circuit 70 is active and displaying the operation warning circuit 80, the resistor 16, the transistor 17, the magnet driving coil 18 And a magnet driving circuit 90 which is driven by a magnet driving signal of the alarm and driving signal generating circuit 60.

FIG. 5 is an operation waveform diagram of each part of FIG. 4, and shows operation according to the switching states of the power switch 2 and the start switch 3. As shown in FIG.

Hereinafter, the operation of FIG. 4 according to the present invention will be described with reference to the waveform diagram of FIG. 5.

In order to perform auto-shooting now, turn on the power switch 2, that is, the self-mode selector switch at point P of FIG. 5, and the positive power of the battery 1 is changed to the first power line VL1, negative ( Power is supplied to the second power line VL2.

At this time, in the normal state, the start switch 3 is connected to the first power supply line VL1, and a positive voltage is input to each of the input terminals 4a and 12a of the noaque 4 and 12, respectively.

Therefore, the input node point N1 of the inverter 7 becomes the logic of the low state, and the no-category 12 outputs the logic low value so that the light emitting diode 15 may be turned off.

When the start switch 3 is switched from the first power line VL1 to the second power line VL2 by pressing the release button of the camera in the above state, the resistor 5 and the capacitor ( 6) After a predetermined time, the node point N1 becomes a logic “high” and is input to the inverter 7 and the input terminal 12a of the no-cause 12 becomes a low state. The signal “high”, which is attenuated by the resistor 14, is input to the anode of 15).

Therefore, when the start switch 3 is switched as shown in FIG. 5B, the inverter 7 outputs a signal by the period of the RC time constant by the resistor 5 and the capacitor 6 to FIG. 5C. As shown in FIG. 5 (J), the oscillation output is performed, and the light emitting diode 15 emits light by the output of the NOA gate 12 to operate in the current automatic photographing mode MODS.

At this time, the light emitting diode 15 has a state of continuously lighting.

On the other hand, the oscillation output of FIG. 5C output from the inverter 7 is input to the input terminal 13a of the analog switch 13 in which the current state is disabled, and divides the input. It is input to the 1 division circuit 8.

The first divider circuit 8 inputs the signal of FIG. 5D, which divides the oscillation output of FIG. 5C, into the second divider circuit 9, and the second divider circuit 9 This is again divided into predetermined amounts to input the signal of FIG. 5E as a clock of the counter 10.

Accordingly, it can be seen that the clock signal inputted to the clock terminal of the counter 10 is a signal having a period of a predetermined state generated by the oscillation circuit.

The counter 10 that inputs the predetermined divided clock output from the second divider circuit 9 outputs data in a state of incrementally counting to the output terminals Q0-Q9 by counting the decimal number.

When the counter 10 counts a predetermined number of clocks and inputs a counting pulse as shown in FIG. 5 (F) to the latch circuit 70 as an operation warning pulse by the output terminal Q6 before completion of the decimal counting, The latch circuit 70 latches the operation warning display signal of the counter 10 and outputs a logic high voltage signal as shown in FIG. 5H as a control signal of the analog switch 13.

At this time, the analog switch 13 is enabled and the oscillating output signal of the inverter 7 input to the input terminal 13a is inputted to the other end 12b of the noar gate 12 as shown in FIG. The counter 10 continues to count the divided output of the second frequency division circuit 9.

Therefore, the noah gate 12 which is outputting a high state signal by inputting the negative power supplied to the second power line VL2 to the one input terminal 12a receives the operation warning display signal from the counter 10. After outputting as shown in FIG. 5F, the output oscillation pulse of the inverter 7 is supplied to the anode of the light emitting diode 15 through the resistor 14.

At this time, the light emitting diode 15 blinks by the clock pulse of FIG. 5 (J) to display that the self-timer operation time is reached.

As described above, the counter 10 also increases and outputs the output of the second frequency dividing circuit 9 even when displaying that the light emitting diode 15 is blinking and the operating time is reached.

When the counter 10 completes the decimal counting and the output of the output terminal Q9 transitions to the high state at the point P2 of FIG. 5G, the high state is the resistance 16. The magnet driving signal as shown in FIG. 5 (K) is input to the base of the magnet driving transistor 17 as a photographing driving signal.

As a result of the " turn on " of the transistor 17, a current flows in the magnet driving coil 18, thereby magnetizing a magnet (not shown) and mechanically stabilizing the mechanism for the self-timer.

As described above, when the magnet driving signal is input to the base of the transistor 17 through the resistor 16, the pulse of the dividing output of the second frequency dividing circuit 9 goes to the falling edge at the point P3 of FIG. Then, the output of the output terminal Q9 of the counter 10 becomes low as shown in FIG. 5 (G).

At this time, the magnet driving transistor 17 is also turned off at the point P3 in FIG. 5 so that the magnet (not shown) loses magnetic force and drives the self-timer mechanism.

The release of the mechanism is driven by the change of the magnetic force of the magnet to release the automatic shooting, and the start switch 3 connected to the release unit is connected to the first power line from the second power line VL2. Switching connection to VL1.

Therefore, the oscillation operation is stopped and the output of the inverter 7 outputs a signal of a stable level, and the output of the counter 10 is stopped.

At this time, the counter 10 and the latch circuit 70 can be cleared by using the return switch of the start switch 3 by disassembly of the release unit, so that a self-timer circuit capable of performing continuous operation can be sufficiently configured.

As described above, the present invention adopts the automatic shooting mode state and the method of the general-purpose device to detect a certain time without error and display the automatic shooting mode state and the operation warning state so that stable automatic shooting can be performed and at the same time integrated. There is an advantage in reducing costs.

Claims (3)

A battery 1 capable of supplying a predetermined first power supply and a second power supply to the first and second power lines VL1 and VL2, and one end of the battery 1 connected to the first power output terminal of the battery 1. A power switch 2 connected to a power line VL1 and switched by a predetermined operation to supply the first power to the first power line VL1, and the first and second power lines VL1 by a predetermined switch. A self-timer circuit having a start switch 3 for selectively outputting a voltage of VL2 to an output contact, wherein the power switch 1 is switched to a predetermined state and the start switch 3 is switched to a second power source. The oscillation circuit 50 is switched and connected to the line VL to oscillate a logic clock having a mode selection signal and a predetermined period when the second power supply is input from the output point, and a logic clock of the oscillation circuit 50 is predetermined. Output operation warning signal and count up A warning and driving signal generating circuit 60 for outputting a photographing driving signal and a mode selection signal of the oscillating circuit 50 display the operation state of the self-timer and the warning of the operation of the driving signal generating circuit 60. An operation warning circuit 80 which performs an operation warning display by erasing a display display of an operation state by an oscillation cycle of the oscillation circuit 60 by the output of a display signal; and the warning and drive signal generation circuit 60 and an operation warning. A latch circuit 70 connected between the circuits 80 to latch the operation and warning display signals of the warning and drive signal generation circuits 60 and output them as warning generation control signals of the operation warning circuit 80; And a magnet driving circuit (90) for driving the magnet by the photographing driving signal output of the driving signal generating circuit (60). The oscillator circuit 50 according to claim 1, wherein the oscillator circuit 50 is connected in series between an inverter for inverting and outputting a predetermined logic state of the input node N1, and an output terminal of the inverter and the input node N1 to perform a predetermined charge / discharge operation. The signal of the negative node and the capacitor and the connection node N2 between the resistor and the capacitor are input to one side input, and the output of the output contact of the start switch 3 is the other end input so that the negative logic signal is input to the input node N1. It consists of a first nodal gate outputting with the input logic of the non-stable oscillation operation by the switching of the start switch (3) to the continuous logic clock to the warning and drive signal generation circuit 60 and the operation warning circuit (80) Self-timer circuit, characterized in that for outputting. 3. A predetermined first and second operation according to claim 2, wherein the operation warning circuit (80) is enabled by a predetermined control signal to pass an output of the inverter and the switching of the start switch (3). And a second negative logic gate configured to input a power supply and a passing output of the analog switch and output an operation warning display signal according to a passing output voltage of the analog switch. Timer circuit.