JP3129767B2 - Oscillation stop detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation stop detecting circuit which operates by an oscillation clock signal and can detect when the oscillation stops.

[0002]

2. Description of the Related Art Conventionally, in the field of electronic timepieces and the like, when oscillation stops, the electronic timepiece also stops, so it has been necessary to immediately detect the stoppage of oscillation and take measures. Some electronic devices need to detect the presence or absence of a clock signal. For example, in the technique described in JP-B-63-45124, oscillation is stopped depending on whether or not the level change is continued by detecting a level change (rising / falling) of the oscillation signal. An oscillation stop detection circuit that determines whether or not the oscillation is stopped is disclosed. FIG.
FIG. 1 is a configuration diagram of an oscillation stop detection circuit according to the above-described conventional technique. In the circuit of FIG. 3, (A) is an output clock of the oscillator. When the clock is input, the output of the inverter 11 rises and falls because of the capacitor 12. This output is waveform-shaped by an inverter 13 and input to an exclusive-OR (EOR) gate 14 as an input (C). The output (C) input to the EOR gate 14 has a certain time delay compared to the clock (A). Therefore, the output (D) of the EOR gate 14 becomes a pulse signal when the clock (A) rises and falls, and does not output when there is no change, that is, when the oscillation is stopped. As a result, the capacitor 19 is discharged through the MOSFET 15 by turning on the MOSFET 15 when oscillating, while the MOS 19 is turned off when the oscillation is stopped.
Since the FET 15 is OFF, the capacitor 19 is charged by the current from the power supply VSS. Therefore, when the signal (D) arrives constantly, that is, when the level of the oscillation signal changes and oscillation continues, the signal (G) does not reach the predetermined potential and the detection signal (H) does not reach the predetermined potential. Is not output. However, when the signal (D) stops reaching,
Since the capacitor 16 continues to be charged by the resistor 16,
At a certain point, the signal (G) reaches a predetermined potential, and the detection signal (H) is output.

[0003]

In the circuit shown in FIG. 3, the charge of the capacitor 19 must be discharged by the signal (D). However, since the pulse width of the signal (D) is extremely narrow, the charge of the capacitor 19 is reduced. In order to sufficiently discharge, it is necessary to reduce the size of the capacitor 19. However, when the capacitor 19 is made smaller, the charging time is shortened, so that there is an inconvenience in circuit adjustment that the value of the resistor 16 must be made larger. Further, since it is considered that the pulse width of the signal (D) varies, there is a trouble in stabilizing the operation. Further, since a circuit for detecting a level change is required, the circuit becomes complicated, and the circuit scale becomes large, resulting in an increase in cost. Further, since a current flows through the resistor 16 and the MOSFET 15 during the output of the signal (D), there is a problem that current consumption increases. An object of the present invention is to solve these conventional problems, to simplify the circuit,
Another object of the present invention is to provide an oscillation stop detection circuit which can perform stable operation and consumes less power.

[0004]

In order to achieve the above object, an oscillation stop detecting circuit according to the present invention comprises a capacitor (4 in FIG. 1) having one end and the other end of a first MOSFET.
(1) and via the second MOSFET (5)
Connected to a constant potential, the first MOSFET and the second M
OSFETs are alternately driven by the clock signal from the oscillation circuit
Charging means for turning on and charging;
And the other end, and the clock signal
Either one end or the other end of the capacitor is connected to the charging means.
When charged to a predetermined voltage via the
Means for discharging in synchronization with a clock signal;
One of the potentials at one end or the other is
Oscillation stop detection signal when the specified threshold potential is reached
Means (8) for generating the discharge, and
In the structure of the first MOSFET and the second MOSFET,
High due to the forward direction of the parasitic diode (9, 10)
It is characterized by starting from a low voltage.

[0005]

In the present invention, since the clock signal of the oscillation circuit repeatedly outputs a high level and a low level potential at a constant period, a predetermined potential is alternately connected to both ends of the capacitor as long as the repetition continues. After that, the charge is discharged. When the operation of the oscillation circuit is stopped, the clock signal is held at the high level or low level potential, so that the discharge potential of the capacitor falls according to the time constant curve of the capacitor and the resistor, and falls below a predetermined threshold potential. When this happens, the oscillation stop detection output is supplied. As a result, an oscillation stop detection circuit that is simple in circuit, has stable operation, and consumes less power can be realized.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram of an oscillation stop detection circuit showing one embodiment of the present invention. In FIG. 1, A is a clock signal generated by oscillation. The clock signal A is input to the inverter 3, the gate of a P-channel MOSFET (PMOS) 1, and the gate of an N-channel MOSFET (NMOS) 2, respectively. The output of the inverter 3, that is, the signal E
Is another set of P-channel MOSFET (PMOS) 5
And the gate of an N-channel MOSFET (NMOS) 6. The sources of the PMOS 1 and the PMOS 5 are both connected to GND. This allows
A set of PMOS1 and NMOS6, a set of PMOS5 and NMOS
The pair 2 performs the opposite operation such that if one is on, the other is off . At the circuit contact B, the drain of the PMOS 1, the drain of the NMOS 2 and one end of the capacitor 4 are connected.
Is input to In the circuit contact C, a PMOS
The drain of NMOS 5, the drain of NMOS 6, and the other end of capacitor 4 are connected, and their combined output is similarly input to NOR gate 8. NMOS2 and NMOS6
Source is connected to the circuit contact D, it is further connected with one end of the resistor 7. The other end of the resistor 7 is connected to a power terminal V
SS (here, negative potential). Parasitic diodes 9 and 10 formed by the drains of PMOS 1 and PMOS 5 are virtually connected to circuit contacts B and C, as shown in FIG. The present invention is provided with such a circuit configuration, and includes one of the capacitors 4 and the other.
Are the drains of PMOS1 and NMOS2 or PMOS
5 and are alternately connected to a predetermined potential via the drain of the NMOS 6. When one is connected to a predetermined potential, the other is connected to a discharge circuit, so that a detection signal is generated when the potential of each terminal of the capacitor 4 reaches a predetermined threshold potential.

FIG. 2 is a timing chart of each signal in the circuit of FIG. The operation of the present invention will be described in detail with reference to FIGS. When the signal A is at a low level (L), the PMOS 1 and the NMOS 6 are ON and the PMOS 5 and the N
Since MOS2 is turned off, the current changes from GND to PMO
Through S1, capacitor 4, and NMOS 6 (-)
It flows to the power supply terminal VSS. At this time, as shown in FIG. 2B, the circuit contact B has the GND potential, and similarly, one end of the capacitor 4 also has the GND potential. On the other hand, the potential of C is temporarily raised to a potential slightly higher than GND by the potential of the capacitor 4 as shown in C of FIG. This potential is about 0.5 to about forward voltage of the parasitic diode 9.
0.6V. However, after that, since the electric charge of the capacitor 4 is discharged by the resistor 7 through the NMOS 6, C
Is gradually lowered in the time constant curve of the discharge by the capacitor 4 and the resistor 7. Next, the signal A becomes high level (H).
In the case of, the operation is almost the same as the case of L described above,
The connection points B and C have the opposite potentials, and the connection point C has the GND potential, whereas the potential of B is temporarily raised to a potential slightly higher than GND (the forward voltage of the parasitic diode 10). After that, it gradually falls along the discharge time constant curve (see FIG. 2). As described above, when the signal A is H, the connection point B gradually decreases toward the (−) VSS potential, and when the signal A is L, the connection point C gradually decreases toward the (−) VSS potential. I do.

As shown in FIG. 2, when the oscillation continues, the signal A repeatedly changes between H and L at a certain period.
In this case, the potential of the circuit contact B or C gradually decreases alternately according to the time constant curve of the capacitor 4 and the resistor 7, but before reaching the predetermined detection voltage of the NOR gate 8 (see FIG. 2). Return to This is because the time constant of the capacitor 4 and the resistor 7 is sufficiently longer than the period of the signal A. Therefore, the output F of the NOR gate 8
Keeps the state of L as shown in FIG. 2, and the oscillation stop detection signal is not output. Next, when the clock of the signal A is stopped and the state of H or L is continued for a long time, the potential of the circuit contact B or C is changed by the time constant curve of the capacitor 4 and the resistor 7 as shown in FIG. To keep discharging,
After a lapse of a certain time, the voltage reaches the predetermined detection voltage of the NOR gate 8. As a result, the detection output F of the NOR gate 8 becomes H
Therefore, it can be determined that the oscillation has stopped.

In the present invention, (a) the operation is stable because the time constant of the capacitor and the resistor for detecting the oscillation stop is determined by the clock cycle and the time required to reach the predetermined detection voltage. (B) Since the discharge starting voltage starts from a point higher by the forward voltage of the parasitic diode, the time constant of the capacitor and the resistor has an effect of increasing apparently, and the time constant must be reduced. Can also.
Further, (c) the circuit of the present invention has a simple circuit configuration and is advantageous in cost. (D) In the circuit, there is no path through which current constantly flows during switching, so that power consumption can be reduced.

[0010]

As described above, according to the present invention,
An oscillation stop detection circuit which is simple and stable in circuit and consumes less power can be realized.

[0011]

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an oscillation stop detection circuit showing one embodiment of the present invention.

FIG. 2 is a timing chart of each signal in FIG.

FIG. 3 is a configuration diagram illustrating an example of a conventional oscillation stop detection circuit.

[Explanation of symbols]

 1,5 P-channel MOSFET 2,6 N-channel MOSFET 3 Inverter 4 Capacitor 7 Resistance 8 NOR gate 9,10 Parasitic diode A Oscillation clock signal B, C NOR gate input connection point D NMOS drain connection Point F Oscillation stop detection output VSS (-) Power supply terminal GND Ground terminal

Claims (1)

(57) [Claims] 1. One end and the other end of a capacitor , respectively.
Via a first MOSFET and a second MOSFET
Connected to a predetermined potential, the first MOSFET and the second
Alternating MOSFET by clock signal from oscillation circuit
A charging means for turning on and charging the power supply, and one end and the other end of the capacitor,
Signal at either end or the other end of the capacitor
One of them is charged to a predetermined voltage via the charging means
Sometimes the other hand is discharged in synchronization with the clock signal.
And a potential at one end or the other end of the capacitor.
Reaches a predetermined threshold potential due to discharge
And means for generating an oscillation stop detection signal, the discharge
Of the first MOSFET and the second MOSFET
Voltage higher by the forward direction of the parasitic diode due to the structure
An oscillation stop detection circuit characterized by starting from the start .