JPS6036644B2 - oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to oscillator circuits used in digital circuits, particularly integrated circuits for electronic watches.

CMOS (complementary MOS) circuits are often used as integrated circuits for electronic watches in order to reduce power consumption.

The oscillation circuit that determines the reference period also often uses a crystal oscillator for reasons of miniaturization and ease of assembly. However,
In dry cell-powered digital watches, most of the total power consumption is consumed by this crystal oscillator, so in order to extend the battery life, it is best to keep the power consumption in this oscillation circuit low. There are many advantages to having a smaller power supply, such as smaller and lighter power supplies and less time and effort to replace batteries. In the crystal oscillation circuit of conventional electronic timepieces, the configuration shown in FIG. 1 is generally used.

That is, terminals 1 and 2 are connected to both ends of a crystal resonator (not shown), and P-channel FETQ, N-channel FETQ act as a resistance circuit in parallel between these terminals 1 and 2.
2, a P-channel FETQ acting as an inverter,
An N-channel FETQ is formed.

The resistance circuit is Q. The sources and drains of Q and Q2 are commonly connected and connected to terminals 1 and 2, respectively, and the gates of Q and Q2 are connected to power supply voltages Vss and Q2 so that they are always on.
Voo is supplied, and the on-resistance of these FETQ, Q2 is utilized. In addition, an inverter circuit that is formed in parallel with this resistor circuit and inverts the signal from terminal 1 to terminal 2 connects the gates of FETs Q3 and Q1000 to terminal 1, and connects Q3 and Q between the power supplies Voo and Vss. They are connected in series and the connection point between Q3 and Q is connected to terminal 2 and used as an output end. Note that a waveform shaping circuit 3 consisting of a frequency divider or an inverter connected in series in multiple stages is connected to the output end of this crystal oscillator circuit, and the shaped pulse output of this circuit 3 is clocked to the required part of the clock circuit. We are trying to supply it as such. These crystal oscillation circuits have a lot of power loss, and as mentioned above, most of the total power consumption in digital watches is consumed by this oscillation circuit.

This is because the voltage required for oscillation when the power is turned on is significantly higher than the voltage required during stable oscillation, and this causes power loss in the oscillation circuit during stable oscillation. This is because it occurs. In other words, in an oscillation circuit like the one shown in Figure 1, the inverter performs a feedback amplification action,
During a transient period when the oscillation state is unstable and reaches steady oscillation, such as when the power is turned on, starting power is required to increase the amplification of the inverter that performs this feedback amplification function and lead to stable steady oscillation. Once it enters a stable oscillation state, it does not require that much power. Now, the power supply voltages (Voo and Vss) required to start oscillation when the power is turned on are
If the voltage difference between the
rt>Vhold...
...There is a relationship of (1}.

In particular, in order to start oscillation promptly, Vsta
Must be sufficiently larger than Vhold.
Therefore, when the secondary oscillation circuit is designed to quickly and reliably perform stable oscillation, the loss of power consumption is large and the battery life cannot be extended. This invention was made in view of the above circumstances, and is an improved oscillator that eliminates power consumption loss in an oscillator consisting of a passive circuit and an active circuit, and extends the battery life of small electronic devices including oscillators such as electronic watches. The purpose is to provide circuits. Embodiments of the present invention will be described below with reference to the drawings. The embodiment circuit shown in FIG. 2 includes terminals 1 and 2 to which signals XT and XT are input from a crystal resonator, FETs Q, Q2 that act as a resistance circuit, FETs Q3 and Q4 that act as an inverter, a frequency divider, an inverter, etc. A waveform shaping circuit 3 is a part of a CMOS integrated circuit device connected and formed in the same manner as the conventional circuit shown in FIG.
A crystal resonator (not shown) is attached externally to the crystal resonator. Power supply VD. The inverter consists of FETs Q3 and Q4 formed in series between P-channel FET Q3 and Vss, and a current-limiting resistor R,
is connected, and a current limiting resistor R2 is connected between the N-channel FET Q4 and the power supply Vss. Also,
The waveform shaping circuit 3 shapes the pulse signal (or frequency divides it) and outputs a stable oscillation signal to the frequency dividing circuit, and is also connected to the oscillation detection circuit 4 to input the oscillation output of the crystal resonator. . In this oscillation detection circuit 4, if the input oscillation is in a normal state, the output Q is "0" (low level); otherwise, when the oscillation is not oscillating or the oscillation output is insufficient, the output Q is "1" ( (high level), and an example of its circuit configuration will be described in detail later. The output Q of the oscillation detection circuit 4 is supplied to the gate of the P-channel FET via an inverter 5, and directly to the gate of the N-channel FET Q6.
are respectively the above FETQ and Q4 as switching elements.
The power supply Voo is formed in parallel with R, , R2 on the Vss side.

In the oscillation circuit configured in this way, a current limiting circuit is added to the inverter that performs the feedback amplification function of the conventional circuit, and the added resistance value is as follows.

RP: Vine main (transparent ‐‐‐‐‐‐(21RN)
= Hot day hair seal ... In other words, the FET formed as a switching circuit has a resistance value of Q6 of R (Toshi), R (
Q), the resistance value added at the end of the current between the inverter and the power supplies VDo and Vss is
It can be expressed as P and RN.

Therefore, when first turning on the power and starting eye excitation vibration in the crystal resonator, the output Q of the oscillation detection circuit 4 is "
1'', the FET Q6 is on, that is, in a conductive state. In these FETs, if the on-resistance of Q is set to a sufficiently small value, then ■, RP of the '3' formula,
Since RN becomes R(Q)→0 and R(Q6)→○, both approaches zero. In this way, the power supply voltage Voo-Vss is applied almost as is to the inverter made up of FETs Q3 and Q4, and the oscillation state is quickly stabilized. The oscillation output of the crystal resonator that oscillates stably is generated by the waveform shaping circuit 3.
Since the waveform is shaped by , the input to the oscillation detection circuit 4 is reduced.
At this time, the output Q of the oscillation detection circuit 4 changes from "1" to "0" and the FET turns off Q6.

Therefore, in the above ■, RP and RN of formula 3' are R (Q5) →
, R(Q6)→, so R. , R2, and due to the voltage drop here, FETQ3, Q4
The operating voltage of an inverter consisting of the following can be made sufficiently small.
The oscillation detection circuit 4 will be explained with reference to FIG.

Signal to detect? The input mode 11 is connected to one terminal of the capacitor 2 and the anode terminal of the diode 13, and the capacitor 12 and the diode 13 are connected in parallel. The other terminal of the commonly connected capacitor 2 and the cathode terminal of the diode 13 are connected to an output Q terminal 16 via an inverter 14 and an inverter 5 in this order. The input terminal J of the inverter 4 is connected to a high-level power supply Voo through a resistor 17, and the output terminal of the inverter 5, that is, the Q terminal 16, is connected to Voo through a capacitor 8. . connected to. In addition, the rear inverter 15
are P-channel FETQ, . and N-channel FETQ, 2
are connected in series, with Q,2 being connected to the high level power supply VDo via a resistor 19, and Q,2 being directly connected to the low level power supply Vss. This detection circuit 4 converts the number of output pulses of the waveform shaping circuit 3 into a voltage level, and it will be clear from the following explanation that when this number of pulses exceeds a predetermined value, a detection signal is output from the detection circuit 4. . Fourth
The figure shows the input and output waveforms of this oscillation detection circuit when the power is turned on. Figure a shows the voltage waveform of the input terminal 11 to which the signal ◇ to be detected is input, and figure b shows the voltage waveform of the input terminal J of the inverter 14. The voltage waveform (c in the figure) is the voltage waveform at the output terminal 16, and the time when this waveform first reaches the "0" level is the normal oscillation detection timing. The input signal remains at a constant level of "1" or "0" until the output of the waveform shaping circuit 3 returns to a normal oscillation state shortly after the power is turned on. During this time, the capacitor 12 is connected to the resistor 17 from the connection point J side.
It is charged to the power supply VDo level, that is, "1" through the power supply VDo level.
And this "1" level of J is inverter 14, 15
, and the oscillation detection output is “1”.
”Hold the level. (In other words, it is detected that there is no oscillation state.) Note that even if the input signal level continues to be at the "0" level, the connection point J may become the "0" level due to the reverse bias effect of the diode 13. There isn't. Thereafter, when the input signal J becomes a pulse with a constant period, a pulse signal of approximately the same phase also appears at the connection point J through the capacitor 12. Of course, for this purpose, capacitor 12 and resistor 1 are required.
7 and V. . Input the discharge time constant for the side signal? It should be set sufficiently larger than the period of the pulse applied as . The pulse signal obtained at the connection point J is transmitted to the output terminal 16 by the inverters 14 and 15, and at this time, the level on the output terminal 16 side of the capacitor 18 is equal to the power supply Vss.
The battery is charged to the "0" level. In this case, the Voo side FETs Q, . Because of the resistor 19 connected in series with the capacitor 8, the discharging time constant is sufficiently large (several 1 M) compared to the charging time constant of the capacitor 8 and the period of 0”
become. In this way, if the input signal is in a normal oscillating signal state, the detected output signal Q is held at "0", and otherwise, Q is set to "1". By turning on and off the FET Q6 connected to the inverter as a switching element in FIG. 2 by the output of the oscillation detection circuit 4, the above {
2', when the resistance value of the current limiting circuit shown by the tide equation is zero and R.
Alternatively, it can be switched to R2. In other words, the oscillation detection output Q
If it becomes "0" and is oscillating normally, then the FET
Q5 and Q are turned off and the voltage supplied to the inverter is VD.
It becomes much smaller than D-Vss. The voltage at this time is V
If it is set to hold, this means that the oscillation detection output Q is "1" and Q
5, is smaller than the voltage Vstan supplied to the inverter when Q is on, and the inequality of equation '1' is satisfied. Therefore, in the above embodiment circuit, when the power is turned on, the inverter that performs the feedback amplification operation operates at Vstan,
When the device enters a stable oscillation state, it operates at a voltage of Vhold (Vstan), thereby reducing wasteful power consumption. That is, during a transient period such as after the power is turned on, a high voltage can be applied to the inverter to quickly bring it into a stable state, and the loss of power consumption in the stable state can be reduced. Figure 5a
shows a frequency dividing circuit as an example of the waveform shaping circuit 3,
FIG. 1B shows a circuit example in which this frequency dividing circuit is composed of four clocked inverters and two inverters. This frequency divider circuit can be formed with a CMOSFET, so that the embodiment of the oscillator circuit of FIG. 2 can be very compactly integrated into a CMOS integrated circuit for an electronic timepiece. At this time, the aforementioned oscillation detection circuit and current limiting resistors R, , R2 can also be integrated and inserted on the same semiconductor substrate, and the resistors R, , R2, etc. can be integrated into the MOSFET.
If the resistor is made using ET, the resistance value can be set with high accuracy, and operation reliability can be achieved even better. Further, by configuring the waveform shaping circuit with a frequency dividing circuit, it is possible to correctly perform off-timing of switching transistors Q5 and Q6 when transitioning from an unstable oscillation state at the start of operation to a normal oscillation state. In other words, the above configuration has a frequency dividing circuit and is configured to detect the number of output pulses of this frequency dividing circuit, so this frequency dividing circuit has an unsteady oscillation component (
It does not respond to the unstable oscillation signal during the initial small oscillation (unstable oscillation signal during the first small oscillation), and the waveform of the unstable oscillation between this initial unstable oscillation and the stable oscillation state (in this oscillation, the frequency divider circuit may respond). By extending the period, the count error in the detection circuit 4 can be reduced. This shows that the switching transistors Q5 and Q6 can be turned off at the correct timing. In the above embodiment, the resistor is connected to the power supply VD as a current limiting circuit.

, Vss, respectively, but they may be provided only in one current path. In addition, since we have explained the case where it is applied to the crystal oscillator of an electronic watch as a digital circuit, it is also possible to apply it to a CM that is generally said to have low power consumption.
Although an embodiment is shown in which an OS circuit is used, the inverter etc. can also be formed using a single channel FET. In addition, in the case of circuits where the size of the circuit is not considered, it is not necessarily necessary to integrate the circuit, and it is not necessary for the passive element to be a crystal oscillator and the active element to be an inverter in the oscillation circuit, and it is generally intended to reduce power consumption. It can be widely applied as an oscillation circuit in an electric circuit. FIG. 6 shows an embodiment in which an inverter is constructed using two P-channel FETs as active elements, and the current is limited on one side of the power supply Vss. This can be understood in the same way as the previous example,
Detailed explanation will be omitted. Note that in each of the above embodiments, the oscillation detection is performed using the output from the waveform shaping circuit 3 in order to prevent the unsteady oscillation state of a passive circuit such as a crystal resonator from being directly supplied to the oscillation detection circuit. In electronic watches and the like, which divide an original oscillation frequency signal to generate a basic oscillation signal, waveform shaping is usually performed by a multi-stage frequency dividing circuit.

Therefore, it is sufficient that the waveform shaping circuit in the present invention has a function of removing unsteady oscillation signal components. As detailed above, according to the present invention, the present invention operates reliably with low power consumption, has a simple circuit configuration, and can extend the life of the battery power supply. It is possible to provide an oscillation circuit that can be made lighter in weight and that can operate favorably using a waveform shaping circuit and an oscillation detection circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional oscillation circuit, FIG. 2 is a diagram showing an example circuit of the present invention, and FIG. 3 is a circuit configuration diagram showing an example of an oscillation detection circuit used in the same example. 4 is a diagram for explaining the detection operation in this oscillation detection circuit, FIGS. 5a and 5b are block diagrams and circuit diagrams showing an example of a frequency dividing circuit, and FIG. 6 is a diagram showing another embodiment of the present invention. FIG. 1, 2...Terminal for vibration signal, 3...
Waveform shaping circuit, 4...Oscillation detection circuit, 5...
...Inverter, Q, ~Q6...FET, R
,,R2...Resistance for current limiting. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. First and second insulated gate field effect transistors of one conductivity type connected in series between a first power source and a second power source, and third and fourth insulated gate field effect transistors of another conductivity type. Gate electrodes of the field effect transistor and the second and third insulated gate field effect transistors are commonly connected, and a crystal resonator and a resistor are connected in parallel between the output terminal of the second or third transistor. The configuration and the above first,
and a configuration in which a resistive load is connected in parallel to the fourth insulated gate field effect transistor;
A frequency divider circuit that divides the frequency of the oscillation wave formed by the fourth transistor, the crystal oscillator, and the resistor; and an oscillation detector that is connected to the frequency divider circuit and outputs a detection signal when the number of output pulses exceeds a predetermined value. circuit, and simultaneously conducts the first and fourth insulated gate field effect transistors using the output signal of the detection circuit to control the current flowing from the first power source to the second power source. An oscillation circuit characterized by the following.