KR20200118989A - Memory system, memory controller and operating method of thereof - Google Patents

Abstract

Embodiments of the present invention relate to a memory system, a memory controller, and an operation method of the memory controller. The memory system comprises: a memory device including a plurality of memory blocks; and a memory controller controlling the memory device. The memory controller may enable high-speed data recovery in an event of a read fail of data by searching a target read bias for a first word line among a plurality of word lines in an arbitrary first memory block of the memory device during an idle time and generating a history including the searched target read bias.

Description

Memory system, memory controller, and operation method thereof {MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD OF THEREOF}

Embodiments of the present invention relate to a memory system, a memory controller, and a method of operating the same.

A memory system corresponding to a storage device is a device that stores data based on a request from a host such as a computer, a mobile terminal such as a smart phone or a tablet, or a host such as various electronic devices. The memory system is not only a device that stores data on a magnetic disk, such as a hard disk drive (HDD), but also a solid state drive (SSD), a universal flash storage (UFS) device, and an embedded MMC (eMMC). A device that stores data in a nonvolatile memory, such as a device, may be included.

Nonvolatile memories included in the memory system include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), Flash memory, Phase-change RAM (PRAM), and MRAM. (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), etc. may be included.

The memory system may further include a memory controller for controlling a memory device, and such a memory controller receives a command from a host, and based on the received command, a volatile memory or a nonvolatile memory included in the memory system is Operations for reading, writing, or erasing data may be executed or controlled.

Meanwhile, in the case of a conventional memory system, a read failure may inevitably occur in the process of reading data from a memory device. When such a read failure occurs, a normal read operation for data is not efficiently executed. It is not a situation. Therefore, when a read failure occurs, a technology that prevents performance degradation of the memory system and at the same time efficiently executes a read re-operation to complete it normally is an urgent situation.

Embodiments of the present invention provide a memory system, a memory controller, and a method of operating the same that enable high-speed data recovery when data read-fail occurs.

In addition, embodiments of the present invention preemptively search for an optimal target read bias for data read retry, and provide a history as a memory system that enables rapid and effective data recovery in the event of a data read failure. A memory controller and a method of operating the same are provided.

Further, embodiments of the present invention provide a memory system, a memory controller, and a method of operating the same for preemptively searching for an optimum target read bias used in a data read operation in consideration of a deterioration state of a memory device.

In one aspect, a memory system according to embodiments of the present invention may include a memory device including a plurality of memory blocks, and a memory controller that controls the memory device.

During an idle time, the memory controller searches for a target read bias for a first word line among a plurality of word lines in an arbitrary first memory block of the memory device, and searches for a target read bias. It is possible to create a history (History) including.

The history can be generated in units of memory blocks.

Alternatively, the history may be generated in units of word lines.

Alternatively, the history may be generated in units of word line groups.

The first word line may correspond to an outermost word line among a plurality of word lines in the first memory block. Alternatively, the first word line may correspond to a word line adjacent to the dummy word line among a plurality of word lines in the first memory block.

When the read count value for the first memory block according to the read operation for one page in the first memory block is equal to or greater than a preset threshold, the memory controller may perform an idle time for the first word line in the first memory block. Target read bias can be searched.

The threshold value may be set smaller than a read count value related to deterioration corresponding to the first memory block.

After the history is generated, when a page in the first memory block fails to read, the memory controller may refer to the history and retry the read operation based on the target read bias.

In another aspect, embodiments of the present invention may provide a memory controller including a host interface for communication with a host, a memory interface for communication with a memory device, and a control circuit for controlling an operation of the memory device.

The operation of the memory device may include a read operation, a program operation, and an erase operation.

The control circuit may include firmware and a processor executing the firmware.

During an idle time, the control circuit searches for a target read bias for a first word line among a plurality of word lines in a first memory block of the memory device, and includes a history including a target read bias. Can be created.

The target read bias may be a representative target read bias for the first memory block.

The target read bias may be an individual target read bias for the first word line.

The target read bias may be a representative target read bias for a group of word lines including the first word line.

In another aspect, embodiments of the present invention, during an idle time (Idle Time), to search for a target read bias for a first word line among a plurality of word lines in a first memory block of a memory device. It is possible to provide a method of operating a memory controller including the step of generating a history including the target read bias.

Embodiments of the present invention can provide a memory system, a memory controller, and a method of operating the same that enable high-speed data recovery when data read-fail occurs.

In addition, embodiments of the present invention preemptively search for an optimal target read bias for data read retry, and provide a history as a memory system that enables rapid and effective data recovery in the event of a data read failure. A memory controller and an operating method thereof can be provided.

In addition, embodiments of the present invention may provide a memory system, a memory controller, and an operating method thereof that preemptively search for an optimum target read bias used in a data read operation in consideration of a deterioration state of a memory device.

1 is a block diagram schematically illustrating a memory system according to embodiments of the present invention.
2 is a block diagram schematically illustrating a memory device according to embodiments of the present invention.
3 is a schematic diagram of a memory block of a memory device according to example embodiments.
4 is a flowchart illustrating a data recovery procedure of a memory system according to embodiments of the present invention.
5 is a flowchart illustrating a method of operating a memory controller using a preemptive history generation technique for high-speed data recovery in a memory system according to embodiments of the present invention.
6 is a diagram illustrating preemptive history generation timing for high-speed data recovery in a memory system according to embodiments of the present invention.
7 is a diagram illustrating a preemptive target read bias search for high-speed data recovery in a memory system according to embodiments of the present invention.
8 is a detailed flowchart illustrating a method of operating a memory controller using a preemptive history generation technique for high-speed data recovery in a memory system according to embodiments of the present invention.
9 is an exemplary diagram of a preemptive target read bias search target for fast recovery of a memory system according to embodiments of the present invention.
10 is another exemplary diagram of a preemptive target read bias search target for fast recovery of a memory system according to embodiments of the present invention.
11 is another exemplary diagram of a preemptive target read bias search target for fast recovery of a memory system according to embodiments of the present invention.
12 is a flowchart illustrating a data recovery procedure of a memory system when the preemptive history generation technique according to embodiments of the present invention is applied.
13 is a schematic functional block diagram of a memory controller according to embodiments of the present invention.
14 is a block diagram schematically illustrating a computing system according to embodiments of the present invention.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms different from each other, and only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the scope of the invention to the possessor, and the invention is only defined by the scope of the claims.

In addition, the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in describing the present invention, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When'include','have','consists of' and the like mentioned in the specification are used, other parts may be added unless'only' is used. In the case of expressing the constituent elements in the singular, the case including the plural may be included unless specifically stated otherwise.

In addition, in interpreting the constituent elements in the embodiments of the present invention, it should be construed as including an error range even if there is no explicit description.

In addition, in describing the constituent elements of the present invention, terms such as first, second, A, B, (a), (b) may be used. These terms are only for distinguishing the component from other components, and the nature, order, order, or number of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, that component may be directly connected or connected to that other component, but other components between each component It is to be understood that is "interposed", or that each component may be "connected", "coupled" or "connected" through other components. In the case of a description of the positional relationship, for example, if the positional relationship of two parts is described as'upper','upper of','lower of','next to','right' Or, unless'direct' is used, one or more other parts may be located between the two parts.

In addition, components in the embodiments of the present invention are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below may be a second component within the technical idea of the present invention.

In addition, features (configurations) in the embodiments of the present invention can be partially or completely combined, combined or separated with each other, technically various interlocking and driving are possible, and each embodiment is implemented independently of each other. It may be possible or it may be possible to act together in a related relationship.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a memory system 100 according to embodiments of the present invention.

Referring to FIG. 1, a memory system 100 according to embodiments of the present invention may include a memory device 110 that stores data, a memory controller 120 that controls the memory device 110, and the like. .

The memory device 110 includes a plurality of memory blocks and operates in response to the control of the memory controller 120. Here, the operation of the memory device 110 may include, for example, a read operation, a program operation (also referred to as a write operation), and an erase operation.

The memory device 110 may include a memory cell array including a plurality of memory cells storing data. Such an array of memory cells may exist within a memory block.

For example, the memory device 110 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), RDRAM (Rambus Dynamic Random Access Memory), NAND Flash Memory, Vertical NAND, NOR Flash memory, Resistive Random Access Memory (RRAM), phase change memory (Phase-Change Memory: PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin Transfer Torque Random Access Memory (STT-RAM), etc. It can be implemented as

Meanwhile, the memory device 110 may be implemented in a three-dimensional array structure. Embodiments of the present invention can be applied to a flash memory device in which the charge storage layer is formed of a conductive floating gate, as well as a charge trap flash (CTF) in which the charge storage layer is formed of an insulating film.

The memory device 110 is configured to receive a command and an address from the memory controller 120 and access a region selected by an address in the memory cell array. That is, the memory device 110 may perform an operation corresponding to the command on the region selected by the address.

For example, the memory device 110 may perform a program operation, a read operation, and an erase operation. In this regard, during the program operation, the memory device 110 will program data in an area selected by an address. During a read operation, the memory device 110 will read data from an area selected by an address. During the erase operation, the memory device 110 will erase data stored in the area selected by the address.

The memory controller 120 may control the operation of the memory device 110 according to the request of the host HOST or irrespective of the request of the host HOST.

For example, the memory controller 120 may control write (program), read, erase, and background operations of the memory device 110. Here, the background operation may be, for example, garbage collection (GC), wear leveling (WL), and bad block management (BBM) operations.

Referring to FIG. 1, the memory controller 120 may include a host interface 121, a memory interface 122, a control circuit 123, and the like.

The host interface 121 provides an interface for communication with a host (HOST). When receiving a command from the host HOST, the control circuit 123 may receive the command through the host interface 121 and perform an operation of processing the received command.

The memory interface 122 is connected to the memory device 110 and provides an interface for communication with the memory device 110. That is, the memory interface 122 may be configured to provide an interface between the memory device 110 and the memory controller 120 in response to the control of the control circuit 123.

The control circuit 123 controls the operation of the memory device 110 by performing an overall control operation of the memory controller 120. To this end, as an example, the control circuit 123 may include one or more of a processor 124, a working memory 125, and the like, and in some cases, an error detection and correction circuit (ECC Circuit, 126), etc. Can include.

The processor 124 may control all operations of the memory controller 120 and may perform logical operations. The processor 124 may communicate with the host HOST through the host interface 121 and may communicate with the memory device 110 through the memory interface 122.

The processor 124 may perform a function of a flash translation layer (FTL). The processor 124 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through a flash translation layer (FTL). The flash conversion layer FTL may receive a logical block address LBA using a mapping table and convert it into a physical block address PBA. There are several address mapping methods of the flash translation layer depending on the mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

The processor 124 is configured to randomize data received from a host (HOST). For example, the processor 124 will randomize the data received from the host using a randomizing seed. The randomized data is provided to the memory device as data to be stored and programmed into the memory cell array.

The processor 124 is configured to derandomize data received from the memory device during a read operation. For example, the processor 124 may derandomize the data received from the memory device using the derandomizing seed. The derandomized data will be output to the host.

The processor 124 may control the operation of the memory controller 120 by executing firmware (FirmWare). In other words, the processor 124 may execute (drive) the firmware loaded in the working memory 125 during booting to control all operations of the memory controller 120 and perform logical operations. As an example, firmware may be stored in the memory device 110 and then loaded into the working memory 125.

Firmware (FirmWare) is a program executed in the memory system 100, for example, a logical address requested from the host (HOST) to the memory system 100 and a physical address of the memory device 110 (Physical address) Flash translation layer (FTL) that converts between addresses), which interprets commands that the host requests to the memory system 100, which is a storage device, and delivers them to the flash translation layer (FTL). It may include a host interface layer (HIL), a flash interface layer (FIL) that transmits a command indicated by the flash conversion layer (FTL) to the memory device 110.

The working memory 125 may store firmware, program codes, commands, or data necessary to drive the memory controller 120.

The working memory 125 is, for example, a volatile memory, and may include at least one of static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like.

The error detection and correction circuit 126 detects and detects an error bit of data stored in the working memory 125 (that is, read data transferred from the memory device 110) using an error correction code. Can be configured to correct the error bits that have been generated.

The error detection and correction circuit 126 may be implemented to decode data into an error correction code. The error detection and correction circuit 126 may be implemented with various code decoders. For example, a decoder that performs unstructured code decoding or a decoder that performs systematic code decoding may be used.

For example, the error detection and correction circuit 126 may detect an error bit in units of sectors for each of the read data. That is, each read data may be composed of a plurality of sectors. A sector may mean a data unit smaller than a page, which is a read unit of a flash memory. Sectors constituting each read data may correspond to each other through an address.

The error detection and correction circuit 126 may calculate a bit error rate (BER) and determine whether correction is possible in units of sectors. The error detection and correction circuit 126, for example, if the bit error rate (BER) is higher than the reference value, will determine the sector as Uncorrectable or Fail. On the other hand, if the bit error rate (BER) is lower than the reference value, it will be determined that the sector is correctable (Correctable or Pass).

The error detection and correction circuit 126 may sequentially perform an error detection and correction operation on all read data. When the sector included in the read data is correctable, the error detection and correction circuit 126 may omit the error detection and correction operation for the corresponding sector for the next read data. When the error detection and correction operation for all the read data is terminated in this way, the error detection and correction circuit 126 may detect a sector determined to be uncorrectable until the end. There may be one or more sectors determined to be uncorrectable. The error detection and correction circuit 126 may transmit information (eg, address information) on a sector determined to be uncorrectable to the processor 124.

The bus 127 may be configured to provide a channel between the components 121, 122, 124, 125, 126 of the memory controller 120. The bus 127 may include, for example, a control bus for transferring various control signals, commands, and the like, and a data bus for transferring various data.

The above-described components 121, 122, 124, 125, 126 of the memory controller 120 are only examples, and some of the components 121, 122, 124, 125, 126 mentioned above are It may be deleted, some of the aforementioned constituent elements 121, 122, 124, 125, 126 may be integrated into one, or one or more constituent elements may be added.

Hereinafter, the memory device 110 will be described in more detail with reference to FIG. 2.

2 is a block diagram schematically illustrating a memory device 110 according to example embodiments.

Referring to FIG. 2, a memory device 110 according to embodiments of the present invention includes a memory cell array 210, an address decoder 220, and a read and write circuit. , 230), a control logic 240, a voltage generation circuit 250, and the like.

The memory cell array 210 may include a plurality of memory blocks BLK1 to BLKz, where z is a natural number of 2 or more.

The plurality of memory blocks BLK1 to BLKz may be connected to the address decoder 220 through word lines WL. The plurality of memory blocks BLK1 to BLKz may be connected to the read-and-write circuit 230 through bit lines BL1 to BLm.

Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. For example, the plurality of memory cells are nonvolatile memory cells, and may be formed of nonvolatile memory cells having a vertical channel structure. The memory cell array 210 may be configured as a two-dimensional memory cell array, and in some cases, may be configured as a three-dimensional memory cell array.

Meanwhile, each of the plurality of memory cells included in the memory cell array may store at least 1 bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 may be a single-level cell (SLC) that stores 1-bit data. As another example, each of the plurality of memory cells included in the memory cell array 210 may be a multi-level cell (MLC) storing 2-bit data. As another example, each of the plurality of memory cells included in the memory cell array 210 may be a triple-level cell (TLC) storing 3-bit data. As another example, each of the plurality of memory cells included in the memory cell array 210 may be a quad-level cell (QLC) storing 4-bit data. As another example, the memory cell array 210 may include a plurality of memory cells each storing 5 bits or more of data.

Referring to FIG. 2, an address decoder 220, a read-and-write circuit 230, a control logic 240, and a voltage generation circuit 250 may operate as peripheral circuits that drive the memory cell array 210. .

The address decoder 220 may be connected to the memory cell array 210 through word lines WL. The address decoder 220 may be configured to operate in response to the control of the control logic 240. The address decoder 220 may receive an address through an input/output buffer in the memory device 110.

The address decoder 220 may be configured to decode a block address among received addresses. The address decoder 220 may select at least one memory block according to the decoded block address. In addition, the address decoder 220 applies the read voltage Vread generated by the voltage generating circuit 250 to the selected word line among the selected memory blocks during the read voltage application operation during the read operation, and the remaining unselected word lines. The pass voltage Vpass may be applied to the fields. In addition, during the program verification operation, a verification voltage generated by the voltage generation circuit 250 may be applied to a selected word line among selected memory blocks to a selected word line, and a pass voltage Vpass may be applied to the remaining unselected word lines. .

The address decoder 220 may be configured to decode a column address among received addresses. The address decoder 220 may transmit the decoded column address to the read and write circuit 230.

The read operation and the program operation of the memory device 110 may be performed on a page basis. Addresses received when requesting a read operation and a program operation may include a block address, a row address and a column address.

The address decoder 220 may select one memory block and one word line according to the block address and the row address. The column address may be decoded by the address decoder 220 and provided to the read-and-write circuit 230.

The address decoder 220 may include one or more of a block decoder, a row decoder, a column decoder, and an address buffer.

The read-and-write circuit 230 may include a plurality of page buffers PB1 to PBm. The read and write circuit 230 operates as a "read circuit" during a read operation of the memory cell array 210, and a "write circuit" during a write operation. Can act as ".

The above-described read-and-write circuit 230 may include a page buffer circuit or a data register circuit. For example, the data register circuit may include a data buffer in charge of a data processing function, and in some cases, may further include a cache buffer in charge of a caching function.

The plurality of page buffers PB1 to PBm may be connected to the memory cell array 210 through bit lines BL1 to BLm. The plurality of page buffers PB1 to PBm continuously supply sensing current to the bit lines connected to the memory cells in order to sense the threshold voltage Vth of the memory cells during a read operation and a program verify operation. Changes in the amount of current flowing according to the program state can be sensed through a sensing node and latched as sensed data. The read-and-write circuit 230 may operate in response to page buffer control signals output from the control logic 240.

During a read operation, the read-and-write circuit 230 senses data of a memory cell to temporarily store read data, and then outputs the data DATA to an input/output buffer of the memory device 110. As an exemplary embodiment, the read-and-write circuit 230 may include a column selection circuit in addition to page buffers (or page registers).

The control logic 240 may be connected to the address decoder 220, the read and write circuit 230, and the voltage generation circuit 250. The control logic 240 may receive the command CMD and the control signal CTRL through the input/output buffer of the memory device 110.

The control logic 240 may be configured to control general operations of the memory device 110 in response to the control signal CTRL. In addition, the control logic 240 may output a control signal for adjusting the sensing node precharge potential level of the plurality of page buffers PB1 to PBm.

The control logic 240 may control the read and write circuit 230 to perform a read operation of the memory cell array 210.

The voltage generation circuit 250 may generate a read voltage Vread and a pass voltage Vpass during a read operation in response to a voltage generation circuit control signal output from the control logic 240.

3 is a diagram schematically illustrating memory blocks BLKi, i=1, 2, ..., z of the memory device 110 according to example embodiments.

Referring to FIG. 3, among a plurality of memory blocks BLK1 to BLKz included in the memory device 110, a first memory block BLKi, i=1, 2, ..., z is n pages. (PG1 to PGn, n is a natural number of 2 or more) and m strings (STR1 to STRm, m is a natural number of 2 or more) may be arranged in a matrix form.

The n pages PG1 to PGn correspond to n word lines WL1 to WLn, and m strings STR1 to STRm correspond to m bit lines BL1 to BLm.

That is, among the plurality of memory blocks BLK1 to BLKz, n word lines WL1 to WLn and m bit lines BL1 are included in any first memory block BLKi, i=1, 2, ..., z. ~ BLm) can be arranged while intersecting.

The n word lines WL1 to WLn and the m bit lines BL1 to BLm may cross each other to define a memory cell, and a transistor may be disposed in each memory cell. For example, a transistor disposed in each memory cell may include a drain, a source, and a gate, and the drain (or source) of the transistor may be connected directly to the corresponding bit line or via another transistor, and the source of the transistor (Or the drain) may be connected directly to the source line (which may be ground) or via another transistor, and the gate of the transistor is a floating gate surrounded by an insulator and a control gate to which the gate voltage is applied. It may include.

A read operation and a program operation (write operation) may be performed in units of pages, and an erase operation may be performed in units of memory blocks.

Referring to FIG. 3, in an arbitrary first memory block BLKi, i=1, 2, ..., z among a plurality of memory blocks BLK1 to BLKz, two outermost word lines WL1 and WLn A first selection line (also referred to as a source selection line or a drain selection line) may be further disposed outside the first outermost word line WL1 that is closer to the read-and-write circuit 230. A second selection line (also referred to as a drain selection line or a source selection line) may be further disposed outside the outer word line WLn.

Meanwhile, in some cases, one or more dummy word lines may be further disposed between the first outermost word line WL1 and the first selection line. In addition, one or more dummy word lines may be further disposed between the second outermost word line WLn and the second selection line.

4 is a flowchart illustrating a data recovery procedure of the memory system 100 according to embodiments of the present invention.

Referring to FIG. 4, the memory system 100 according to embodiments of the present invention may perform a data recovery procedure when a read fail occurs during a data read process S410.

Referring to FIG. 4, the data recovery procedure executed due to a read failure is a read retry step that is performed when there is a history according to the results of the history read step (S420) and the history read step (S420). Step, S430), a target read bias search step (TRB Search Step, S440) that searches for a target read bias (TRB) that proceeds when there is no history according to the result of the history read step (S420). I can.

In the history read step (S420), the memory controller 120 stores a target read bias (TRB) that has been previously searched or information corresponding thereto (eg, an index of a read retry table (RRT)) as a history. You can check if it exists.

In the present specification, a target read bias (TRB) may be a type of gate voltage applied to a word line WL electrically connected to a control gate of a transistor disposed in each memory cell in order to perform a read operation. . This target read bias (TRB) is also referred to as an optimal read bias (Optimal Read Bias). The target read bias TRB may correspond to each word line WL, for example, or may correspond to each memory block. That is, a history including the target read bias TRB or corresponding information thereof is a kind of information or data, and may exist corresponding to each word line WL or exist corresponding to each memory block.

The read retry step (S430) is a step executed when it is confirmed that the history exists in the history read step (S420). In the read retry step S430, the memory controller 120 may retry the read operation by using the target read bias TRB included in the history checked in the read history step S420.

The target read bias search step (S440) is a step executed when it is determined that the history does not exist in the history read step (S420). In the target read bias search step S440, the memory controller 120 newly searches for the target read bias TRB corresponding to the optical read bias and generates a history including the searched target read bias TRB. Thereafter, the memory controller 120 may perform a read retry step S430 using the newly discovered target read bias TRB. Here, the newly searched target read bias TRB corresponds to a corresponding word line WL or a corresponding memory block.

As described above, the target read bias TRB is also referred to as an optimal read bias. The read bias (which may also be referred to as a lead voltage) may not be fixed and may change as the memory device 110 deteriorates. Therefore, an optimum read bias suitable for the deteriorated state of the memory device 110 is referred to as a target read bias TRB. Here, degradation corresponds to a characteristic value of a transistor disposed in each memory cell, and may mean that a threshold voltage Vth that changes an operation (on-off operation) of the transistor changes. That is, when the transistor is deteriorated, the threshold voltage Vth of the transistor may decrease or increase. Meanwhile, when viewed as a whole, the distribution of threshold voltages of a plurality of transistors arranged in the memory cell array can be shifted in a negative direction (a direction in which the threshold voltage is lowered) or a positive direction (a direction in which the threshold voltage is increased) ( That is, the distribution change of the threshold voltage distribution) and the average value of the threshold voltages of a plurality of transistors arranged in the memory cell array may be decreased or increased. Changes in the characteristics of the threshold voltage distribution (distribution change (statistically, for example, standard deviation), change in average value, etc.) change the timing of the on-off operation of the transistor in each memory cell. , When the memory cell is operated (lead, program, erase, etc.), a desired operation may be performed.

As described above, the target read bias TRB needs to be set to an optimal value according to threshold voltage distributions reflecting the deterioration state of the memory device 110. Therefore, the time or number of times it takes to newly search for the target read bias TRB is determined by the memory cell being a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell ( It may vary depending on the type and number of threshold voltage distribution levels that vary depending on whether it is QLC) or the like. Here, a single-level cell (SLC) has a total of two levels (L0, L1) per cell, a multi-level cell (MLC) has a total of four levels (L0, L1, L2, L3) per cell, The triple-level cell TLC has a total of 8 levels (L0, L1, L2, L3, L4, L5, L6, L7) per cell. In addition, a quad-level cell (QLC) has a total of 16 levels per cell.

As an example, in the case of a multi-level cell (MLC) having 4 (=2^2) threshold voltage distribution levels, in the worst case, a new target read bias (TRB) may be searched through three search processes. . As another example, in the case of a triple-level cell (TLC) having 8 (=2^3) threshold voltage distribution levels, in the worst case, a new target read bias (TRB) may be searched through 7 search processes. . Accordingly, it may take too long to search for the target read bias TRB in the data recovery process.

As described above, when data is recovered, when there is no history, a large amount of time and number of searches are required to search for a new target read bias (TRB), and data recovery may be slow, and accordingly, performance of the memory system 100 decreases. Can occur.

Accordingly, embodiments of the present invention propose high-speed data recovery and preemptive history generation techniques for this. In the following, high-speed data recovery and preemptive history generation techniques for this will be described in detail.

5 is a flowchart illustrating a method of operating the memory controller 120 using a preemptive history generation technique for high-speed data recovery of the memory system 100 according to embodiments of the present invention, and FIG. 6 is an embodiment of the present invention. A diagram showing the timing of preemptive history generation for high-speed data recovery of the memory system 100 according to the present invention, and FIG. 7 is a diagram illustrating a preemptive target read bias search for high-speed data recovery of a memory system according to embodiments of the present invention. This is the diagram shown.

5 and 6, the preemptive history generation technique for high-speed data recovery includes a step (S510) of searching for a target read bias (TRB) during an idle time (Ti), and a searched target read. The process may proceed to an operation S520 of generating a history including the bias TRB.

Here, the idle time (Ti) is a time when other general operations such as a read operation, a program operation, and an erase operation are not performed, and operation times (To) for performing other general operations such as a read operation, a program operation, and an erase operation. It may be a time interval between.

This idle time Ti may be an idle time of a flash interface layer (FIL) in the memory controller 120. Here, as an example, the flash interface layer FIL may be a layer that transfers a command indicated by the flash conversion layer FTL among function layers in the firmware to the memory device 110.

During the idle time Ti, the memory controller 120 includes first word lines WL1 to WLn among a plurality of word lines WL1 to WLn in any first memory block BLK1 to BLKz in the memory device 110. One of the WLn) may be searched for a target read bias TRB (S510), and a history including the searched target read bias TRB may be generated (S520). Here, the first word line is a word line to be searched for the target read bias TRB.

For example, target read bias search and history generation (S510 and S520) performed during the idle time Ti may be performed by the control circuit 123 included in the memory controller 120. That is, the processor 124 in the control circuit 123 may execute the firmware loaded in the working memory 125 to search for a target read bias and generate a history (S510, S520).

Meanwhile, the history may be generated by the memory controller 120 and stored in an internal memory (eg, working memory 125) of the memory controller 120, or in some cases, stored in the memory device 110. Alternatively, it may be stored in both the internal memory of the memory controller 120 (for example, the working memory 125) and the memory device 110.

Meanwhile, the memory controller 120 may perform target read bias search and history generation in units of memory blocks, or may perform more compactly in units of word lines.

Accordingly, the target read bias TRB for one first word line in the first memory block BLK1 to BLKz is applied to the first memory block BLK1 to BLKz including the first word line. It may be one representative target read bias for the first memory block or an individual target read bias for one first word line in the first memory block BLK1 to BLKz.

In other words, the memory controller 120 determines the target read bias TRB for the first word line to be searched among the plurality of word lines WL1 to WLn in the first memory block BLK1 to BLKz. It can be searched as a representative target read bias for one memory block (one of BLK1 to BLKz).

Alternatively, the memory controller 120 may apply a target read bias TRB for the first word line among the plurality of word lines WL1 to WLn in the first memory block BLK1 to BLKz for the first word line. You can search as individual target read bias. That is, the memory controller 120 may individually search for a target read bias for each of the plurality of word lines WL1 to WLn in the first memory blocks BLK1 to BLKz.

Alternatively, the memory controller 120 includes a target read bias TRB for a first word line among a plurality of word lines WL1 to WLn in the first memory block BLK1 to BLKz as a first word line. It can be searched as a representative target read bias for a group of word lines to be used. Here, one word line group may include two or more word lines among the plurality of word lines WL1 to WLn in the first memory blocks BLK1 to BLKz.

As described above, the target read bias TRB may be determined according to distributions of threshold voltages Vth reflecting the deterioration state of the memory device 110. Accordingly, the search for the target read bias TRB may be performed in consideration of threshold voltage distributions of the memory device 110 as illustrated in FIG. 7.

Referring to FIG. 7, the time or number of times it takes to search for a target read bias TRB during an idle time Ti is a single-level cell (SLC), a multi-level cell (MLC), and a triple-level cell. It may vary according to the type and number of threshold voltage distribution levels that vary depending on whether it is (TLC) or a quad-level cell (QLC).

As an example, referring to FIG. 7, in the case of a multi-level cell (MLC) having 4 (=2^2) threshold voltage distribution levels, a new target read bias (TRB) may be searched through three search processes. I can. As another example, in the case of a triple-level cell TLC having 8 (=2^3) threshold voltage distribution levels, a new target read bias TRB may be searched through the seventh search process.

8 is a detailed flowchart illustrating a method of operating the memory controller 120 using a preemptive history generation technique for high-speed data recovery of the memory system 100 according to embodiments of the present invention.

Referring to FIG. 8, a method of operating the memory controller 120 using a preemptive history generation technique for high-speed data recovery of the memory system 100 according to embodiments of the present invention is to search for a target read bias (TRB). Prior to the step (S510), the read operation step (S810), the read count value monitoring step (S820), the memory state determination step (S830), the memory block address storage step (S840), the idle time determination step (S850), the memory It may include a block address loading step (S860) and a history presence check step (S870).

When the read operation is performed on the first memory block (one of BLK1 to BLKz) among the plurality of memory blocks BLK1 to BLKz in the read operation step S810, in the read count value monitoring step S820, the memory controller 120 Increases the read count value READ_COUNT for the first memory block BLK1 to BLKz, and monitors the increased read count value READ_COUNT.

In the memory state determination step S830, the memory controller 120 performs a first read operation for one page (one of PG1 to PGn) in the first memory block BLK1 to BLKz to be checked. It is determined whether the read count value READ_COUNT for the memory blocks BLK1 to BLKz exceeds a preset threshold value TH.

As a result of the determination in the memory state determination step S830, if the read count value READ_COUNT for the first memory block (one of BLK1 to BLKz) is less than the preset threshold TH, the memory controller 120 performs a read operation. Can be performed again.

As a result of the determination in the memory state determination step (S830), when the read count value (READ_COUNT) for the first memory block (one of BLK1 to BLKz) exceeds the preset threshold value TH, the memory block address storage step (S840) ) Proceeds.

For example, the preset threshold TH may be set to be smaller than a read count value related to degradation corresponding to the first memory block BLK1 to BLKz.

In connection with this example, when the read count value READ_COUNT reaches a certain value (deterioration-related read count value), the first memory block (one of BLK1 to BLKz) is considered to have deteriorated, and the corresponding first memory block A garbage collection operation or a bad block management (BBM) operation for (one of BLK1 to BLKz) may be performed. In consideration of this, the threshold value (TH) corresponding to the read count value (READ_COUNT) to trigger the advance entry of the preemptive history generation technique is the deterioration lead count that causes the garbage collection operation or the bad block management operation to proceed. It can be set smaller than the value.

If the condition for triggering the advance entry of the preemptive history generation technique is satisfied, the memory block address storage step (S840) proceeds, and in this memory block address storage step (S840), the memory controller 120 performs a first memory block. It stores the memory block address for (one of BLK1 ~ BLKz).

After the memory block address storing step (S840), the idle time determination step (S850) proceeds. In the idle time determination step S850, the memory controller 120 determines whether the idle time Ti is reached.

When it is determined that the idle time Ti is reached in the idle time determination step S850, the memory block address loading step S860 and the history existence check step S870 are performed.

In the memory block address loading step (S860), the memory controller 120, when the memory controller 120 reaches the idle time Ti, the first memory blocks BLK1 to BLKz stored in the memory block address storage step S840. The memory block address for one of) is loaded.

Thereafter, in the step S870 of checking whether the history exists, the memory controller 120 determines whether the history exists.

If the history exists as a result of performing the history existence check step S870, the memory controller 120 skips the step S510 of searching for the target read bias TRB and the step S520 of generating the history.

As a result of performing the history presence/absence check step S870, if the history does not exist, the memory controller 120 performs a step S510 of searching for a target read bias TRB and a step S520 of generating a history.

As described above, the memory controller 120 does not always perform a preemptive history generation operation of proactively generating a history by searching for a target read bias TRB, but one of the first memory blocks BLK1 to BLKz. ) When the read count value (READ_COUNT) for the first memory block (one of BLK1 to BLKz) according to the read operation for one page within is equal to or greater than the preset threshold value TH, during the idle time Ti, the first Since the history is generated by searching for the target read bias (TRB) for the first word line (one of WL1 to WLn) in the memory block (one of BLK1 to BLKz), the procedure to search for unnecessary target read bias and check the existence of unnecessary history It can prevent the back. Accordingly, unnecessary performance degradation of the memory controller 120 and the memory system 100 including the same can be prevented.

In addition, as described above, the memory controller 120 preempts the history required in the data recovery procedure during the idle time (Ti) between the general operation times (To) before the data recovery procedure proceeds according to a read failure. Since it is created in advance as a target, it can enable high-speed data recovery even if a lead failure occurs.

The order of steps in the flowchart of FIG. 8 is merely an example and may be changed, and in some cases, two or more steps may be integrated into one, one or more steps may be omitted or replaced with other steps.

9 is an exemplary diagram of a preemptive target read bias search target for high-speed recovery of the memory system 100 according to embodiments of the present invention, and FIG. 10 is a diagram of a memory system 100 according to embodiments of the present invention. It is another exemplary diagram of a preemptive target read bias search target for high-speed recovery.

9 and 10, the target read bias TRB to be searched during the idle time Ti may be a representative target read bias for the first memory blocks BLK1 to BLKz. That is, the target read bias TRB may be one representative target read bias representing all of the word lines WL1 to WLn in the first memory block BLK1 to BLKz.

That is, only a part of the plurality of word lines WL1 to WLn included in the corresponding first memory block BLK1 to BLKz is a target to preemptively search for the target read bias TRB during the idle time Ti. Can be.

Meanwhile, the two outermost word lines WL1 and WLn may be the weakest word lines in terms of reliability among the plurality of word lines WL1 to WLn.

Considering this, the one or more first word lines that are to be preemptively searched for the target read bias TRB during the idle time Ti are, for example, as shown in FIG. 9, the first memory block It may correspond to one or more of the two outermost word lines WL1 and WLn among the plurality of word lines WL1 to WLn in (any one of BLK1 to BLKz).

Meanwhile, as shown in FIG. 10, in any first memory block BLKi, i = 1, 2, ..., z among a plurality of memory blocks BLK1 to BLKz, two outermost word lines ( One or more first dummy word lines DMY_WL1 may be further disposed outside the first outermost word line WL1 adjacent to the read-and-write circuit 230 among WL1 and WLn, and two outermost words One or more second dummy word lines DMY_WL2 may be further disposed outside of the second outermost word line WLn located on the opposite side of the first outermost word line WL1 among the lines WL1 and WLn.

In the case of having such a structure, one or more word lines WL1 and WLn adjacent to one or more dummy word lines DMY_WL1 and DMY_WL2 may be a word line having the least reliability among the plurality of word lines WL1 to WLn.

Accordingly, as shown in FIG. 10, the first word line, which is a target for preemptively searching for the target read bias TRB during the idle time Ti, is within the first memory block BLK1 to BLKz. It may correspond to one or more word lines WL1 and WLn adjacent to one or more dummy word lines DMY_WL1 and DMY_WL2 among the plurality of word lines WL1 to WLn.

On the other hand, the first word line is the weakest word line in terms of reliability among a plurality of word lines WL1 to WLn in the first memory block BLK1 to BLKz, and the outermost word lines WL1 and WLn are In terms of reliability, the word line may be the weakest, or the word lines WL1 and WLn adjacent to the dummy word lines DMY_WL1 and DMY_WL2 may be the weakest word line in terms of reliability, but one or two or more word lines ( One or more of WL2 to WLn-1) may be the weakest word line. Here, the most vulnerable in terms of reliability may mean that a read operation may not be performed normally, leading to a read failure. In other words, the first word line may be an arbitrary word line among a plurality of word lines WL1 to WLn in the first memory block BLK1 to BLKz, and read fail occurs during a read operation. It may correspond to a word line judged to have a possibility of triggering.

11 is another exemplary diagram of a preemptive target read bias search target for high-speed recovery of the memory system 100 according to example embodiments.

Referring to FIG. 11, as described above with reference to FIGS. 9 and 10, only a part of a plurality of word lines WL1 to WLn included in a corresponding first memory block BLK1 to BLKz is an idle time ( During Ti), each of the plurality of word lines WL1 to WLn included in the corresponding first memory block (any one of BLK1 to BLKz) is not a target to preemptively search for the target read bias TRB. During (Ti), the target read bias TRB may be preemptively searched for.

Accordingly, referring to FIG. 11, the memory controller 120 includes a target read bias TRB for a first word line among a plurality of word lines WL1 to WLn in the corresponding first memory block BLK1 to BLKz. ) May be searched as an individual target read bias for the corresponding first word line, not as a representative target read bias representing the entire first memory block BLK1 to BLKz.

That is, the target read bias TRB searched during the idle time Ti may be an individual target read bias for the first word line.

12 is a flowchart illustrating a data recovery procedure of the memory system 100 when the preemptive history generation technique according to embodiments of the present invention is applied.

Referring to FIG. 12, according to the preemptive history generation technique described above, the memory controller 120 preemptively generates a history by proactively searching for a target read bias TRB during an idle time Ti. As a result of performing the normal read operation (S410), when a lead failure occurs, in the process of performing the history read step (S420), the history preemptively generated prior to the lead failure is read, and the read retry is quickly performed. It can be performed (S430). Thus, high-speed data recovery may be possible.

That is, according to the preemptive history generation technique, the case where the history in FIG. 4 does not exist or is minimized, the target read bias search step (S440) in the data recovery process is eliminated or minimized. It could be possible.

For example, referring to FIG. 12, after the step of generating the history of FIG. 8 (S520), when a read-fail for one page in the first memory block BLK1 to BLKz, the data recovery procedure proceeds, The read operation may be retried using the target read bias TRB by referring to the history preemptively generated in the history generation step S520.

That is, the control circuit 123 in the memory controller 120 includes a history of the first memory block BLK1 to BLKz or a first word line included in the first memory block BLK1 to BLKz. After the history of the first memory block (either BLK1 to BLKz) fails to read, a read operation is performed based on the target read bias TRB by referring to the previously generated history. You can try again.

13 is a schematic functional block diagram of a memory controller 120 according to embodiments of the present invention.

Referring to FIG. 13, a memory controller 120 according to embodiments of the present invention includes a plurality of words in a first memory block BLK1 to BLKz of the memory device 110 during an idle time Ti. A target read bias search module 1310 that preemptively searches for a target read bias TRB for a first word line (one of WL1 to WLn) among lines WL1 to WLn, and a target read that is preemptively searched. A history management module 1320 that generates a history including the bias TRB may be included.

In addition, the memory controller 120 according to embodiments of the present invention monitors the read count value READ_COUNT and compares the read count value with the threshold value TH in order to check a condition for executing the preemptive history technique. A management module 1330 and a memory address management module 1340 for managing storage and loading of memory block addresses, and the like may be further included.

14 is a block diagram schematically illustrating a computing system 1400 according to embodiments of the present invention.

Referring to FIG. 14, a computing system 1400 according to embodiments of the present invention includes a memory system 100 electrically connected to a system bus 1460, a central processing unit (CPU, 1410), and a RAM (RAM) 1420. , A UI/UX (User Interface/User Experience) module 1430, a communication module 1440 of one or more communication methods, a power management module 1450, and the like.

The computing system 1400 according to the embodiments of the present invention may be a personal computer (PC), a mobile terminal such as a smart phone or a tablet, or various electronic devices.

The computing system 1400 according to the embodiments of the present invention may further include a battery for supplying an operating voltage, and an application chipset, a graphic related module, and a camera image processor (CIS) , DRAM, etc. may be further included. In addition, it is self-evident to those who have acquired common knowledge in this field.

Meanwhile, the memory system 100 described above is a device that stores data on a magnetic disk, such as a hard disk drive (HDD), as well as a solid state drive (SSD), a universal flash (UFS). Storage) devices, eMMC (embedded MMC) devices, and the like may include devices that store data in nonvolatile memory. Non-volatile memory includes Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), Flash memory, Phase-change RAM (PRAM), Magnetic RAM (MRAM), It may include a resistive RAM (RRAM), a ferroelectric RAM (FRAM), or the like. In addition, the memory system 100 may be implemented in various types of storage devices and mounted in various electronic devices.

The embodiments of the present invention described above may provide a memory system 100, a memory controller 120, and a method of operating the memory system 100, which enable high-speed data recovery when data read-fail occurs.

In addition, embodiments of the present invention preemptively search for the optimum target read bias (TRB) for retrying data read and prepare it as a history, enabling rapid and effective data recovery in the event of data read failure. A memory system 100, a memory controller 120, and an operating method thereof may be provided.

In addition, embodiments of the present invention include the memory system 100, the memory controller 120, and the memory system 100 that preemptively search for an optimum target read bias (TRB) used in a data read operation in consideration of a deterioration state of a memory device. It can provide a method of operation.

The description above and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the technical field to which the present invention pertains, combinations of configurations without departing from the essential characteristics of the present invention Various modifications and variations, such as separation, substitution, and alteration, will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

100: memory system
110: memory device
120: memory controller
210: memory cell array
220: address decoder
230: lead and write circuit
240: control logic
250: voltage generating circuit

Claims (20)

A memory device including a plurality of memory blocks; And
A memory controller for controlling the memory device,
During an idle time, the memory controller searches for a target read bias for a first word line among a plurality of word lines in a first memory block of the memory device, and determines the target read bias. A memory system that creates a containing history.
The method of claim 1,
The first word line corresponds to an outermost word line among a plurality of word lines in the first memory block.
The method of claim 1,
The first word line corresponds to a word line adjacent to a dummy word line among a plurality of word lines in the first memory block.
The method of claim 1,
The first word line is an arbitrary word line among a plurality of word lines in the first memory block, or corresponds to a word line determined to have a possibility of causing a read fail during a read operation. The method of claim 1,
The memory controller,
A memory system for searching for a target read bias for the first word line among a plurality of word lines in the first memory block as a representative target read bias for the first memory block.

The method of claim 1,
The memory controller,
A memory system for searching for a target read bias for the first word line among a plurality of word lines in the first memory block as a representative target read bias for a group of word lines including the first word line.
The method of claim 1,
The memory controller,
When a read count value for the first memory block according to a read operation for one page in the first memory block is equal to or greater than a preset threshold value,
During the idle time, a memory system for searching for a target read bias for the first word line in the first memory block.
The method of claim 7,
The threshold value is set to be smaller than a read count value related to degradation corresponding to the first memory block.
The method of claim 1,
The memory controller,
After the history is generated, when a read failure of one page in the first memory block is performed, a read operation is retried based on the target read bias by referring to the history.
A host interface for communicating with a host;
A memory interface for communicating with the memory device; And
A control circuit for controlling the operation of the memory device,
The control circuit,
During an idle time, a target read bias for a first word line among a plurality of word lines in a first memory block of the memory device is searched, and
A memory controller that generates a history including the target read bias.
The method of claim 10,
The history is generated in units of memory blocks.

The method of claim 10,
The history is generated in units of word line groups.
The method of claim 10,
The first word line is an outermost word line among a plurality of word lines in the first memory block. The method of claim 10,
The first word line is a word line adjacent to a dummy word line among a plurality of word lines in the first memory block.
The method of claim 10,
The first word line corresponds to an arbitrary word line among a plurality of word lines in the first memory block.
In the method of operating the memory controller,
Searching for a target read bias for a first word line among a plurality of word lines in a first memory block of a memory device during an idle time; And
And generating a history including the target read bias.
The method of claim 16,
Prior to the step of searching for the target read bias,
Determining whether a read count value for the first memory block according to a read operation for one page in the first memory block exceeds a preset threshold value;
Storing a memory block address for the first memory block when the read count value exceeds the threshold value;
Determining whether the idle time is reached;
Loading a memory block address for the first memory block when the idle time is reached; And
Further comprising the step of determining whether the history exists,
If the history exists, the step of searching for the target read bias is omitted, and if the history does not exist, the step of searching for the target read bias is performed.
The method of claim 16,
The first word line corresponds to an outermost word line among a plurality of word lines in the first memory block.
The method of claim 16,
The first word line corresponds to a word line adjacent to a dummy word line among a plurality of word lines in the first memory block.
The method of claim 16,
After the step of generating the history,
And retrying a read operation using the target read bias by referring to the history when a single page in the first memory block fails to read.

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