KR102564563B1 - Memory system and operating method thereof - Google Patents

Abstract

The present technology relates to an electronic device, and relates to a memory system having improved reliability and an operating method thereof. A method of operating a controller for controlling a semiconductor memory device including a plurality of memory blocks according to the present technology includes a program command and a program address for performing a program operation on at least one page included in an open block among the plurality of memory blocks. If the generating step, the reading step of at least one page of data, and the number of fail bits included in the at least one page of data are less than or equal to a first reference value, the program command and program address are transferred to the semiconductor memory Sending to the device.

Description

Memory system and its operating method {MEMORY SYSTEM AND OPERATING METHOD THEREOF}

The present invention relates to an electronic device, and more particularly, to a memory system and an operating method thereof.

A memory system (MEMORY SYSTEM) is widely used as a data storage device for digital devices such as computers, digital cameras, MP3 players, and smart phones. Such a memory system may include a semiconductor memory device for storing data and a controller for controlling the memory device. Digital devices operate as a host of the memory system, and the controller transmits commands and data between the host and the semiconductor memory device.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si, silicon), germanium (Ge, Germanium), gallium arsenide (GaAs), and indium phospide (InP). am. Semiconductor memory devices are largely classified into volatile memory devices and nonvolatile memory devices.

A volatile memory device is a memory device in which stored data is lost when power supply is cut off. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that maintains stored data even when power supply is cut off. Non-volatile memory devices include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), and magnetic RAM (MRAM). , RRAM (Resistive RAM), FRAM (Ferroelectric RAM), and the like. Flash memory is largely classified into a NOR type and a NAND type.

An embodiment of the present invention is to provide a memory system having improved reliability and an operating method thereof.

A method of operating a controller for controlling a semiconductor memory device including a plurality of memory blocks according to an embodiment of the present invention includes a program command for performing a program operation on at least one page included in an open block among the plurality of memory blocks. and generating a program address, reading data of at least one page corresponding to the program address, and when the number of fail bits included in the data of the at least one page is less than or equal to a first reference value, the program and transmitting a command and a program address to the semiconductor memory device.

According to another embodiment of the present invention, a controller for controlling a semiconductor memory device including a plurality of memory blocks may include a memory block management unit that manages memory block state information, which is a state of the plurality of memory blocks, and a memory block state information based on the memory block state information. and a processor performing a fail bit check operation on the open block before or after performing a program operation on at least one page included in an open block among the plurality of memory blocks.

A method of operating a memory system according to another embodiment of the present invention includes performing a first fail bit check operation on at least one page included in a memory block to be programmed before performing a program operation; Performing the program operation according to a result of the check operation, performing a second fail bit operation on at least one page programmed according to the program operation, and storing the memory block according to the result of the second fail bit check operation. and storing stored data in a memory block other than the memory block.

According to an embodiment of the present invention, a memory system having improved reliability and an operating method thereof are provided.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram for explaining states of memory blocks included in the memory cell array of FIG. 1 .
Figure 3 is a block diagram showing the structure of the controller of Figure 1;
FIG. 4 is a block diagram showing the structure of the semiconductor memory device of FIG. 1 .
FIG. 5 is a diagram illustrating an example of the memory cell array of FIG. 4 .
FIG. 6 is a diagram illustrating another embodiment of the memory cell array of FIG. 4 .
FIG. 7 is a diagram illustrating another embodiment of the memory cell array of FIG. 4 .
8 is a flowchart illustrating a controller operation according to an embodiment of the present invention.
9 is a flowchart for explaining the fail bit check operation of FIG. 8 .
10 is a flowchart illustrating a program operation according to another embodiment of the present invention.
FIG. 11 is a flowchart illustrating a fail bit check operation of FIG. 10 .
12 is a flowchart illustrating an operation of a semiconductor memory device according to an exemplary embodiment of the present invention.
13 is a diagram for describing an operation of a memory system according to another exemplary embodiment of the present disclosure.
14 is a block diagram showing an embodiment for implementing the controller of FIG. 1 .
FIG. 15 is a block diagram illustrating an application example of a memory system including the controller of FIG. 14 .
FIG. 16 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 15 .

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification or application are only exemplified for the purpose of explaining the embodiment according to the concept of the present invention, and the implementation according to the concept of the present invention Examples may be embodied in many forms and should not be construed as limited to the embodiments described in this specification or application.

Embodiments according to the concept of the present invention may be applied with various changes and may have various forms, so specific embodiments are illustrated in the drawings and described in detail in the present specification or application. However, this is not intended to limit the embodiments according to the concept of the present invention to a specific disclosed form, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

Terms such as first and/or second may be used to describe various components, but the components should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from another component, e.g., without departing from the scope of rights according to the concept of the present invention, a first component may be termed a second component, and similarly The second component may also be referred to as the first component.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when an element is referred to as “directly connected” or “directly connected” to another element, it should be understood that no other element exists in the middle. Other expressions describing the relationship between elements, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", etc., should be interpreted similarly.

Terms used in this specification are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "have" are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, but one or more other features or numbers However, it should be understood that it does not preclude the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in this specification, it should not be interpreted in an ideal or excessively formal meaning. don't

In describing the embodiments, descriptions of technical contents that are well known in the technical field to which the present invention pertains and are not directly related to the present invention will be omitted. This is to more clearly convey the gist of the present invention without obscuring it by omitting unnecessary description.

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a memory system.

The memory system includes a semiconductor memory device 100 and a controller 200 .

The semiconductor memory device 100 includes a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), and a phase change memory. memory (phase-change memory: PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM) etc. In addition, the semiconductor memory device 100 in the memory system according to an embodiment of the present invention may be implemented as a three-dimensional array structure. The present invention can be applied not only to a flash memory device in which the charge storage layer is composed of a conductive floating gate (FG), but also to a charge trap flash (CTF) in which the charge storage layer is composed of an insulating film.

The semiconductor memory device 100 includes a memory cell array 110 and a peripheral circuit 120 for driving the memory cell array 110 . The memory cell array 110 includes a plurality of nonvolatile memory cells.

The peripheral circuit 120 operates in response to the control of the controller 200 . The peripheral circuit 120 may perform a program operation for storing data in the memory cell array 110 in response to control of the controller 200 . The peripheral circuit 120 may perform a read operation for reading data from the memory cell array 110 . The peripheral circuit 120 may perform an erase operation to erase data stored in the memory cell array 110 .

In an embodiment, a read operation and a program operation of the semiconductor memory device 100 may be performed in units of pages. An erase operation of the semiconductor memory device 100 may be performed in units of memory blocks.

During a program operation, the peripheral circuit 120 may receive a command indicating a program operation, a physical block address (PBA), and write data from the controller 200 . When one memory block and one page included in the corresponding memory block are selected by the physical block address PBA, the peripheral circuit 120 can program data into the selected page.

During a read operation, the peripheral circuit 120 may receive a command representing a read operation (hereinafter referred to as a read command) and a physical block address (PBA) from the controller 200 . The peripheral circuit 120 may read data from one memory block selected by the physical block address PBA and one page included therein, and output the read data to the controller 200 .

During an erase operation, the peripheral circuit 120 may receive a command indicating an erase operation and a physical block address PBA from the controller 200 . A physical block address (PBA) may specify one memory block. The peripheral circuit 120 may erase data of a memory block corresponding to the physical block address PBA.

The controller 200 controls overall operations of the semiconductor memory device 100 . The controller 200 may access the semiconductor memory device 100 in response to a request from an external host. The controller 200 commands the semiconductor memory device 100 according to a request from an external host.

As an example embodiment, the controller 200 may control the semiconductor memory device 100 to perform a program operation, a read operation, or an erase operation. During a program operation, the controller 200 provides a program command, address, and data to the semiconductor memory device 100 through a channel. During a read operation, the controller 200 may provide a read command and address to the semiconductor memory device 100 through a channel. During an erase operation, the controller 200 may provide an erase command and an address to the semiconductor memory device 100 through a channel.

The controller 200 may further include a memory block management unit 270 . During program operation, the controller 200 generates program commands and program addresses for storing data according to a request from an external host. The controller 200 may generate a program address based on memory block information included in the memory block management unit 270 .

The memory block management unit 270 may include memory block information that is state information of a plurality of memory blocks included in the memory cell array 110 of the semiconductor memory device 100 . In an embodiment, the memory block information includes bad block information, which is information on bad memory blocks, open block information, which is information on memory blocks in which space to store data remains, and memory in which data is not stored. It may include at least one of free block information, which is information on blocks, and closed block information, which is information on memory blocks in which there is no remaining space to store data.

The controller 200 generates a program address for storing data in either an open block or a free block based on the memory block information included in the memory block management unit 270. can

One memory block may include a plurality of pages. As a program operation for storing data in a memory block is performed, pages in which data is written and pages in which data are not written may coexist in one memory block. In particular, when one memory cell is composed of a triple level cell (TLC) storing three data bits, open blocks may continuously occur. When performing a program operation on an open block, a P/E cycling number may be used or a program operation using a complicated algorithm may be required to secure reliability of a memory device.

In an embodiment of the present invention, the reliability of an open block can be guaranteed by checking the fail bit of the page on which the program operation is performed or the page on which the program operation is performed before and/or after the program operation on the open block. . In an embodiment of the present invention, when a page to perform a program operation or a page on which a program operation is performed includes fail bits exceeding a predetermined reference value, the corresponding memory block is set as a closed block or a bad block ( bad block) to manage the memory block, the reliability of the open block can be guaranteed.

According to an embodiment of the present invention, the memory system may perform at least one fail bit check operation before performing a program operation or after performing a program operation. Alternatively, the memory system may perform a fail bit check operation on at least one page to be programmed before performing the program operation, and may perform a fail bit check operation on at least one programmed page after performing the program operation.

In an embodiment, the controller 200 may update memory block information included in the memory block manager 270 according to the result of the fail bit check operation. For example, the memory block information may be updated so that memory blocks for which there is no remaining storage space after the execution of the program operation is completed are included in the write complete block information. In an embodiment, the controller 200 may update memory block information such that memory blocks having a number of fail bits exceeding a reference value are included in bad block information. In an embodiment, the controller 200 may update memory block information such that memory blocks for which an erase operation has been completed are included in free block information.

In an embodiment of the present invention, the controller 200 transmits a read command for reading the fail bits of at least one page to be programmed to the semiconductor memory device 100 before transmitting the program command, and programs the program according to the result. It may be determined whether the number of fail bits included in at least one page to be processed exceeds a first reference value. As a result of the determination, if the number of fail bits included in the at least one page to be programmed exceeds the first reference value, the controller 200 sets the state of the memory block including the at least one page to be programmed as a write block, and A program address for programming in a memory block can be regenerated. The controller 200 may transmit a program command and a program address to the semiconductor memory device 100 when the number of fail bits included in at least one page to be programmed does not exceed the first reference value.

In an embodiment of the present invention, the semiconductor memory device 100 may perform a fail bit check operation before performing a program operation without receiving a read command for reading fail bits from the controller 200 . Specifically, upon receiving a program command from the controller 200, the semiconductor memory device 100 may determine whether the number of fail bits included in at least one page to be programmed exceeds a first reference value. The semiconductor memory device 100 may provide a fail block detection signal to the controller 200 when the number of fail bits included in at least one page to be programmed exceeds a first reference value. The controller 200 may set a state of a memory block including at least one page to be programmed as a write block, regenerate a program address for programming in another memory block, and transmit the same to the semiconductor memory device 100 . The semiconductor memory device 100 may perform a program operation according to the received program command when the number of fail bits included in at least one page to be programmed does not exceed the first reference value.

In another embodiment of the present invention, when the program operation is completed, the controller 200 transmits a read command for reading the fail bits of at least one programmed page to the semiconductor memory device 100, and according to the result It may be determined whether the number of fail bits included in at least one programmed page exceeds a second reference value. As a result of the determination, if the number of fail bits included in the at least one programmed page exceeds the second reference value, the controller 200 moves the data stored in the memory block including the at least one programmed page to another memory block. An operation may be performed and the state of the corresponding memory block may be set to a bad block. In an embodiment, the controller 200 may erase a corresponding memory block and set a state of the memory block to an erased state. The controller 200 terminates the fail bit check operation when the number of fail bits included in at least one programmed page does not exceed the second reference value.

In another embodiment of the present invention, the semiconductor memory device 100 may perform a fail bit check operation after a program operation without receiving a read command for reading fail bits from the controller 200 . When the program operation is completed, the semiconductor memory device 100 may determine whether the number of fail bits included in at least one programmed page exceeds a second reference value. The semiconductor memory device 100 may provide a fail block detection signal to the controller 200 when the number of fail bits included in at least one programmed page exceeds the second reference value. The controller 200 may perform an operation of moving data stored in a memory block including at least one programmed page to another memory block and set a state of the corresponding memory block as a bad block. In an embodiment, the controller 200 may erase a corresponding memory block and set a state of the memory block to an erased state. The semiconductor memory device 100 may terminate the program operation when the number of fail bits included in at least one programmed page does not exceed the second reference value.

In various embodiments, the semiconductor memory device 100 or the controller 200 performs a fail bit check operation on at least one page to be programmed before performing the program operation, and after performing the program operation, the at least one programmed A fail bit check operation can be performed on the page.

FIG. 2 is a diagram for explaining states of memory blocks included in the memory cell array of FIG. 1 .

Referring to FIG. 2 , the memory cell array 110 may include a plurality of memory blocks. The plurality of memory blocks may be divided into a plurality of states depending on whether or not there is a space to store data.

One memory block may include a plurality of pages. One page may include memory cells (not shown) connected to one word line. For example, each of the first to third memory blocks BLK1 to BLK3 may include first to mth pages PG1 to PGm. The memory cells included in each page are single-level cells (SLC) each storing one data bit, multi-level cells (MLC) storing two data bits, or three memory cells. It may be composed of any one of triple level cells (TLC) that stores data bits. In various embodiments, each of the memory cells may be a quad-level cell (QLC) that stores four data bits. In an embodiment, more than four data bits may be stored in a memory cell.

The first memory block BLK1 is a memory block (hereinafter referred to as a write completion block) in a write completion state (closed). All of the pages PG1 to PGm included in the first memory block BLK1 in the writing complete state store data. Therefore, data cannot be stored any more in the first memory block BLK1.

The second memory block BLK2 is a memory block (hereinafter referred to as an open block) in a writable state (open). An open block may be a memory block having a state in which data is stored in some pages and data is not stored in other pages. Since data is stored in the first to third pages PG1 to PG3 of the second memory block BLK2 and there is no stored data in the other pages, new data can be stored. Memory cells included in pages in which data is not stored may have threshold voltages in an erase state.

The third memory block BLK3 is a free memory block (hereinafter referred to as a free block). Data may be stored in all pages included in the free block. Memory cells included in the free block may have threshold voltages in an erase state.

The states of the plurality of memory blocks included in the memory cell array 100 may be stored as memory block information in the memory block management unit 270 of the controller 200 described with reference to FIG. 1 . Memory block information may be updated as states of a plurality of memory blocks change.

Figure 3 is a block diagram showing the structure of the controller of Figure 1;

Referring to FIG. 3 , the controller 200 is connected to a host and a semiconductor memory device. In response to a request from the host, the controller 200 is configured to access the semiconductor memory device. For example, the controller 200 is configured to control a read operation, a program operation, and an erase operation of the semiconductor memory device. The controller 200 is configured to provide an interface between a semiconductor memory device and a host. The controller 200 is configured to drive firmware for controlling the semiconductor memory device. The semiconductor memory device 200 includes a flash memory device.

The controller 200 includes an internal bus 210, a processor 220, a storage unit 230, an error correction circuit block (ECC) 240, a memory interface 250, a host interface 260, and a memory block management unit ( 270) may be included.

Internal bus 210 is configured to provide channels between components of controller 200 . Illustratively, the internal bus 210 may be a common channel for transmitting commands and data. In various embodiments, the internal bus 210 may include a command channel and a data channel for transmitting commands and data, respectively.

The processor 220 is configured to control overall operations of the controller 200 . The processor 220 may be configured to execute software and firmware driven by the controller 200 . The processor 220 is configured to run firmware such as a Flash Translation Layer (FTL). The flash translation layer (FTL) provides various means for controlling the semiconductor memory device 100 . The flash translation layer (FTL) may convert a logical block address into a physical block address. The flash translation layer (FTL) forms and maintains information on a mapping relationship between a logical block address and a physical block address in a table. In an embodiment, the flash translation layer (FTL) provides a means for controlling program and erase counts of memory blocks of the semiconductor memory device 100 to be uniform. For example, the flash translation layer (FTL) may provide a means of wear leveling. The flash translation layer (FTL) provides a means for minimizing the erase count of the semiconductor memory device 100 . For example, the Flash Transformation Layer (FTL) provides control means such as merge, garbage collection, and copy back.

When receiving a request from the host through the host interface 260, the processor 220 may generate a physical block address corresponding to the request.

The processor 220 may convert a logical block address included in the request of the host into a physical block address.

When the request from the host is a program request, program data may be received from the host. The processor 220 may store a physical block address, program data, and a program command corresponding to a program request in the storage unit 230 . Program commands, physical block addresses, and program data stored in the storage unit 230 may be transmitted to the semiconductor memory device 100 through the memory interface 250 .

When the request from the host is a read request, the processor 220 may store a physical block address and a read command corresponding to the read request in the storage 230 . A read command and a physical block address stored in the storage unit 230 may be transmitted to the semiconductor memory device 100 through the memory interface 250 . The semiconductor memory device 100 may access memory cells corresponding to the physical block address received from the controller 200, read data stored in the corresponding memory cells, and transmit the data to the controller 200.

When the request from the host is an erase request, the processor 220 may store a physical block address and an erase command corresponding to the erase request in the storage 230 . The erase command and the physical block address stored in the storage unit 230 may be transmitted to the semiconductor memory device 100 through the memory interface 250 . The semiconductor memory device 100 may erase a memory block corresponding to the physical block address received from the controller 200 .

The storage unit 230 may be used as a working memory of the processor 220 . Alternatively, it may be used as a buffer memory between the semiconductor memory device 100 and a host. In an embodiment, the storage unit 230 may be used as a cache memory between the semiconductor memory device 100 and a host. Also, it may be used as a buffer for temporarily storing data input from the semiconductor memory device 100 . For example, the storage unit includes static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), It may include at least one of various memories capable of random access, such as a NOR flash memory.

The error correction code (ECC) 240 may be configured to detect and correct errors in data read from the semiconductor memory device 100 .

The memory interface 250 includes a protocol for communication with the semiconductor memory device 100 . For example, the memory interface 250 may include at least one of flash interfaces such as a NAND interface and a NOR interface.

The host interface 260 includes a protocol for exchanging data between the host HOST and the controller 200 . Illustratively, the controller 200 includes a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, External (host) via at least one of various interface protocols such as Serial-ATA protocol, Parallel-ATA protocol, SCSI (small computer small interface) protocol, ESDI (enhanced small disk interface) protocol, and IDE (Integrated Drive Electronics) protocol. configured to communicate with

The memory block manager 270 manages memory blocks of the memory cell array 110 included in the semiconductor memory device 100 . The memory block management unit 270 may include memory block information indicating the state of each memory block. In an embodiment, the memory block information includes bad block information, which is information on bad memory blocks, open block information, which is information on memory blocks in which space to store data remains, and memory in which data is not stored. It may include at least one of free block information, which is information on blocks, and closed block information, which is information on memory blocks in which there is no remaining space to store data.

The processor 220 may generate a physical block address based on memory block information stored in the memory block management unit 270 . For example, the processor 220 may generate addresses of memory cells included in an open block or a free block excluding a written block and a bad block as a physical block address to store data.

In an embodiment, the processor 220 may update memory block information included in the memory block management unit 270 according to the result of the fail bit check operation. For example, the processor 220 may control the memory block management unit 270 to set states of memory blocks for which there is no more storage space after the execution of a program operation is completed to a writing complete state. Alternatively, the processor 220 may control the memory block management unit 270 to set states of memory blocks having a number of fail bits exceeding the first reference value to a writing complete state. In an embodiment, the processor 220 may control the memory block manager 270 to set memory blocks having the number of fail bits exceeding the second reference value as bad blocks. In an embodiment, the controller 200 may control the memory block management unit 270 to set memory blocks that have completed an erase operation to a free block state.

In an embodiment of the present invention, the processor 220 transmits a read command for reading the fail bits of at least one page to be programmed to the semiconductor memory device 100 before transmitting the program command, and programs the program according to the result. It may be determined whether the number of fail bits included in at least one page to be processed exceeds a first reference value. As a result of the determination, if the number of fail bits included in the at least one page to be programmed exceeds the first reference value, the processor 220 sets the state of the memory block including the at least one page to be programmed as a write block, and A program address for programming in a memory block can be regenerated. The processor 220 may transmit a program command and a program address to the semiconductor memory device when the number of fail bits included in at least one page to be programmed does not exceed the first reference value.

In an embodiment of the present invention, the semiconductor memory device may perform a fail bit check operation before performing a program operation without receiving a read command for reading fail bits from the controller 200 . Specifically, upon receiving a program command from the controller 200, the semiconductor memory device may determine whether the number of fail bits included in at least one page to be programmed exceeds a first reference value. The semiconductor memory device may provide a fail block detection signal to the controller 200 when the number of fail bits included in at least one page to be programmed exceeds a first reference value. The processor 220 may set a state of a memory block including at least one page to be programmed as a write block, regenerate a program address for programming another memory block, and transmit the same to the semiconductor memory device. The semiconductor memory device 100 may perform a program operation according to the received program command when the number of fail bits included in at least one page to be programmed does not exceed the first reference value.

In another embodiment of the present invention, when the program operation is completed, the processor 220 transmits a read command for reading the fail bits of at least one programmed page to the semiconductor memory device 100, and according to the result It may be determined whether the number of fail bits included in at least one programmed page exceeds a second reference value. As a result of the determination, if the number of fail bits included in the at least one programmed page exceeds the second reference value, the processor 220 moves the data stored in the memory block including the at least one programmed page to another memory block. An operation may be performed and the state of the corresponding memory block may be set to a bad block. The processor 220 terminates the fail bit check operation when the number of fail bits included in at least one programmed page does not exceed the second reference value.

In another embodiment of the present invention, the semiconductor memory device may perform a fail bit check operation after a program operation without receiving a read command for reading fail bits from the controller 200 . When the program operation is completed, the semiconductor memory device may determine whether the number of fail bits included in at least one programmed page exceeds a second reference value. The semiconductor memory device may provide a fail block detection signal to the controller 200 when the number of fail bits included in at least one programmed page exceeds the second reference value. The processor 220 may perform an operation of moving data stored in a memory block including at least one programmed page to another memory block and set a state of the corresponding memory block as a bad block. In an embodiment, the controller 200 may erase a corresponding memory block and set a state of the memory block to an erased state. The semiconductor memory device may terminate the program operation when the number of fail bits included in at least one programmed page does not exceed the second reference value.

In various embodiments, the processor 220 transmits a read command for reading the fail bits of at least one page to be programmed to the semiconductor memory device before transmitting the program command, performs a fail bit check operation, and performs a program operation. After that, a read command for reading fail bits of at least one programmed page may be transmitted to the semiconductor memory device to perform a fail bit check operation.

FIG. 4 is a block diagram showing the structure of the semiconductor memory device of FIG. 1 .

FIG. 5 is a diagram illustrating an example of the memory cell array of FIG. 4 .

Referring to FIG. 4 , the semiconductor memory device 100 includes a memory cell array 110 and a peripheral circuit 120 .

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 121 through row lines RL and connected to the read/write circuit 123 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an example embodiment, the plurality of memory cells are nonvolatile memory cells.

Referring to FIG. 5 , the first to z-th memory blocks BLK1 to BLKz are connected in common to the first to m-th bit lines BL1 to BLm. In FIG. 5 , for convenience of explanation, elements included in a first memory block BLK1 among a plurality of memory blocks BLK1 to BLKz are shown, and elements included in each of the remaining memory blocks BLK2 to BLKz are shown. It is omitted. It will be understood that each of the remaining memory blocks BLK2 to BLKz is configured similarly to the first memory block BLK1.

The memory block BLK1 includes a plurality of cell strings CS1_1 to CS1_m. The first to m th cell strings CS1_1 to CS1_m are connected to the first to m th bit lines BL1 to BLm, respectively.

Each of the first to m th cell strings CS1_1 to CS1_m includes a drain select transistor DST, a plurality of memory cells MC1 to MCn connected in series, and a source select transistor SST. The drain select transistor DST is connected to the drain select line DSL1. The first to n th memory cells MC1 to MCn are connected to the first to n th word lines WL1 to WLn, respectively. The source select transistor SST is connected to the source select line SSL1. The drain side of the drain select transistor DST is connected to the corresponding bit line. Drain select transistors of the first to m th cell strings CS1_1 to CS1_m are respectively connected to the first to m th bit lines BL1 to BLm. The source side of the source select transistor SST is connected to the common source line CSL. As an example embodiment, the common source line CSL may be commonly connected to the first to z-th memory blocks BLK1 to BLKz.

The drain select line DSL1, the first to n th word lines WL1 to WLn, and the source select line SSL1 are included in the row lines RL of FIG. 4 . The drain select line DSL1 , the first to n th word lines WL1 to WLn, and the source select line SSL1 are controlled by the address decoder 121 . The common source line (CSL) is controlled by control logic 125. The first to m th bit lines BL1 to BLm are controlled by the read and write circuit 123 .

Referring back to FIG. 4 , the peripheral circuit 120 includes an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input/output circuit 124, a control logic 125, and a fail bit detector ( 126).

The address decoder 121 is connected to the memory cell array 110 through row lines RL. The address decoder 121 may operate in response to control of the control logic 125 . The address decoder 121 receives the address ADDR through the control logic 125 .

As an example embodiment, a program operation and a read operation of the semiconductor memory device 100 are performed in units of pages.

The address decoder 120 is configured to decode a block address among the received addresses ADDR. The address decoder 120 selects one memory block among the memory blocks BLK1 to BLKz according to the decoded block address.

The address decoder 120 is configured to decode a row address among the received addresses ADDR. The address decoder 120 selects one word line of the selected memory block according to the decoded row address. Accordingly, one page is selected.

As an embodiment, the address decoder 120 may include an address buffer, a block decoder, and a row decoder.

The voltage generator 122 is configured to generate a plurality of voltages using an external power supply voltage supplied to the semiconductor memory device 100 . The voltage generator 122 operates in response to control of the control logic 125 .

As an example embodiment, the voltage generator 122 may generate an internal power voltage by regulating an external power voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operating voltage of the semiconductor memory device 100 .

As an example embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 122 may include a plurality of pumping capacitors that receive an internal power supply voltage, and generate a plurality of voltages by selectively activating the plurality of pumping capacitors in response to a control of the control logic 125. . The generated voltages are applied to word lines selected by the address decoder 121 .

During a program operation, the voltage generator 122 will generate a high voltage program pulse and a pass pulse lower than the program pulse. During a read operation, the voltage generator 130 will generate a read voltage and a pass voltage higher than the read voltage. During an erase operation, the voltage generator 130 will generate an erase voltage.

The read and write circuit 123 includes first to m th page buffers PB1 to PBm. The first to m th page buffers PB1 to PBm are connected to the memory cell array 110 through the first to m th bit lines BL1 to BLm, respectively. The first to m th page buffers PB1 to PBm operate in response to the control of the control logic 125 .

The first to m th page buffers PB1 to PBm communicate data with the data input/output circuit 124 . During programming, the first to m th page buffers PB1 to PBm receive data DATA to be stored through the data input/output circuit 124 and the data lines DL.

During the program operation, the first to m th page buffers PB1 to PBm receive data DATA to be stored through the data input/output circuit 124 when a program pulse is applied to the selected word line. will be transferred to the selected memory cells through the bit lines BL1 to BLm. The memory cells of the selected page are programmed according to the transferred data DATA. A memory cell connected to a bit line to which a program allowable voltage (eg, ground voltage) is applied may have a raised threshold voltage. A threshold voltage of a memory cell connected to a bit line to which a program prohibition voltage (eg, power supply voltage) is applied may be maintained. During the program verify operation, the first to m th page buffers PB1 to PBm read page data from the selected memory cells through the bit lines BL1 to BLm.

When the program operation is performed, each of the memory cells may have a threshold voltage corresponding to any one of an erase state and first to nth program states PV1 to PVn, which are distinguished based on the threshold voltage.

When a memory cell is a single level cell (SLC) storing one data bit, it may have one of an erase state and a first program state (PV1) according to the execution of a program operation. If the memory cell is a multi-level cell (MLC) storing two data bits, an erase state and any one of the first to third program states (PV1 to PV3) are programmed according to the program operation. can have When a memory cell is composed of a triple level cell (TLC) storing three data bits, an erase state and any one of the first to seventh program states (PV1 to PV7) are displayed according to the execution of a program operation. It can have program state. In an embodiment, a memory cell may store four or more data bits, and accordingly, a program state of the memory cell may increase.

During a read operation, a read voltage Vread may be applied to a word line selected by the address decoder 121 . A read voltage applied to the selected word line may have a voltage level for classifying a plurality of program states determined according to the number of data bits stored in the memory cell. For example, if the memory cell is a single level cell (SLC) storing one data bit, the first read voltage R1 for distinguishing between the erase state and the first program state PV1 is applied. It can be. When the memory cell is a multi-level cell (MLC) storing two data bits, the first to third read voltages for distinguishing the erase state and the first to third program states (PV1 to PV3), respectively (R1 to R3) may be sequentially applied. If the memory cell is a triple level cell (TLC) storing three data bits, the first to seventh read voltages for distinguishing the erase state and the first to seventh program states (PV1 to PV7), respectively. (R1 to R7) may be sequentially applied. When a read voltage is applied to the selected word line, the read/write circuit 123 reads data DATA from the memory cells of the selected page through the bit lines BL, and transfers the read data DATA to the input/output circuit 124 ) is output as

During an erase operation, the read/write circuit 123 may float the bit lines BL.

As an example embodiment, the read/write circuit 123 may include a column select circuit.

The data input/output circuit 124 is connected to the first to m th page buffers PB1 to PBm through the data lines DL. The data input/output circuit 124 operates in response to the control of the control logic 125 . During programming, the data input/output circuit 124 receives data DATA to be stored from an external controller (not shown). During a read operation, the data input/output circuit 124 receives data DATA read from the read/write circuit 123 and outputs it to an external controller.

The control logic 125 is connected to the address decoder 121 , the voltage generator 122 , the read and write circuit 123 , the data input/output circuit 124 and the fail bit detector 126 . The control logic 125 may control overall operations of the semiconductor memory device 100 . The control logic 125 receives a command CMD and an address ADDR from an external controller. The control logic 125 may control the address decoder 121, the voltage generator 122, the read and write circuit 123, the data input/output circuit 124, and the fail bit detector 126 in response to the command CMD. there is. The control logic 125 transfers the address ADDR to the address decoder 121 .

The fail bit detector 126 is connected to the first to m th page buffers PB1 to PBm and the control logic 125 . The fail bit detector 126 operates in response to control of the control logic 125 .

According to an embodiment of the present invention, any one of a first fail check voltage and a second fail check voltage may be applied to a selected word line during a fail bit check operation. Page data read from the selected memory cells may be temporarily stored in the first to m th page buffers PB1 to PBm. The first to m th page buffers PB1 to PBm may detect fail bits included in the selected memory cells in response to control of the control logic 125 . The first fail check voltage may have a voltage level for verifying a threshold voltage in an erase state. The second fail check voltage may be a voltage for reading the last programmed logical page when one memory cell is composed of a triple level cell (TLC) storing three data bits. In an embodiment, the second fail check voltage may be a read voltage for reading a Most Significant Bit (MSB). In an embodiment, the second fail check voltage may be the first read voltage R1.

The first to m th page buffers PB1 to PBm may generate fail bits indicating whether data bits of the page data match data bits in an erased state. Accordingly, the fail bits may indicate whether the threshold voltages of the selected memory cells are in an erase state. The generated fail bits are passed to the fail bit detector 126 .

The fail bit detector 126 enables a detection signal (DS) when the number of fail bits exceeds a predetermined number (first reference value or second reference value). The fail bit detector 126 disables the detection signal DS when the number of fail bits is less than or equal to the reference value. When determining whether to enable the detection signal, the first reference value is used when the fail bit of at least one page to be programmed is checked, and the first reference value is used when the fail bit of at least one page to be programmed is checked. 2 reference values may be used. In an embodiment, the second reference value may have a greater value than the first reference value.

The control logic 125 controls the peripheral circuit 120 to perform a program operation when the detection signal DS is disabled. When the detection signal DS is enabled, the control logic 125 may output a fail block detection signal SF indicating that the memory block including the selected page is a fail block.

FIG. 6 illustrates another embodiment of the memory cell array of FIG. 4 .

Referring to FIG. 6 , the memory cell array 110_2 includes a plurality of memory blocks BLK1 to BLKz. In FIG. 5 , for convenience of recognition, the internal configuration of the first memory block BLK1 is shown, and the internal configurations of the remaining memory blocks BLK2 to BLKz are omitted. It will be understood that the second to z-th memory blocks BLK2 to BLKz are configured similarly to the first memory block BLK1.

Referring to FIG. 6 , the first memory block BLK1 includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a 'U' shape. Within the first memory block BLK1, m cell strings are arranged in a row direction (ie, +X direction). In FIG. 6 , it is illustrated that two cell strings are arranged in a column direction (ie, a +Y direction). However, this is for convenience of explanation, and it will be understood that three or more cell strings may be arranged in a column direction.

Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain. It includes a selection transistor (DST).

Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an embodiment, a pillar for providing a channel layer may be provided to each cell string. As an embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

As an embodiment, source select transistors of cell strings arranged in the same row are connected to source select lines extending in a row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. In FIG. 6 , the source select transistors of the cell strings CS11 to CS1m in the first row are connected to the first source select line SSL1. Source select transistors of the cell strings CS21 to CS2m in the second row are connected to the second source select line SSL2.

As another embodiment, the source select transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p+1 to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in the +Z direction and the reverse direction, and are connected in series between the source select transistor SST and the pipe transistor PT. The p+1th to nth memory cells MCp+1 to MCn are sequentially arranged in the +Z direction and connected in series between the pipe transistor PT and the drain select transistor DST. The first to pth memory cells MC1 to MCp and the p+1 to nth memory cells MCp+1 to MCn are connected through a pipe transistor PT. Gates of the first to n th memory cells MC1 to MCn of each cell string are connected to the first to n th word lines WL1 to WLn, respectively.

As an example embodiment, at least one of the first to n th memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, a voltage or current of a corresponding cell string can be stably controlled. Accordingly, reliability of data stored in the memory block BLK1 is improved.

The gate of the pipe transistor PT of each cell string is connected to the pipeline PL.

The drain select transistor DST of each cell string is connected between a corresponding bit line and memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected to the drain select line extending in the row direction. Drain select transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. Drain select transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

Cell strings arranged in the column direction are connected to bit lines extending in the column direction. In FIG. 4 , the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the mth column are connected to the mth bit line BLm.

Memory cells connected to the same word line in cell strings arranged in a row direction constitute one page. For example, among the cell strings CS11 to CS1m in the first row, memory cells connected to the first word line WL1 constitute one page. Among the cell strings CS21 to CS2m in the second row, memory cells connected to the first word line WL1 constitute another page. When one of the drain select lines DSL1 and DSL2 is selected, cell strings arranged in one row direction are selected. When one of the word lines WL1 to WLn is selected, one page of the selected cell strings is selected.

FIG. 7 illustrates another embodiment of the memory cell array of FIG. 4 .

Referring to FIG. 7 , the memory cell array 110_3 includes a plurality of memory blocks BLK1' to BLKz'. In FIG. 7 , for convenience of recognition, the internal configuration of the first memory block BLK1′ is shown, and the internal configurations of the remaining memory blocks BLK2′ to BLKz′ are omitted. It will be understood that the second to z-th memory blocks BLK2' to BLKz' are configured similarly to the first memory block BLK1'.

The first memory block BLK1' includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Within the first memory block BLK1', m cell strings are arranged in the +X direction. In FIG. 7, it is shown that two cell strings are arranged in the +Y direction. However, this is for convenience of explanation, and it will be understood that three or more cell strings may be arranged in a column direction.

Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selector. It includes a transistor DST.

The source select transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn. Source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. As another embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' may be connected in common to one source select line.

The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. Gates of the first to n th memory cells MC1 to MCn are connected to the first to n th word lines WL1 to WLn, respectively.

As an example embodiment, at least one of the first to n th memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, a voltage or current of a corresponding cell string can be stably controlled. Accordingly, reliability of data stored in the memory block BLK1' is improved.

The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. Drain select transistors of the cell strings arranged in the row direction are connected to drain select lines extending in the row direction. Drain select transistors of the cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. Drain select transistors of the cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

As a result, the memory block BLK1' of FIG. 7 has an equivalent circuit similar to that of the memory block BLK1 of FIG. 6 except that the pipe transistor PT is excluded from each cell string.

8 is a flowchart illustrating a controller operation according to an embodiment of the present invention.

Referring to FIG. 8 , in step 801, the controller receives a program request from the host. The controller may receive data and a logic block address to be stored in the semiconductor memory device from the host.

In step 803, the controller may generate a program command that is a command for storing data and a program address that is a physical block address for storing data. In an embodiment, the controller may generate a physical block address based on states of a plurality of memory blocks included in the semiconductor memory device. For example, the controller may generate a program address to store data in at least one page included in any one of a free block and an open block.

In step 805, the controller may determine whether the program address belongs to an open block. The controller may determine whether the program address belongs to an open block based on memory block information included in the memory block management unit. The memory block information includes bad block information, which is information on bad memory blocks, open block information, which is information on memory blocks in which space to store data remains, and information on memory blocks in which data is not stored. It may include at least one of free block information and closed block information that is information on memory blocks in which there is no remaining space to store data. As a result of the determination, if the program address does not belong to the open block, step 807 is performed, and if the program address belongs to the open block, step 809 is performed.

In step 807, the controller may transmit the program command and program address generated in step 803 to the semiconductor memory device. In step 805, if the program address does not belong to the open block, the program address will belong to the free block. The controller performs a program operation without performing a fail bit check operation on the free block.

In step 809, if the program address belongs to the open block, a fail bit check operation may be performed. A specific method of performing the fail bit check operation will be described in detail in the description of FIG. 9 to be described later.

In step 811, if the fail bit check operation is PASS, a program operation is performed on the corresponding open block. If the fail bit check operation in step 811 is a fail, the program operation is not performed on the corresponding open block and the process proceeds to step 803 to generate a new program address. In an embodiment, an open block that fails in a fail bit check operation may be set to a write complete state. In this case, after performing a program operation of storing dummy data in pages in which data of a failed open block is not stored in a fail bit check operation, the write complete state may be set.

9 is a flowchart for explaining the fail bit check operation of FIG. 8 .

Referring to FIG. 9 , in step 901, the controller may detect a fail bit of at least one page included in the open block. The controller may generate a read command for reading at least one page included in the open block in order to detect the fail bit, and transmit the generated read command to the semiconductor memory device.

At least one page included in the open block may be pages corresponding to the program address generated in step 803 of FIG. 8 . In an embodiment, the operation of detecting the fail bit may be performed on all or part of pages in which open block data is not stored. When a fail bit is detected for some of the pages, according to an embodiment, some of the pages may be at least one of pages corresponding to a word line adjacent to any one of the drain select line and the source select line.

According to an embodiment, during an operation of reading at least one page included in an open block, a first fail check voltage may be applied to a selected word line. Here, the first fail check voltage may have a voltage level for verifying a threshold voltage in an erase state. The controller may receive a result of performing a read operation with the first fail check voltage on at least one page to be programmed from the semiconductor memory device.

In step 903, the controller may determine whether the number of detected fail bits exceeds a reference value. In this case, the first reference value may be used as the reference value. The first reference value indicates how many fail bits per 1 kilobyte (1 kB). In an embodiment, the first reference value may indicate 5 fail bits per 1 kB.

As a result of the determination in step 903 , if the number of detected fail bits exceeds the first reference value, the controller proceeds to step 905 to determine that the fail bit check operation has failed. Alternatively, if the number of detected fail bits does not exceed the first reference value, the controller proceeds to step 907 to determine that the fail bit check operation has passed.

10 is a flowchart illustrating a program operation according to another embodiment of the present invention.

The embodiment of FIG. 10 relates to a fail bit check operation performed after performing a program operation. Referring to FIG. 10 , in step 1001, the controller may perform a fail bit check operation on at least one programmed page. A detailed description of the fail bit check operation performed after the program operation is performed will be described in detail with reference to FIG. 11 to be described later.

In step 1003, if the fail bit check operation passes, the controller ends the fail bit check operation. In step 1003, if the fail bit check operation is a fail, the controller may control the semiconductor memory device to move data stored in the corresponding memory block to another memory block. The controller may transmit a read command for reading data of a corresponding memory block to the semiconductor memory device in order to store the data of the memory block in which the fail bit check operation has failed in a free block. Thereafter, the controller may transmit a program command and a program address to the semiconductor memory device to store the read data in the free block. In an embodiment, the controller may erase a failed memory block through a fail bit check operation and set the corresponding memory block to an erase state (not shown).

FIG. 11 is a flowchart illustrating a fail bit check operation of FIG. 10 .

Referring to FIG. 11 , in step 1101, the controller may detect a fail bit of at least one programmed page. The controller may generate a read command for reading at least one programmed page to detect the fail bit, and transmit the generated read command to the semiconductor memory device.

In an embodiment, the operation of detecting the fail bit may be performed on all or some of the pages programmed through the corresponding program operation after the program operation is completed. When detecting the fail bit for some pages, the controller may detect the fail bit of the last programmed page in the corresponding memory block.

According to an embodiment, during an operation of reading at least one programmed page, the second fail check voltage may be applied to a selected word line. The second fail check voltage may have a voltage level for verifying a threshold voltage in an erase state. Alternatively, the second fail check voltage may be a voltage for reading the last programmed logical page when one memory cell is composed of a triple level cell (TLC) storing three data bits. In an embodiment, the second fail check voltage may be a read voltage for reading a Most Significant Bit (MSB). In an embodiment, the second fail check voltage may be the first read voltage R1. The controller may receive a result of performing a read operation with the second fail check voltage on at least one programmed page from the semiconductor memory device.

In step 1103, the controller may determine whether the number of detected fail bits exceeds a reference value. In this case, the second reference value may be used as the reference value. The second reference value indicates how many fail bits per 1 kilobyte (1 kB). In an embodiment, the second reference value may indicate 50 fail bits per 1 kB. In an embodiment, the second reference value may be greater than the first reference value used in the fail bit check operation performed before the program operation is performed.

As a result of the determination in step 1103, if the number of detected fail bits exceeds the second reference value, the controller proceeds to step 1105 to determine that the fail bit check operation has failed. Alternatively, if the number of detected fail bits does not exceed the second reference value, the controller proceeds to step 1107 to determine that the fail bit check operation has passed.

12 is a flowchart illustrating an operation of a semiconductor memory device according to an exemplary embodiment of the present invention.

Unlike the embodiments of FIGS. 9 and 10 in which the controller performs a fail bit check operation before a program operation according to the program request of the host, the embodiment of FIG. 12 transmits a program command and an address, and the semiconductor memory device operates at a program voltage. It is a diagram for explaining an embodiment of performing a fail bit check operation on an open block before performing a program operation for applying .

Referring to FIG. 12 , in step 1201, the semiconductor memory device may receive a program command and a program address from the controller. The program address may be a physical block address that specifies one of memory blocks included in the semiconductor memory device and corresponds to at least one page included in the corresponding memory block.

In operation 1203, the semiconductor memory device may select at least one page to be programmed from the program address and detect a fail bit of the at least one page to be programmed. In detail, the semiconductor memory device may read data of at least one page to be programmed by applying the first fail check voltage to the selected word line. The first fail check voltage may have a voltage level for verifying a threshold voltage in an erase state.

In operation 1205, the semiconductor memory device may determine whether the number of detected fail bits exceeds a first reference value. The semiconductor memory device may read the selected page with the first fail check voltage and determine whether the number of detected fail bits exceeds a reference value based on the result. As a result of the determination, if the number of detected fail bits exceeds the first reference value, step 1207 is performed. If the number of detected fail bits does not exceed the first reference value, step 1209 is performed.

In step 1207, the semiconductor memory device may perform a program operation according to the program command and program address received in step 1201.

In operation 1209, the semiconductor memory device may output a fail block detection signal indicating that the memory block including the selected page is a fail block to the controller.

Upon receiving the fail block detection signal from the semiconductor memory device, the controller sets the state of a memory block including at least one page to be programmed as a written block, and regenerates a program address for programming another memory block to the semiconductor memory. can be transmitted to the device. In an embodiment, the semiconductor memory device may store dummy data in pages in which data of an open block to which the selected page belongs is not stored (not shown).

13 is a diagram for describing an operation of a memory system according to another exemplary embodiment of the present disclosure.

Specifically, the embodiment of FIG. 13 performs a fail bit check operation on at least one page to be programmed before performing a program operation, and performs a fail bit check operation on at least one programmed page after performing a program operation. It is a diagram showing the operation of the memory system to be performed.

Steps 1301 to 1311 in FIG. 13 may be performed according to steps 801 to 811 described with reference to FIG. 8 . In an embodiment, steps 1305 to 1311 may be performed according to steps 1201 to 1209 described with reference to FIG. 12 .

Steps 1313 to 1317 in FIG. 13 may be performed according to steps 1001 to 1005 described with reference to FIG. 10 .

In an embodiment, steps 1313 to 1317 may be performed according to the description below.

In step 1313, when the program operation is completed, the semiconductor memory device may perform a fail bit check operation on at least one programmed page. In an embodiment, the operation of detecting the fail bit may be performed on all or some of the pages programmed through the corresponding program operation after the program operation is completed. When a fail bit is detected for some pages, the semiconductor memory device may detect a fail bit of a page programmed last in a corresponding memory block.

According to an embodiment, during an operation of reading at least one programmed page, the second fail check voltage may be applied to a selected word line. The second fail check voltage may have a voltage level for verifying a threshold voltage in an erase state. Alternatively, the second fail check voltage may be a voltage for reading the last programmed logical page when one memory cell is composed of a triple level cell (TLC) storing three data bits. In an embodiment, the second fail check voltage may be a read voltage for reading a Most Significant Bit (MSB). In an embodiment, the second fail check voltage may be the first read voltage R1.

The semiconductor memory device may determine whether the number of detected fail bits exceeds a reference value. In this case, the second reference value may be used as the reference value. The second reference value indicates how many fail bits per 1 kilobyte (1 kB). In an embodiment, the second reference value may indicate 50 fail bits per 1 kB. In an embodiment, the second reference value may be greater than the first reference value used in the fail bit check operation performed before the program operation is performed.

When the number of fail bits of at least one programmed page exceeds the second reference value, the semiconductor memory device may output a fail block detection signal indicating that a memory block including the selected page is a fail block to the controller.

The controller may perform an operation of moving data stored in a memory block including at least one programmed page to another memory block, and set a state of the corresponding memory block as a bad block. In an embodiment, the controller may erase a corresponding memory block and set a state of the memory block to an erase state. The semiconductor memory device terminates the operation when the number of fail bits of at least one programmed page does not exceed the second reference value.

14 is a block diagram showing an embodiment for implementing the controller of FIG. 1 .

Referring to FIG. 14, the controller 1600 includes a random access memory (RAM) 1610, a processing unit (1620), a host interface (1630), a memory interface (1640), and an error correction block. (1650).

The processing unit 1620 controls overall operations of the controller 1600 . The RAM 1610 may be used as at least one of an operating memory of the processing unit 1620, a cache memory between the semiconductor memory device and the host, and a buffer memory between the semiconductor device and the host. The processing unit 1620 may execute the function of the processor 220 described with reference to FIG. 3 by executing firmware.

The host interface 1630 includes a protocol for performing data exchange between the host and the controller 1600 . As an embodiment, the controller 1600 may include a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, At least one of various interface protocols such as Serial-ATA protocol, Parallel-ATA protocol, SCSI (small computer system interface) protocol, ESDI (enhanced small disk interface) protocol, and IDE (Integrated Drive Electronics) protocol, private protocol, etc. It is configured to communicate with the host via one.

The memory interface 1640 interfaces with a semiconductor memory device.

The error correction block 1650 may decode data received from the semiconductor memory device using an error correction code.

FIG. 15 is a block diagram illustrating an application example of a memory system including the controller of FIG. 14 .

Referring to FIG. 15 , a memory system 2000 includes a semiconductor memory device 2100 and a controller 2200 . The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. A plurality of semiconductor memory chips are divided into a plurality of groups.

In FIG. 15 , a plurality of groups are shown to communicate with the controller 2200 through the first to k th channels CH1 to CHk, respectively. Each semiconductor memory chip will be configured and operated similarly to the semiconductor memory device 100 described with reference to FIG. 4 .

Each group is configured to communicate with the controller 2200 through one common channel. The controller 2200 may be configured similarly to the controller 200 described with reference to FIG. 3 and may be configured to control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk. . In FIG. 15, it has been described that a plurality of semiconductor memory chips are connected to one channel. However, it will be understood that the memory system 2000 may be modified such that one semiconductor memory chip is connected to one channel.

The controller 2200 and the semiconductor memory device 2100 may be integrated into one semiconductor device. As an embodiment, the controller 2200 and the semiconductor memory device 2100 may be integrated into a single semiconductor device to form a memory card. For example, the controller 2200 and the semiconductor memory device 2100 are integrated into a single semiconductor device such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), or a smart media card (SM, SMC). ), memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), universal flash memory (UFS), etc.

The controller 2200 and the semiconductor memory device 2100 may be integrated into a single semiconductor device to form a solid state drive (SSD). When the memory system is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 2000 is remarkably improved.

As another example, the memory system 2000 may be used in computers, ultra mobile PCs (UMPCs), workstations, net-books, personal digital assistants (PDAs), portable computers, web tablets, and wireless devices. A wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game device, a navigation device, a black box ), digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital video player ( digital picture player, digital video recorder, digital video player, device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, constituting a computer network It is provided as one of various components of an electronic device, such as one of various electronic devices constituting a telematics network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system.

As an exemplary embodiment, the semiconductor memory device 2100 or the memory system 2000 may be mounted in various types of packages. For example, the semiconductor memory device 2100 or the memory system 2000 may include package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP) and the like may be packaged and mounted.

FIG. 16 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 15 .

Referring to FIG. 16, a computing system 3000 includes a central processing unit 3100, a RAM 3200 (RAM, Random Access Memory), a user interface 3300, a power supply 3400, a system bus 3500, and a memory system. (2000).

The memory system 2000 is electrically connected to the central processing unit 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through a system bus 3500. Data provided through the user interface 3300 or processed by the CPU 3100 is stored in the memory system 2000 .

In FIG. 16 , the semiconductor memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200 . However, the semiconductor memory device 2100 may be configured to be directly connected to the system bus 3500 . At this time, the function of the controller 2200 will be performed by the central processing unit 3100 and RAM 3200.

In FIG. 16, the memory system 2000 described with reference to FIG. 15 is shown as being provided. However, the memory system 2000 may be replaced with the memory system described with reference to FIG. 1 . As an embodiment, the computing system 3000 may be configured to include all of the memory systems described with reference to FIGS. 1 and 15 .

As described above, although the present invention has been described with limited embodiments and drawings, the present invention is not limited to the above embodiments, and those skilled in the art in the field to which the present invention belongs can make various modifications and variations from these descriptions. this is possible

Therefore, the scope of the present invention should not be limited to the described embodiments and should not be defined, and should be defined by not only the claims to be described later, but also those equivalent to these claims.

In the above-described embodiments, all steps may be selectively performed or omitted. Also, the steps in each embodiment do not necessarily have to occur in order and can be reversed. On the other hand, the embodiments of the present specification disclosed in the present specification and drawings are only presented as specific examples to easily explain the technical content of the present specification and help understanding of the present specification, and are not intended to limit the scope of the present specification. That is, it is obvious to those skilled in the art that other modified examples based on the technical spirit of the present specification can be implemented.

On the other hand, preferred embodiments of the present invention have been disclosed in the present specification and drawings, and although specific terms have been used, they are only used in a general sense to easily explain the technical content of the present invention and help understanding of the present invention. It is not intended to limit the scope of the invention. It is obvious to those skilled in the art that other modified examples based on the technical idea of the present invention can be implemented in addition to the embodiments disclosed herein.

100: semiconductor memory device
110: memory cell array
120: peripheral circuit
200: controller
270: memory block management unit

Claims (19)

A method of operating a controller for controlling a semiconductor memory device including a plurality of memory blocks, comprising:
generating a program command and a program address for performing a program operation on at least one page included in an open block among the plurality of memory blocks;
reading data of at least one page corresponding to the program address; and
and transmitting the program command and program address to the semiconductor memory device when the number of fail bits included in the at least one page of data is less than or equal to a first reference value. ◈Claim 2 was abandoned when the registration fee was paid.◈ According to claim 1,
If the number of fail bits included in the data of the page exceeds a first reference value, generating a program command and a program address for performing a program operation on a memory block other than the open block; method. ◈Claim 3 was abandoned when the registration fee was paid.◈ According to claim 2,
programming dummy data in at least one page in which data of the open block is not stored; and
The method of operating a controller further comprising setting the open block to an erase state. ◈Claim 4 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the first reference value,
The operating method of the controller, which is the number of preset fail bits per 1 kilobyte (1 kB). ◈Claim 5 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the at least one page,
A page corresponding to a word line adjacent to any one of the drain selection line and the source selection line of the open block. ◈Claim 6 was abandoned when the registration fee was paid.◈ The method of claim 1, wherein the reading of data of the at least one page comprises:
transmitting a read command for the at least one page to a semiconductor memory device;
and receiving data obtained by reading the data of the at least one page with a first fail check voltage from the semiconductor memory device. ◈Claim 7 was abandoned when the registration fee was paid.◈ 7. The method of claim 6, wherein the first fail check voltage comprises:
The operating method of the controller, which is the voltage level that verifies the threshold voltage of the erased state. ◈Claim 8 was abandoned when the registration fee was paid.◈ According to claim 1,
reading data of at least one programmed page when the program operation according to the program command is completed; and
moving data of a memory block including the at least one programmed page to a memory block other than the open block when the number of fail bits included in the data of the at least one programmed page exceeds a second reference value; A method of operating a controller that further includes ; ◈Claim 9 was abandoned when the registration fee was paid.◈ The method of claim 8, wherein the second reference value,
A method of operating a controller having a value greater than the first reference value. ◈Claim 10 was abandoned when the registration fee was paid.◈ 9. The method of claim 8, wherein when a program operation according to the program command is completed, reading data of at least one programmed page comprises:
transmitting a read command for the at least one programmed page to a semiconductor memory device;
and receiving data obtained by reading data of the at least one programmed page as a second fail check voltage from the semiconductor memory device. ◈Claim 11 was abandoned when the registration fee was paid.◈ 11. The method of claim 10, wherein the second fail check voltage comprises:
A read voltage for classifying memory cells included in the at least one programmed page into an erase state and a program state. ◈Claim 12 was abandoned when the registration fee was paid.◈ The method of claim 8, wherein the at least one programmed page,
A method of operating a controller that is a page programmed last in the program operation among a plurality of pages included in the open block. A controller for controlling a semiconductor memory device including a plurality of memory blocks,
a memory block management unit managing memory block state information, which is a state of the plurality of memory blocks; and
Before performing a program operation on at least one page included in an open block among the plurality of memory blocks based on the memory block state information, a fail bit check operation is performed on at least one page among pages to be programmed. and a processor configured to generate a program command and a program address for performing the program operation when the number of fail bits included in the at least one page of data is less than or equal to a first reference value. ◈Claim 14 was abandoned when the registration fee was paid.◈ The method of claim 13, wherein the processor,
At least one page of data included in the open block is read, and if the number of fail bits included in the at least one page of data exceeds a first reference value, a program operation is performed on a memory block other than the open block. A controller that generates program commands and program addresses to execute. ◈Claim 15 was abandoned when the registration fee was paid.◈ The method of claim 13, wherein the processor,
programming dummy data in at least one page in which data of the open block is not stored;
The memory block management unit,
A controller that sets the open block to an erase state. ◈Claim 16 was abandoned when the registration fee was paid.◈ The method of claim 14, wherein the processor,
If the data of at least one programmed page is read according to the program operation, and the number of fail bits included in the data of the at least one programmed page exceeds a second reference value, the at least one programmed page is included. A controller that moves the data of the opened memory block to a memory block other than the open block. ◈Claim 17 was abandoned when the registration fee was paid.◈ The method of claim 16, wherein the second reference value,
A controller having a value greater than the first reference value. ◈Claim 18 was abandoned when the registration fee was paid.◈ The method of claim 16, wherein the processor,
erasing a memory block including at least one programmed page;
The memory block management unit,
A controller that sets a memory block including the at least one programmed page to a free block state. performing a first fail bit check operation on at least one page included in a memory block to be programmed before performing a program operation;
performing the program operation according to a result of the first fail bit check operation;
performing a second fail bit check operation on at least one page programmed according to the program operation; and
and storing the data stored in the memory block in a memory block other than the memory block according to a result of the second fail bit check operation.

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