KR20150003053A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device according to an embodiment of the present invention, which can mitigate the deterioration of display quality, comprises: a liquid crystal display panel including data lines, gate lines crossing the data lines, and a pixel array having a plurality of sub-pixels arranged in a crossing region defined by the data lines and the gate lines; a data driving circuit to convert digital video data into data voltages and supply the data voltages to the data lines; and a gate driving circuit to sequentially supply gate pulses to the gate lines, wherein the two data lines are arranged between the sub-pixels, and when one sub-pixel is connected to the data line arranged on one side thereof, each sub-pixel adjacent to the sub-pixel is connected to the data line arranged on the other side of the sub-pixel.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

BACKGROUND ART [0002] Liquid crystal display devices are becoming increasingly widespread due to features such as light weight, thinness, and low power consumption driving. BACKGROUND ART Liquid crystal display devices are widely used as portable computers such as notebook PCs, office automation devices, audio / video devices, indoor and outdoor advertisement display devices, and the like.

The liquid crystal display controls an electric field applied to the liquid crystal layer to modulate light incident from the backlight unit to display an image. Specifically, a liquid crystal display device includes a plurality of pixels arranged in a matrix form by an intersection structure of data lines and gate lines. Each of the pixels includes a pixel electrode, a storage capacitor, and the like, and is connected to the gate line and the data line through the thin film transistor. The thin film transistor supplies the data voltage of the data line to the pixel electrode in response to the gate pulse of the gate line. Each of the pixels drives light of the liquid crystal layer by the electric field between the data voltage of the pixel electrode and the common voltage of the common electrode, thereby modulating the light incident from the backlight unit.

Recently, UHD (Ultra High Definition) liquid crystal display devices have been developed which further enhance the display quality of images according to market demand. A liquid crystal display of FHD (Full High Definition) has a resolution of 1920 x 1080, while a liquid crystal display of UHD has a resolution of 3840 x 2160. The liquid crystal display of the FHD includes 1920 x 1080 pixels to represent the resolution of 1920 x 1080, while the liquid crystal display of the UHD includes 3840 x 2160 pixels to represent the resolution of 3840 x 2160.

1 is an exemplary view showing pixels of a display panel of a conventional UHD liquid crystal display device. 2 is a diagram illustrating an example of a gate pulse supplied to a j-th gate line and data voltages supplied to a k-th data line of a conventional UHD liquid crystal display device. Referring to Figs. 1 and 2, each of the pixels is connected to a gate line and a data line through a thin film transistor (T). The gate pulse GPj swings between the gate high voltage VGH and the gate low voltage VGL and the data voltage DVk swings to the positive polarity or the negative polarity with reference to the common voltage Vcom . The thin film transistor is turned on by the gate high voltage VGH of the gate pulse and turned off by the gate low voltage VGL. The thin film transistor supplies the data voltage DVk of the kth data line Dk to the pixel electrode in response to the gate pulse GPj of the gate high voltage VGH during the first period t1, and is turned off by the gate pulse GPj of the gate low voltage VGL from the time t2. The pixel electrode can maintain the data voltage supplied during the first period t1 for one frame period due to the storage capacitor.

On the other hand, in the UHD liquid crystal display device, the gate pulse load is increased due to the increase in the number of pixels, so that falling of the gate pulse may be delayed as shown in FIG. In this case, since the data voltage varies before the polling of the gate pulse is completed, the data voltage supplied to the pixel electrode during the first period t1 is affected by the data voltage during the second period t2. At this time, as shown in FIG. 2, when the data voltage in the first period t1 is the peak white gradation voltage and the data voltage in the second period t2 is the peak black gradation voltage, The greater the difference d between the data voltage of the first period t1 and the data voltage of the second period t2 is, the larger the influence of the data voltage supplied to the pixel electrode during the first period t1 is on the data voltage of the second period t2. In this case, since the pixel can not express the gradation to be originally expressed, there is a problem that the display quality of the liquid crystal display device is lowered.

The peak black gradation voltage is a voltage that allows a pixel to express a peak black gray scale. The peak black gradation voltage is a common voltage (Vcom) And the peak white gradation voltage is a voltage that allows the pixel to express a peak white gray scale and can be implemented with a voltage having the largest difference from the common voltage Vcom.

The present invention provides a liquid crystal display device capable of improving the display quality deterioration even when polling of a gate pulse is delayed.

A liquid crystal display according to an embodiment of the present invention includes data lines, gate lines intersecting the data lines, and a plurality of subpixels arranged in a crossing region defined by the data lines and the gate lines A liquid crystal display panel including a formed pixel array; A data driving circuit for converting digital video data into data voltages and supplying the data voltages to the data lines; And a gate driving circuit for sequentially supplying gate pulses to the gate lines, wherein two data lines are arranged between the subpixels, and one of the subpixels is connected to a data line arranged at one side of the subpixel Each of the sub pixels neighboring the sub pixel is connected to a data line disposed on the other side of each of the sub pixels.

The present invention designs a pixel array of a liquid crystal display panel so as to supply a gate pulse at a gate high voltage for one horizontal period and supply the same data voltage for two horizontal periods. Therefore, the present invention can uniformly supply the same data voltage to the pixel electrodes from rising to polling of the gate pulse. As a result, the present invention can accurately express the gradation originally expressed by the pixel even in the case of the polling delay of the gate pulse, so that deterioration of display quality can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an exemplary view showing pixels of a display panel of a conventional UHD liquid crystal display; FIG.
2 is a view showing an example of a gate pulse supplied to a j-th gate line and data voltages supplied to a k-th data line of a conventional UHD liquid crystal display device.
3 is an exemplary view showing a liquid crystal display device according to an embodiment of the present invention.
4 is an exemplary illustration showing in detail a portion of subpixels of the pixel array of FIG. 3;
5 is a waveform diagram showing gate pulses and data voltages according to a first embodiment of the present invention;
6 is an exemplary view showing gate pulses supplied to the j-th gate line of FIG. 5 and data voltages supplied to the k-th data line.
7 is a waveform diagram showing gate pulses and data voltages according to a second embodiment of the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

3 is a view illustrating an example of a liquid crystal display according to an embodiment of the present invention. 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit, and a gate driving circuit 13 formed with a pixel array PA, Respectively.

The liquid crystal display panel 10 includes an upper substrate and a lower substrate facing each other with a liquid crystal layer interposed therebetween. A pixel array PA is formed on the liquid crystal display panel. The pixel array PA displays video data using pixels arranged in a matrix form by an intersection structure of the data lines and the gate lines. Each of the pixels includes a plurality of subpixels, for example, each of the pixels may comprise a red subpixel, a green subpixel, and a blue subpixel. Data lines, gate lines, TFTs (thin film transistors), pixel electrodes of subpixels connected to TFTs, and storage capacitors connected to the pixel electrodes are formed on the lower substrate of the pixel array PA do. Each of the subpixels of the pixel array PA drives the liquid crystal of the liquid crystal layer by the electric field between the pixel electrode through which the data voltage is charged through the TFT and the common electrode to which the common voltage is applied, do. On the other hand, when the liquid crystal display device is implemented in UHD (Ultra High Definition), the pixel array P may be implemented to include 3840 × 2160 pixels to represent a resolution of 3840 × 2160. The detailed structure of the pixel array PA will be described in detail with reference to FIG.

On the upper substrate of the liquid crystal display panel, a black matrix and color filters are formed. The common electrode is formed on the upper substrate in the case of a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode may be formed in the IPS (In-Plane Switching) mode and the FFS And is formed on the lower substrate together with the pixel electrode in the case of the horizontal electric field driving method. The liquid crystal display of the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. On the upper substrate and the lower substrate of the liquid crystal display panel, an alignment film is formed to attach a polarizing plate and set a pre-tilt angle of the liquid crystal.

A backlight unit (not shown) for uniformly irradiating light to the liquid crystal display panel 10 may be disposed under the liquid crystal display panel 10. The backlight unit may be implemented as a direct type or an edge type.

The data driving circuit includes a plurality of source drive integrated circuits (ICs) 12. The source drive ICs 12 are mounted on a TCP (Tape Carrier Package) 15, bonded to a lower glass substrate of a liquid crystal display panel by a TAB (Tape Automated Bonding) process, . Alternatively, the source drive ICs 12 may be bonded onto a lower glass substrate of the liquid crystal display panel by a COG (Chip On Glass) process. Each of the source drive ICs 12 receives the digital video data and the source timing control signal from the timing controller 11. The source drive ICs 12 convert the digital video data into positive / negative data voltages in response to the source timing control signal and supply them to the data lines of the pixel array PA.

The gate drive circuit 13 is mounted on the TCP and can be bonded to the lower glass substrate of the liquid crystal display panel 10 by the TAB process. Alternatively, the gate drive circuit 13 may be formed directly on the lower glass substrate simultaneously with the pixel array PA by a GIP (Gate In Panel) process. The gate drive circuit 13 may be disposed on either side of the pixel array PA or on one side of the pixel array PA as shown in FIG. The gate drive circuit 13 receives the gate timing control signal from the timing controller 11. [ The gate driving circuit 13 sequentially supplies gate pulses (or scan pulses) to the gate lines of the pixel array in response to the gate timing control signal.

The timing controller 11 receives digital video data, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and timing signals such as a dot clock from an external system board. The timing controller 11 generates a timing control signal for controlling the operation timing of the source drive ICs 12 based on the digital video data and timing signals and a gate timing control signal for controlling the operation timing of the gate drive circuit 13 And generates a control signal. The timing controller 11 supplies digital video data and a source timing control signal to the source drive ICs 12. [ The timing controller 11 supplies a gate timing control signal to the gate drive circuit 13. [ The timing controller 11 is mounted on the control PCB 16. The control PCB 16 and the source PCB 14 are connected through a flexible circuit board 17 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

FIG. 4 is an exemplary view showing a part of subpixels of the pixel array of FIG. 3 in detail. In FIG. 4, for the sake of convenience of explanation, the (j is a natural number) to the (j + 3) th gate lines Gj, Gj + 1, Gj + 2 and Gj + Only the 2k + 6 data lines (D2k-1, D2k, D2k + 1, D2k + 2, D2k + 3, D2k + 4, D2k + 5, D2k + 6, D2k + 7) . In FIG. 4, the i-th (i is a natural number) subpixel P (i, j) of the j-th horizontal line indicates the i-th subpixel among the subpixels .

Referring to FIG. 4, two data lines are arranged between subpixels. Further, when a subpixel is connected to a data line disposed on one side of the subpixel, each of the subpixels neighboring the subpixel is connected to a data line disposed on the other side of each of the subpixels. For example, since the (i + 1, j + 1) th subpixel of the (i + 1) th horizontal line is connected to the (2 + 1) th data line D2k + The i-th sub-pixel P (i + 1) of the (j + 1) -th horizontal line neighboring in the horizontal direction (x-axis direction) to the (i + 1, j + 1) i, j + 1) may be connected to the second k data line D2k disposed on the right side thereof. (J + 1) th horizontal line which is another subpixel neighboring in the horizontal direction (x axis direction) to the (i + 1, j + 1) th subpixel of the (j + The i + 2 subpixel P (i + 2, j + 1) may be connected to the second k + 4 data line D2k + 4 arranged on the right side thereof. (I + 1, j + 1) of the j-th horizontal line which is a subpixel neighboring in the vertical direction (y-axis direction) to the i + 1th subpixel P The subpixel P (i + 1, j) may also be connected to the second k + 2 data line D2k + 2 arranged on the right side thereof. (I + 1, j + 1) of the (j + 2) -th horizontal line, which is another subpixel neighboring in the vertical direction The i + 1 subpixel P (i + 1, j + 2) may be connected to the second k + 2 data line D2k + 2 arranged on the right side thereof.

Also, the polarity of the data voltage supplied to one subpixel is opposite to the polarity of the data voltage supplied to each of the subpixels neighboring the subpixel. For example, the polarity of the data voltage supplied to the i + 1-th subpixel P (i + 1, j + 1) of the j + 1 horizontal line is positive (+ (I, j + 1) of the (j + 1) th horizontal line neighboring in the horizontal direction (x axis direction) to the i + 1th subpixel P 1) th sub-pixel of the j-th horizontal line neighboring in the vertical direction (y-axis direction) and the i + 2 subpixels P (i + 2, j + 1) (-) of the data voltage supplied to the pixel P (i + 1, j) and the i + 1th subpixel P (i + 1, j + 2) of the j + 2 horizontal line.

Also, the subpixels arranged in one horizontal line are connected to the same gate line. For example, the subpixels arranged on the j th horizontal line are connected to the j th gate line only, and the subpixels arranged on the j th + 1 horizontal line can be connected to the j th + 1 gate line only.

5 is a waveform diagram showing gate pulses and data voltages according to the first embodiment of the present invention. 5, a j-th gate pulse GPj supplied to the j-th gate line Gj, a (j + 1) -th gate pulse GPj + 1 supplied to the (j + 1) -th gate line Gj + And a (j + 2) -th gate pulse GPj + 2 supplied to the two-gate line Gj + 2. 5, the second k-1 data voltage DV2k-1 supplied to the 2k-1 data line D2k-1, the 2k data voltage DV2k supplied to the 2k data line D2k, The second k + 2 data voltage DV2k + 2 supplied to the 2k + 1 data line D2k + 1, the (2k + 1) Respectively.

Referring to FIG. 5, the gate drive circuit 13 sequentially supplies gate pulses to the gate lines. As a result, the subpixels arranged on any one horizontal line are simultaneously supplied with the data voltages. That is, the subpixels are supplied with the data voltages in units of horizontal lines.

Specifically, the gate driving circuit 13 supplies the gate pulse at a gate high voltage for one horizontal period (1H) as shown in FIG. Further, the gate drive circuit 13 supplies one gate pulse to each of the gate lines, and supplies the gate pulse to the gate lines while shifting the gate pulse by a predetermined period. For example, the gate driving circuit 13 can supply gate pulses to the gate lines while shifting by one horizontal period (1H) as shown in FIG. In this case, the phase of the gate pulse supplied to one gate line differs from the phase of the gate pulse supplied to each of the gate lines adjacent to the gate line by one horizontal period (1H). For example, the gate driving circuit 13 supplies the j-th gate pulse GPj to the gate high voltage VGH during the first period t1 and supplies the j + 1 gate pulse (j + 1) during the second period t2 2 gate pulse GPj + 1 to the gate high voltage VGH and supplies the j + 2 gate pulse GPj + 2 to the gate high voltage VGH during the third period t3. Each of the first to third periods t1, t2 and t3 corresponds to one horizontal period (1H), the second period t2 continues to the first period t1, the third period t3 corresponds to the first period And continues in the second period t2. One horizontal period (1H) is a period for supplying data voltages to the subpixels arranged in one horizontal line, and indicates one line scanning period.

The source drive ICs 12 simultaneously supply the data voltages to the data lines. The source drive ICs 12 supply the same data voltage to each of the data lines for two horizontal periods (2H) as shown in Fig. At this time, the phase of the data voltage supplied to one data line differs from the phase of the data voltage supplied to the data line adjacent to the data line by one horizontal period (1H). In this case, the phase of the data voltage supplied to one of the data lines may be substantially equal to the phase of the data voltage supplied to the data line adjacent to the other side of the data line. For example, the phase of the second k data voltage DV2k supplied to the second k data line D2k is supplied to the second k-1 data line D2k-1, which is adjacent to the left side of the second k data line D2k Is different by one horizontal period (1H) from the phase of the (2k-1) -th data voltage (DV2k-1). However, the phase of the second k data voltage DV2k supplied to the second k data line D2k is different from the phase of the second k data voltage DV2k supplied to the second k + 1 data line D2k + 1, which is right adjacent to the second k data line D2k. Is substantially the same as the phase of the +1 data voltage DV2k + 1. The phase of the second k + 1 data voltage DV2k + 1 supplied to the (2k + 1) -th data line D2k + 1 is the phase of the (2k + 1) th data line D2k + And the phase of the second k + 2 data voltage DV2k + 2 supplied to the data line D2k + 2 by one horizontal period (1H). However, the phase of the second k + 1 data voltage DV2k + 1 supplied to the (2k + 1) -th data line D2k + 1 is the phase of the second k data line D2k + Is substantially the same as the phase of the second k data voltage (DV2k) supplied to the second data line (D2k). That is, in the first embodiment of the present invention, the phase of the second k-1 data voltage DV2k-1 and the phase of the second k + 2 data voltage DV2k + 2 are substantially the same, And the phase of the (2k + 1) th data voltage DV2k + 1 are substantially the same. The phase of the (2k + 1) -th data voltage DV2k-1 and the phase of the (2k + 2) -th data voltage DV2k + ) And one horizontal period (1H).

In addition, the source drive ICs 12 output the data voltages in a column inversion manner. The column inversion method supplies data voltages of opposite polarities to data lines neighboring in the horizontal direction (x-axis direction), and a method of maintaining the polarities of the data voltages supplied to each of the data lines for a predetermined period of time . For example, as shown in FIG. 5, a negative (-) data voltage DV2k is supplied to the second k data line D2k, and a data voltage DV2k supplied to the second k data line D2k, (+) Data voltages DV2k-1 and DV2k + 1 are supplied to the (2k-1) th data line D2k-1 and the (2k + 1) th data line D2k + 1. That is, although the embodiment of the present invention supplies the data voltages to the data lines in the version scheme in which each of the source drive ICs 12 is a column, by connecting the subpixels to the data lines as shown in FIG. 4, Lt; / RTI > is driven in a similar manner to the dot-in version scheme, which is charged with the data voltages of opposite polarity to the neighboring subpixels. Thus, the embodiment of the present invention can remarkably reduce the power consumption in the column-type version system and can be operated in a similar manner to the dot-inversion system, thereby suppressing the after-image after-image of liquid crystal, flicker, There are advantages.

6 is an exemplary view showing gate pulses supplied to the j-th gate line of FIG. 5 and data voltages supplied to the 2k-1 data line. Referring to FIG. 6, in the UHD liquid crystal display device, the gate pulse load is increased due to an increase in the number of pixels, so that the falling of the gate pulse may be delayed as shown in FIG.

However, in the embodiment of the present invention, since the gate pulse is supplied at the gate high voltage for one horizontal period (1H), while the data voltage is maintained for the two horizontal periods (2H), the data voltage fluctuates before the polling of the gate pulse is completed It does not. 6, when the data voltages in the first and second periods t1 and t2 are the peak white gradation voltages and the data voltages in the third and fourth periods t3 and t4 are the peak black gradation voltages, (D) between the data voltages of the first period (t1, t2) and the second period (t1, t2) and the data voltages of the third period (t3, t4) is large, the data voltages supplied to the pixel electrodes It is constant. Therefore, since the gradation that the pixel originally intended to represent can be accurately expressed, deterioration in display quality of the liquid crystal display device can be improved.

6, the peak black gradation voltage is a voltage that allows the pixel to express a peak black gray scale. The peak black gradation voltage is a common voltage Vcom, And the peak white gradation voltage is a voltage that allows the pixel to express a peak white gray scale and can be implemented with a voltage having the largest difference from the common voltage Vcom.

7 is a waveform diagram showing gate pulses and data voltages according to a second embodiment of the present invention. 7, a j-th gate pulse GPj supplied to the j-th gate line Gj, a (j + 1) -th gate pulse GPj + 1 supplied to the (j + 1) -th gate line Gj + And a (j + 2) -th gate pulse GPj + 2 supplied to the two-gate line Gj + 2. 7, the second k-1 data voltage DV2k-1 supplied to the 2k-1 data line D2k-1, the 2k data voltage DV2k supplied to the 2k data line D2k, The second k + 2 data voltage DV2k + 2 supplied to the 2k + 1 data line D2k + 1, the (2k + 1) Respectively.

Referring to FIG. 7, the gate drive circuit 13 sequentially supplies gate pulses to the gate lines. In particular, the gate drive circuit 13 simultaneously supplies gate pulses to two neighboring gate lines. As a result, the subpixels arranged on the two neighboring horizontal lines are simultaneously supplied with the data voltages. That is, the subpixels are supplied with the data voltages in units of two horizontal lines.

Specifically, the gate drive circuit 13 supplies the gate pulse at a gate high voltage for one horizontal period (1H) and supplies one gate pulse to each of the gate lines as shown in FIG. In addition, the gate driving circuit 13 may be configured such that the phase of a gate pulse supplied to two neighboring gate lines is the same as the phase of a gate pulse supplied to two neighboring two gate lines adjacent to the neighboring two gate lines Gate pulses are supplied so that the phase is shifted by two horizontal periods (2H). For example, the gate driving circuit 13 supplies the j-th gate pulse GPj and the j + 1-th gate pulse GPj + 1 to the gate high voltage VGH during the first period t1, The gate high voltage VGH is supplied to the (j + 2) th gate pulse GPj + 2 and the (j + 3) th gate pulse GPj + 3 during the period t3. Thus, the phase of each of the jth and j + 1 gate pulses GPj and GPj + 1 is different from the phase of each of the (j + 2) th and (j + 3) th gate pulses GPj + 2 and GPj + And the horizontal period (2H). On the other hand, each of the first to third periods t1, t2 and t3 corresponds to one horizontal period (1H), the second period t2 continues to the first period t1, the third period t3 ) Continues in the second period (t2). One horizontal period (1H) is a period for supplying data voltages to the subpixels arranged in one horizontal line, and indicates one line scanning period.

The source drive ICs 12 simultaneously supply the data voltages to the data lines. The source drive ICs 12 supply the same data voltage to each of the data lines for two horizontal periods (2H) as shown in Fig. At this time, the phase of the data voltage supplied to one of the data lines is the same as the phase of the data voltage supplied to each of the data lines adjacent to both of the data lines. For example, the phase of the second k data voltage DV2k supplied to the second k data line D2k is supplied to the second k-1 data line D2k-1, which is adjacent to the left side of the second k data line D2k Is substantially the same as the phase of the (2k-1) -th data voltage DV2k-1. The phase of the second k data voltage DV2k supplied to the second k data line D2k is the same as the phase of the second k data voltage D2k supplied to the (2k + 1) th data line D2k + 1 adjacent to the right side of the second k data line D2k. Is substantially the same as the phase of the +1 data voltage DV2k + 1. That is, in the second embodiment of the present invention, the phases of the respective data voltages supplied to the data lines of the pixel array PA are substantially the same.

In addition, the source drive ICs 12 output the data voltages in a column inversion manner. The column inversion method supplies data voltages of opposite polarities to data lines neighboring in the horizontal direction (x-axis direction), and a method of maintaining the polarities of the data voltages supplied to each of the data lines for a predetermined period of time . For example, as shown in FIG. 7, a negative (-) data voltage DV2k is supplied to the second k data line D2k and a negative (-) data voltage DV2k is supplied to the second k data line D2k in the horizontal direction (+) Data voltages DV2k-1 and DV2k + 1 are supplied to the (2k-1) th data line D2k-1 and the (2k + 1) th data line D2k + 1. That is, although the embodiment of the present invention supplies the data voltages to the data lines in the version scheme in which each of the source drive ICs 12 is a column, by connecting the subpixels to the data lines as shown in FIG. 4, Lt; / RTI > is driven in a similar manner to the dot-in version scheme, which is charged with the data voltages of opposite polarity to the neighboring subpixels. Thus, the embodiment of the present invention can remarkably reduce the power consumption in the column-type version system and can be operated in a similar manner to the dot-inversion system, thereby suppressing the after-image after-image of liquid crystal, flicker, There are advantages.

As described above, in the second embodiment of the present invention, since the gate pulse is supplied at the gate high voltage for one horizontal period (1H) while the data voltage is maintained for the two horizontal periods (2H), the polling of the gate pulse is completed The data voltage does not fluctuate. 6, when the data voltage in the first period t1 is the peak white gradation voltage and the data voltage in the second period t2 is the peak black gradation voltage, the data voltage in the first period t1 and the data voltage in the second period t2, The data voltage supplied to the pixel electrode is constant from rising to polling of the gate pulse even if the difference d between the data voltages in the period t2 is large. Therefore, the gradation that the pixel originally intended to represent can be accurately expressed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: liquid crystal display panel 11: timing controller
12: Source drive IC 13: Gate drive circuit
PA: pixel array

Claims (10)

A liquid crystal display panel including a pixel array in which data lines, gate lines intersecting with the data lines, and a plurality of subpixels arranged in a crossing region defined by the data lines and the gate lines are formed;
A data driving circuit for converting digital video data into data voltages and supplying the data voltages to the data lines; And
And a gate driving circuit for sequentially supplying gate pulses to the gate lines,
Two data lines are arranged between the subpixels,
When a subpixel is connected to a data line disposed on one side of the subpixel, each of the subpixels neighboring the subpixel is connected to a data line arranged on the other side of each of the subpixels Liquid crystal display device. The method according to claim 1,
The gate driving circuit supplies the gate pulse at a gate high voltage for one horizontal period,
Wherein the data driving circuit supplies the same data voltage for two horizontal periods. 3. The method of claim 2,
The phase of the data voltage supplied to one of the data lines differs from the phase of the data voltage supplied to the data line adjacent to the one data line and the phase of the data voltage to the data line adjacent to the other data line And the phase of the supplied data voltage is equal to the phase of the supplied data voltage. The method of claim 3,
Wherein a phase of a gate pulse supplied to one of the gate lines is different from a phase of a gate pulse supplied to each of the gate lines adjacent to the gate line by one horizontal period. 3. The method of claim 2,
And the phases of the data voltages supplied to the data lines are equal to each other. 6. The method of claim 5,
The gate drive circuit includes:
And a gate pulse is simultaneously supplied to two adjacent gate lines. The method according to claim 6,
The gate drive circuit includes:
The phase of the gate pulse supplied to the two neighboring gate lines is different from the phase of the gate pulse supplied to another two neighboring gate lines adjacent to the neighboring two gate lines by two horizontal periods The liquid crystal display device comprising: 3. The method of claim 2,
Wherein a polarity of a data voltage supplied to one of the data lines is opposite to a polarity of a data voltage supplied to each of the data lines adjacent to the data line. 9. The method of claim 8,
And the polarity of the data voltage supplied to one of the subpixels is opposite to the polarity of the data voltage supplied to each of the subpixels adjacent to the subpixel. The method of claim 3,
Wherein the data driving circuit supplies data voltages such that the polarity is alternately inverted every predetermined period in a column-type version scheme.

Images