KR20130036909A - Driving method for display device - Google Patents

Abstract

PURPOSE: A method for driving a display device is provided to prevent a horizontal stripe fault by previously generating a gate clock signal in an initialization stage of the display device until the display device is normally operated. CONSTITUTION: Power is applied to a display device(S10). An oscillator starts operating(S20). A gate clock signal is generated and outputted to a gate driving part(S30). A signal control part grasps the property of a display panel(S40). The signal control part outputs entire control signals and image data for displaying images(S50). [Reference numerals] (S10) VCC application; (S20) Oscillator operation; (S30) CPV output; (S40) Panel characterization; (S50) Image display according to a T-con control signal;

Description

DRIVING METHOD FOR DISPLAY DEVICE}

The present invention relates to a method of driving a display device and to a method of driving a display device having an integrated gate driver.

Among the display panels, the liquid crystal display is one of the flat panel display devices most widely used, and includes two display panels on which field generating electrodes, such as a pixel electrode and a common electrode, are formed and a liquid crystal layer interposed therebetween. do. The liquid crystal display displays an image by applying a voltage to the electric field generating electrode to generate an electric field in the liquid crystal layer, thereby determining the direction of the liquid crystal molecules in the liquid crystal layer and controlling the polarization of the incident light. In addition to the liquid crystal display device, the display device includes an organic light emitting display device, a plasma display device, an electrophoretic display device, and the like.

Such a display device including a liquid crystal display includes a gate driver and a data driver. The gate driver may be patterned together with the gate line, the data line, and the thin film transistor to be integrated on the panel. The integrated gate driver does not need to form a separate gate driver chip, thereby reducing manufacturing costs.

However, the integrated gate driver may have a problem in operating reliability. That is, there is a problem that characteristics of a semiconductor (particularly an amorphous semiconductor) of a thin film transistor vary according to temperature, and as a result, a gate voltage output when using a predetermined time at a high temperature may not have a predetermined waveform and noise may occur. There is a prior art for various gate drivers to ensure that no noise occurs for high temperature noise.

In addition, the integrated gate driver may have poor operating characteristics at a low temperature, and a certain level of leakage current is generated while outputting the gate-off signal, resulting in poor power consumption.

On the other hand, the integrated gate driver not only has a problem of high temperature noise, but also may cause malfunctions from when the display device is turned on until the gate driver normally operates.

An object of the present invention is to provide a method of driving a display device having an integrated gate driver in which a malfunction does not occur even after the display device is turned on until the gate driver normally operates.

In order to solve this problem, a method of driving a display device according to an embodiment of the present invention includes the steps of turning on the power of the display device; Generating an gate clock signal by operating the oscillator upon receiving the power; Determining, by the signal controller, characteristics of the display panel; And displaying an image on the display panel according to a control signal generated by the signal controller.

The gate clock signal generated by the oscillator may be used only in an initialization step from when the display device is turned on until the display device operates normally.

The oscillator may be located inside the signal controller.

The signal controller further includes an LVDS receiver, an image data corrector, a mini LVDS transmitter, and a timing generator, wherein the control signal generated by the signal controller is configured to generate the timing based on an external clock signal received through the LVDS receiver. Can be generated from wealth.

The control signal includes the gate clock signal, and in the initializing step, the timing generator generates the gate clock signal based on the output of the oscillator. When the display device is normalized, the timing generator generates the LVDS receiver. The gate clock signal may be generated based on an external clock signal received from the gate clock signal.

The displaying of the image on the display panel according to the control signal generated by the signal controller may include a first clock signal and a second clock signal used in the gate driver of the display device based on the gate clock signal generated by the timing generator. And generating a clock signal, wherein the first clock signal has the same period as the gate clock signal but has a different voltage level, and the second clock signal may be generated by inverting the first clock signal.

The signal controller may further include an I2C transceiver and a ROM map, and the I2C transceiver and ROM map may be used by the signal controller to determine characteristics of a display panel.

The determining of the characteristics of the display panel by the signal controller may include an extended display identity data (EDID) of the display panel of the display device by using an I2C standard communication in which the signal controller transmits data through an SDA line and an SCL line. The information can be received and grasped.

The oscillator may be located outside the signal controller.

The signal controller includes an LVDS receiver, an image data corrector, a mini LVDS transmitter, and a timing generator, and the control signal generated by the signal controller is based on the external clock signal received through the LVDS receiver. Can be generated from

The control signal includes the gate clock signal, and the gate clock signal is directly generated by the oscillator in the initialization step, and when the display device is in a normal state, the timing generator generates an external clock signal received by the LVDS receiver. The gate clock signal may be generated based on the above.

Generating a first clock signal and a second clock signal used in the gate driver of the display device based on the gate clock signal generated by the oscillator or the timing generator, wherein the first clock signal is The period is the same as the gate clock signal, but different in voltage, and the second clock signal may be generated by inverting the first clock signal.

The signal controller may further include an I2C transceiver and a ROM map, and the I2C transceiver and ROM map may be used by the signal controller to determine characteristics of a display panel.

The determining of the characteristics of the display panel by the signal controller may include an extended display identity data (EDID) of the display panel of the display device by using an I2C standard communication in which the signal controller transmits data through an SDA line and an SCL line. The information can be received and grasped.

The display device includes a display area including a gate line and a gate driver connected to one end of the gate line and including a plurality of stages and integrated on a substrate, wherein the stage includes a clock signal, a first low voltage, and the first voltage. The gate voltage having the first low voltage as the gate-off voltage may be output by receiving the second low voltage lower than the low voltage, the transfer signal of at least one of the preceding stages, and the transfer signal of at least two of the next stages.

The voltage when the transfer signal is low may be the second low voltage.

The stage may include an input unit, a pull-up driver, a pull-down driver, an output unit, and a transfer signal generator.

The display device includes a display area including a gate line and a gate driver connected to one end of the gate line and including a plurality of stages and integrated on a substrate, wherein the stage includes at least one of a clock signal, a low voltage, and a front end stage. The gate voltage having the first low voltage as the gate-off voltage may be output by receiving one transfer signal and at least two transfer signals of the next stages.

The gate driver may include an input unit, a pull-up driver, a transfer signal generator, an output unit, and a pull-down driver.

As described above, since the gate clock signal CPV is generated and output in advance in the initialization step from when the display device is turned on until the display device operates normally, the clock signal generated according to the gate clock signal CPV ( CKV and CKVB control the gate driver so that no horizontal line defect occurs.

In addition, according to an embodiment of the present invention, by lowering the inside of each stage to a potential lower than the gate-off voltage (Vss2) to reduce current leakage to have low power consumption, and to reduce ripple applied through a transmission signal even at high temperatures, even at high temperatures. Output a constant gate-on voltage. In addition, even at a low temperature can be operated even if a lower voltage is applied, there is an advantage that the life is long.

1A is a plan view of a display device according to an exemplary embodiment of the present invention.
1B is a block diagram of a signal controller according to the embodiment of FIG. 1A.
FIG. 2 is a block diagram illustrating the gate driver and the gate line of FIG. 1 in detail.
FIG. 3 is an enlarged circuit diagram of one stage and one gate line in FIG. 2.
4 is a waveform diagram of a driving signal used in a display device according to an exemplary embodiment of the present invention.
5 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment of the present invention.
6 and 7 illustrate whether a display device is defective due to a change in an application timing of a driving signal according to an exemplary embodiment of the present invention.
8 is a diagram illustrating a display device in which a horizontal line defect has occurred.
9 is a block diagram of a signal controller and an oscillator located outside the signal controller according to another embodiment of the present invention.
FIG. 10 is a block diagram illustrating the gate driver and the gate line of FIG. 1 according to another exemplary embodiment. FIG.
FIG. 11 is an enlarged circuit diagram of one stage and one gate line in FIG. 10.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to FIGS. 1A and 1B.

1A is a plan view of a display device according to an exemplary embodiment, and FIG. 1B is a block diagram of a signal controller according to the exemplary embodiment of FIG. 1A.

Referring to FIG. 1A, a display device according to an exemplary embodiment of the present invention includes a display panel 100, a data driver IC 460, and a signal controller 600 (also referred to as a T-con).

First, the display panel 100 includes a display area 300 for displaying an image and a gate driver 500 for applying a gate voltage to a gate line of the display area 300. The data line of the display area 300 receives a data voltage from the data driver IC 460 formed on the flexible printed circuit film FPC 450 attached to the display panel 100. The gate driver 500 and the data driver IC 460 are controlled by the signal controller 600. A printed circuit board (PCB) is formed on the outer side of the flexible printed circuit film 450 to transmit a signal from the signal controller 600 to the data driver IC 460 and the gate driver 500. In some embodiments, the signal controller 600 may be formed on the printed circuit board PCB.

The signal controller 600 includes an oscillator 610, and the signals provided by the signal controller include a panel characteristic information signal SCL, a power supply voltage AVDD, a gate clock signal CPV, a low voltage Vss2, and a scan. Start signal STVP, image data DAT, and the like.

First, the panel characteristic information signal SCL receives EDID (extended display identity data) of the display panel 100 through communication of I2C standard that transmits data through the SDA line and the SCL line. do. (See I2C transceiver 621 of FIG. 1B.)

The power supply voltage AVDD is an analog voltage generated when power is applied to the display device, and is a basic voltage that generates various voltages used in the display device.

The low voltage Vss2 is one of two low voltages Vss1 and Vss2 used in the gate driver 500. In the embodiment of the present invention, the low voltage Vss1 is generated based on the power supply voltage AVDD, and the low voltage Vss2 is the power source. Generated separately with voltage AVDD.

The gate clock signal CPV is a signal that is the basis of the first clock signal CKV and the second clock signal CKVB used in the gate driver 500, and has the same period as the first clock signal CKV. Voltage magnitudes may vary. The second clock signal CKVB is generated by inverting the first clock signal CKV.

The scan start signal STVP is a control signal for starting the gate driver 500 to operate.

On the other hand, the image data DAT is digital data transmitted to the data driver IC 460 after a predetermined process of the image data received from the outside.

The detailed structure of the signal controller 600 according to the embodiment of the present invention will be described below with reference to FIG. 1B.

The signal controller 600 includes an LVDS receiver (LVDS RX) 601, an image data compensator 602, a mini LVDS transmitter (mini-LVDS TX) 603, an oscillator 610, a timing generator 611, and an I2C transmission / reception. A portion I2C 621 and a ROM map 622 are included.

The LVDS receiver 601 receives an externally input image data RDAT and an external clock signal RCLK of an LVDS type, converts the image data into RGB data that can be processed by the signal controller 600, and outputs the converted RGB data.

The image data corrector 602 processes the image data to properly display the RGB data received by the LVDS receiver 601 on the display panel 100. An example of the processing of the image data is an ACC (Accurate Color Capture) process that processes data according to the gamma characteristics of the display panel 100 or an image of the current frame and an image of an existing frame in order to improve a response speed. There is a DCC (Dynamic Capacitance Compensation) process for correcting the data according to the difference of the data.

The mini LVDS transmitter 603 converts the RGB data corrected by the image data corrector 602 to the mini-LVDS method and outputs the data to the data driver IC 460.

In the above description, the image data between the outside and the signal controller 600 is transmitted and received by the LVDS method, and the signal controller 600 and the data driver IC 460 are transmitted and received by the mini-LVDS method. Can also send and receive.

On the other hand, the external clock signal RCLK received by the LVDS receiver 601 is converted and transferred to the timing generator 611 to be a basis for generating various control signals (STVP, TP, REV, DE, CPV, etc.).

As described above, the I2C transceiver 621 transmits and receives EDID (extended display identity data) of the display panel 100 through I2C standard communication that transmits data through the SDA line and the SCL line. .

The ROM map 622 connected to the I2C transceiver 621 stores control signal (STVP, TP) generated by storing the extended display identity data (EDID) of the display panel 100 or according to characteristics of the display panel 100. , REV, DE, CPV, etc.) for the detailed tuning of information is stored.

When the power supply VCC is applied to the display device, the oscillator 610 directly receives the power supply VCC to operate the oscillator 610 first. The signal generated as the oscillator 610 operates is transferred to the timing generator 611 to generate only the gate clock signal CPV first. The gate clock signal CPV generated by the timing generator 611 is transferred to the DC / DC IC 650 to convert a level to generate a first clock signal CKV and a second clock signal CKVB. The generated first clock signal CKV and second clock signal CKVB are transmitted to the gate driver 500. As a result, the gate driver 500 does not malfunction due to the clock signals CKV and CKVB applied in the initialization step from when the display device is turned on until the display device operates normally.

The oscillator 610 may generate the gate clock signal CPV by transferring the output to the timing generator 611 as described above only in the initialization step. Meanwhile, according to an exemplary embodiment, the display device may operate even when the display device operates normally. In this case, the grayscale signal required to display the screen may be generated when the external signal is an abnormal signal. .

The signal controller 600 generates the signal, voltage, and image data as described above, and controls the gate driver 500 and the data driver IC 460 to display an image.

In particular, when the power supply is turned on and the power voltage AVDD and the low voltage VSS2 are generated, the signal controller 600 operates the oscillator 610 before receiving the panel characteristic information signal SCL according to the I2C standard to operate the gate clock signal ( CPV) is generated to control the gate driver 500.

That is, the gate clock signal CPV, which is the basis of the first clock signal CKV and the second clock signal CKVB applied to the gate driver 500, is generally displayed after the panel characteristic information signal SCL is received. Since the panel 100 is generated during normal operation, it cannot be controlled even if the gate driver 500 malfunctions until the normal operation after the power is turned on. In particular, since the low voltage VSS2 is already transmitted to the gate driver 500, another voltage (for example, VSS1 low voltage) is also generated and applied according to the power supply voltage AVDD. May occur.

In order to eliminate this problem, in the exemplary embodiment of the present invention, when the display device is turned on, the power supply voltage AVDD and the low voltage VSS2 are generated, and the oscillator 610 of the signal controller 600 operates to operate the gate clock signal. Generates and outputs a CPV, and then receives a panel characteristic information signal SCL according to the I2C specification.

Through this procedure, display quality is improved by eliminating the period in which the gate driver 500 may malfunction. This will be described in detail later with reference to FIG. 5.

In the case of a liquid crystal display panel, the display area 300 includes a thin film transistor Trsw, a liquid crystal capacitor Clc, a storage capacitor Cst, and the like. In FIG. 1, the liquid crystal display panel is illustrated as an example. Meanwhile, the organic light emitting display panel includes a thin film transistor and an organic light emitting diode, and in other display panels, the display region 300 is formed by including elements such as thin film transistors. Hereinafter, a liquid crystal display panel will be described as an example.

The display area 300 includes a plurality of gate lines G1 -Gn and a plurality of data lines D1 -Dm, and the plurality of gate lines G1 -Gn and a plurality of data lines D1 -Dm are insulated from each other. Is crossed.

Each pixel PX includes a thin film transistor Trsw, a liquid crystal capacitor Clc, and a sustain capacitor Cst. The control terminal of the thin film transistor Trsw is connected to one gate line, the input terminal of the thin film transistor Trsw is connected to one data line, and the output terminal of the thin film transistor Trsw is one side of the liquid crystal capacitor Clc. It is connected to one terminal of the terminal and the holding capacitor (Cst). The other terminal of the liquid crystal capacitor Clc is connected to the common electrode, and the other terminal of the sustain capacitor Cst receives the sustain voltage Vcst applied from the signal controller 600.

The plurality of data lines D1 -Dm receive data voltages from the data driver IC 460, and the plurality of gate lines G1 -Gn receive gate voltages from the gate driver 500.

The data driver IC 460 is connected to the data lines D1 -Dm formed on the upper or lower side of the display panel 100 and extending in the vertical direction. In the embodiment of FIG. 1, the data driver IC 460 displays the data driver IC 460. An embodiment located above the panel 100 is illustrated.

The gate driver 500 receives the first low voltage Vss1 corresponding to the clock signals CKV and CKVB, the scan start signal STVP, and the gate off voltage, and a second low voltage Vss2 which is lower than the gate off voltage. The gate on voltage and the gate off voltage are generated to sequentially apply the gate on voltage to the gate lines G1 -Gn.

The clock signals CKV and CKVB are generated based on the gate clock signal CPV of the signal controller 600. In some embodiments, the clock signals CKV and CKVB are generated based on the gate clock signal CPV in the signal controller 600. Signals CKV and CKVB may be transmitted to the gate driver 500. The gate clock signal CPV and the first clock signal CKV have the same period, but different voltage magnitudes, and the second clock signal CKVB has an inverse relationship with the first clock signal CKV.

The first low voltage Vss1 according to the exemplary embodiment of the present invention is generated based on the power supply voltage AVDD, and the second low voltage Vss2 is generated as the display device is turned on together with the power supply voltage AVDD.

The clock signals CKV and CKVB, the scan start signal STVP, the first low voltage Vss1 and the second low voltage Vss2 applied to the gate driver 500 are outermost sides as shown in FIG. 1, and the gate driver The gate driver 500 is applied to the gate driver 500 through the flexible printed circuit film 450 positioned on the 500 side. Such a signal is transmitted from the external or signal controller 600 to the flexible printed circuit film 450 through the printed circuit board 400.

In the above, the overall structure of the display device has been described.

Hereinafter, the gate driver 500 and the gate lines G1 -Gn related to the present invention will be described.

FIG. 2 is a block diagram illustrating the gate driver and the gate line of FIG. 1 in detail.

In FIG. 2, the gate driver 500 is blocked and illustrated in detail.

In FIG. 2, the display area 300 is represented by a resistor Rp and a capacitor Cp. The gate line G1 -Gn, the liquid crystal capacitor Clc, and the storage capacitor Cst each have a resistance value and a capacitance, and the sum of all of them is represented by one resistor Rp and one capacitor Cp. The gate voltage output from the stage SR is transferred through the gate line. As shown in FIG. 2, the gate line may be represented as having a resistor Rp and a capacitance Cp. These values are values that one gate line generally has, and may have different values according to the structure and characteristics of the display area 300.

Hereinafter, the gate driver 500 will be described.

The gate driver 500 includes a plurality of stages SR1, SR2, SR3, SR4... Each stage SR1, SR2, SR3, SR4, ... outputs three input terminals IN1, IN2, IN3, one clock input terminal CK, two voltage input terminals Vin1 and Vin2, and a gate voltage. A gate voltage output terminal OUT and a transfer signal output terminal CRout.

First, the first input terminal IN1 is connected to the transfer signal output terminal CRout of the front stage and receives the transfer signal CR of the previous stage. The first stage has no previous stage stage, so the first input terminal IN1 does not exist. ) Receives a scan start signal STVP.

The second input terminal IN2 is connected to the transfer signal output terminal CRout of the next stage and receives the transfer signal CR of the next stage. In addition, the third input terminal IN3 is connected to the transfer signal output terminal CRout of the next stage and receives the transfer signal CR of the next stage.

The stage SRn (not shown) connected to the n-th gate line Gn may form two dummy stages to receive the transfer signal CR from the next stage and the next stage. The dummy stages SRn + 1 and SRn + 2 (not shown) are stages that generate and output a dummy gate voltage, unlike the other stages SR1-SRn. That is, while the gate voltages output from the other stages SR1 -SRn are transmitted through the gate lines, a data voltage is applied to the pixels to display an image, but the dummy stages SRn + 1 and SRn + 2 are connected to the gate lines. It may not be used, and may be connected to the gate line of a dummy pixel (not shown) that does not display an image even though it is connected to the gate line, and thus may not be used to display an image.

A clock signal is applied to the clock terminal CK, and a first clock CKV is applied to the clock terminal CK of the odd stage among the plurality of stages, and a second clock (CK) is applied to the clock terminal CK of the even stage. CKVB) is applied. The first clock CKV and the second clock CKVB are clock signals that are out of phase with each other.

The first low voltage Vss1 corresponding to the gate-off voltage is applied to the first voltage input terminal Vin1, and the second low voltage Vss2 lower than the first low voltage Vss1 is applied to the second voltage input terminal Vin2. do. The voltage values of the first low voltage Vss1 and the second low voltage Vss2 may vary depending on the embodiment. In this embodiment, -5V is used as the first low voltage Vss1 value, and the second low voltage Vss2 is used. Use -10V as the value.

The operation of the gate driver 500 will be described below.

First, the first stage SR1 receives the first clock signal CKV provided from the outside through the clock input terminal CK, and the scan start signal STVP through the first input terminal IN1. The second voltage input terminals Vin1 and Vin2 have the first and second low voltages Vss1 and Vss2, and the second stage SR2 and the third stage through the second and third input terminals IN2 and IN3. The transfer signals CR provided from SR3 are respectively input, and the gate-on voltage is output through the gate voltage output terminal OUT to the first gate line. In addition, the transfer signal output terminal CRout outputs the transfer signal CR and transfers it to the first input terminal IN1 of the second stage SR2.

The second stage SR2 receives the second clock signal CKVB provided from the outside through the clock input terminal CK and the transfer signal CR of the first stage SR1 through the first input terminal IN1. And the first and second low voltages Vss1 and Vss2 to the first and second voltage input terminals Vin1 and Vin2, and the third stage SR3 and the second and third input terminals IN2 and IN3. The transfer signal CR provided from each of the fourth stages SR4 is input to output a gate-on voltage to the second gate line through the gate voltage output terminal OUT. In addition, the transmission signal output terminal CRout outputs the transmission signal CR and transmits the transmission signal CR to the first input terminal IN1 of the third stage SR3 and the second input terminal IN2 of the first stage SR1. .

On the other hand, the third stage SR3 receives the first clock signal CKV provided from the outside through the clock input terminal CK and transmits the transfer signal of the second stage SR2 through the first input terminal IN1. (CR) to the first and second voltage input terminals Vin1 and Vin2, the first and second low voltages Vss1 and Vss2, and the fourth stage through the second and third input terminals IN2 and IN3. The transfer signal CR provided from each of the SR4 and the fifth stage SR5 is input to output a gate-on voltage to the third gate line through the gate voltage output terminal OUT. In addition, the transmission signal output terminal CRout outputs the transmission signal CR so that the first input terminal IN1 of the fourth stage SR4, the third input terminal IN3 and the second of the first stage SR1 are output. The signal is transferred to the second input terminal IN2 of the stage SR2.

In the same manner as described above, the n-th stage SRn receives the second clock signal CKVB provided from the outside through the clock input terminal CK, and n-1-1 through the first input terminal IN1. The transmission signal CR of the stage SR2 is connected to the first and second voltage input terminals Vin1 and Vin2, and the first and second low voltages Vss1 and Vss2, and the second and third input terminals IN2, IN3) receives the transfer signal CR provided from the n + 1th stage SRn + 1 (dummy stage) and the n + 2th stage SRn + 2 (dummy stage), respectively, and receives a gate voltage to the nth gate line. The gate-on voltage is output through the output terminal OUT. In addition, the transmission signal output terminal CRout outputs the transmission signal CR so that the first input terminal IN1 and the n-2 stage SRn-2 of the n + 1 stage SRn + 1 (dummy stage) are output. The third input terminal IN3 and the second input terminal IN2 of the n-1th stage SRn-1 of FIG.

Referring to FIG. 2, the stage (SR) connection structure of the entire gate driver 500 has been described. Hereinafter, the structure of the stage SR of the gate driver connected to one gate line will be described in more detail with reference to FIG. 3.

FIG. 3 is an enlarged circuit diagram of one stage SR connected to one gate line in FIG. 2.

Referring to FIG. 3, each stage SR of the gate driver 500 according to the present exemplary embodiment may include an input unit 511, a pull-up driver 512, a transfer signal generator 513, an output unit 514, and a pull-down driver. 515.

The input unit 511 includes one transistor (fourth transistor Tr4), and an input terminal and a control terminal of the fourth transistor Tr4 are commonly connected (diode connected) to the first input terminal IN1. The output terminal is connected to a Q contact (hereinafter also referred to as a first node). The input unit 511 serves to transfer the high voltage to the Q contact when the high voltage is applied to the first input terminal IN1.

The pull-up driver 512 includes two transistors (a seventh transistor Tr7 and a twelfth transistor Tr12). First, the control terminal and the input terminal of the twelfth transistor Tr12 are commonly connected to receive the first clock signal CKV or the second clock signal CKVB through the clock terminal CK, and the output terminal receives the seventh transistor ( It is connected to the control terminal and pull-down drive unit 515 of Tr7. Meanwhile, an input terminal of the seventh transistor Tr7 is also connected to the clock terminal CK, an output terminal is connected to a Q 'contact (hereinafter also referred to as a second node), and a pull-down driver 515 passing through the Q' contact. ) The control terminal of the seventh transistor Tr7 is connected to the output terminal of the twelfth transistor Tr12 and the pull-down driver 515. Here, parasitic capacitors (not shown) may be formed between the input terminal and the control terminal of the seventh transistor Tr7 and between the control terminal and the output terminal, respectively. In the pull-up driver 512, when a high signal is applied from the clock terminal CK, a high signal is transmitted to the control terminal and the pull-down driver of the seventh transistor Tr7 through the twelfth transistor Tr12. 515). The high signal transferred to the seventh transistor Tr7 turns on the seventh transistor Tr7, and as a result, the high signal applied from the clock terminal CK is applied to the Q ′ contact.

The transfer signal generator 513 includes one transistor (a fifteenth transistor Tr15). The clock terminal CK is connected to an input terminal of the fifteenth transistor Tr15 so that the first clock signal CKV or the second clock signal CKVB is input, and the control terminal is an output of the input unit 511, that is, Q. It is connected to the contact point, and the output terminal is connected to the transfer signal output terminal CRout for outputting the transfer signal CR. Here, a parasitic capacitor (not shown) may be formed between the control terminal and the output terminal. The output terminal of the fifteenth transistor Tr15 is connected to the transfer signal output terminal CRout and the pull-down driver 515 to receive the second low voltage Vss2. As a result, the voltage value when the transfer signal CR is low has a second low voltage Vss2 value.

The output unit 514 includes one transistor (first transistor Tr1) and one capacitor (first capacitor C1). The control terminal of the first transistor Tr1 is connected to the Q contact, the input terminal receives the first clock signal CKV or the second clock signal CKVB through the clock terminal CK, and the control terminal and the output terminal. The first capacitor C1 is formed therebetween, and the output terminal is connected to the gate voltage output terminal OUT. In addition, the output terminal is connected to the pull-down driver 515 to receive the first low voltage Vss1. As a result, the voltage value of the gate-off voltage has a first low voltage Vss1 value. The output unit 514 outputs a gate voltage according to the voltage at the Q contact and the first clock signal CKV.

The pull-down driver 515 removes the charge present on the stage SR so as to smoothly output the gate-off voltage and the low voltage of the transfer signal CR, and lowers the potential of the Q contact. It serves to lower the potential of the Q 'contact, to lower the voltage output to the transmission signal (CR) and to lower the voltage output to the gate line. The pull-down driver 515 includes ten transistors (second transistor Tr2, third transistor Tr3, fifth transistor Tr5, sixth transistor Tr6, eighth transistor Tr8 to eleventh transistor Tr11. ), A thirteenth transistor Tr13, and a sixteenth transistor Tr16.

First, we look at the transistor that pulls down the Q contact. The transistors that pull down the Q contact are the sixth transistor Tr6, the ninth transistor Tr9, the tenth transistor Tr10, and the sixteenth transistor Tr16.

The sixth transistor Tr6 is connected to the third input terminal IN3 and the control terminal, the output terminal is connected to the second voltage input terminal Vin2, and the input terminal is connected to the Q contact. Therefore, the sixth transistor Tr6 is turned on in accordance with the transfer signal CR applied in the next stage to lower the voltage at the Q contact point to the second low voltage Vss2.

The ninth transistor Tr9 and the sixteenth transistor Tr16 operate together to pull down the Q contact, and the control terminal of the ninth transistor Tr9 is connected to the second input terminal IN2, and the input terminal is connected to the Q contact. The output terminal is connected to an input terminal and a control terminal of the sixteenth transistor Tr16. The sixteenth transistor Tr16 has a control terminal and an input terminal connected to the output terminal of the ninth transistor Tr9 (diode connection), and the output terminal is connected to the second voltage input terminal Vin2. Therefore, the ninth transistor Tr9 and the sixteenth transistor Tr16 are turned on in response to the transfer signal CR applied in the next stage, thereby lowering the voltage at the Q contact point to the second low voltage Vss2.

The input terminal of the tenth transistor Tr10 is connected to the Q contact, the output terminal is connected to the second voltage input terminal Vin2, and the control terminal is referred to as an inverting terminal, having a phase opposite to that of the Q 'contact (Q contact). Is connected to the Therefore, in the general section in which the Q 'contact has a high voltage, the tenth transistor Tr10 continuously decreases the voltage of the Q contact to the second low voltage Vss2, but only when the Q' contact voltage is low. It does not lower the voltage. When the voltage at the Q contact does not decrease, the stage outputs the gate-on voltage and the transfer signal CR.

The transistor that pulls down the Q 'contact from the pull-down driver 515 will be described. The transistors that pull down the Q 'contacts are the fifth transistor Tr5, the eighth transistor Tr8, and the thirteenth transistor Tr13.

The control terminal of the fifth transistor Tr5 is connected to the first input terminal IN1, the input terminal is connected to the Q ′ contact, and the output terminal is connected to the second voltage input terminal Vin2. As a result, it serves to lower the voltage of the Q 'contact to the second low voltage (Vss2) according to the transfer signal CR of the front stage.

Meanwhile, the eighth transistor Tr8 has a control terminal connected to the transfer signal output terminal CRout of the main stage, an input terminal connected to the Q 'contact, and an output terminal connected to the second voltage input terminal Vin2. As a result, the voltage of the Q 'contact is reduced to the second low voltage Vss2 according to the transmission signal CR of the main stage.

The thirteenth transistor Tr13 is a control terminal connected to the transfer signal output terminal CRout of the main stage, an input terminal connected to the output terminal of the twelfth transistor Tr12 of the pull-up driving unit 512, and a second voltage input terminal Vin2. Has an output terminal connected to As a result, the potential inside the pull-up driver 512 is lowered to the second low voltage Vss2 according to the transmission signal CR of the main stage, and the voltage of the Q ′ contact connected to the pull-up driver 512 is also reduced to the second low voltage Vss2. It acts to lower. That is, while the thirteenth transistor Tr13 strictly discharges the internal charge of the pull-up driver 512 to the second low voltage Vss2 side, the pull-up driver 512 is also connected to the Q 'contact, so Q' Helping to lower the voltage of the Q 'contact to the second low voltage (Vss2) by preventing the voltage of the contact is pulled up.

Meanwhile, the transistor which serves to lower the voltage output from the pull-down driver 515 as the transfer signal CR will be described. The transistor that serves to lower the voltage output to the transfer signal CR is the eleventh transistor Tr11.

The eleventh transistor Tr11 has a control terminal connected to the Q 'contact, an input terminal connected to the transfer signal output terminal CRout, and an output terminal connected to the second voltage input terminal Vin2. As a result, when the voltage of the Q 'contact is high, the voltage of the transmission signal output terminal CRout is lowered to the second low voltage Vss2, and as a result, the transmission signal CR is changed to the low level.

On the other hand, the transistor that serves to lower the voltage output from the pull-down driver 515 to the gate line will be described. The transistors that lower the voltage output to the gate line are the second transistor Tr2 and the third transistor Tr3.

The second transistor Tr2 has a control terminal connected to the second input terminal IN2, an input terminal connected to the gate voltage output terminal OUT, and an output terminal connected to the first voltage input terminal Vin1. As a result, when the transfer signal CR of the next stage is output, the output gate voltage is changed to the first low voltage Vss1.

The third transistor Tr3 has a control terminal connected to the Q 'contact, an input terminal connected to the gate voltage output terminal OUT, and an output terminal connected to the first voltage input terminal Vin1. As a result, when the voltage of the Q 'contact is high, the output gate voltage is changed to the first low voltage Vss1.

In the pull-down driver 515, only the gate voltage output terminal OUT is lowered to the first low voltage Vss1, and the Q contact, Q ′ contact, and the transfer signal output terminal CRout are lower than the first low voltage Vss1. Lower to Vss2). As a result, although the gate on voltage and the voltage at the high of the transfer signal CR may have the same voltage, the gate off voltage and the voltage at the low of the transfer signal CR have different voltage values. . That is, the gate-off voltage has a first low voltage Vss1 value, and the low voltage value of the transfer signal CR has a second low voltage Vss2 value.

Although the gate voltage and the transfer signal CR may have various voltage values, in the present embodiment, the gate on voltage is 25V, the gate off voltage and the first low voltage Vss1 are -5V, and the high of the transfer signal CR is high. The high voltage has 25V, the low voltage and the second low voltage Vss2 have -10V.

In summary, one stage SR outputs a high voltage and a gate-on voltage of the transmission signal CR by operating the transfer signal generator 513 and the output unit 514 based on the voltage at the Q contact. In addition, the transfer signal CR is lowered from the high voltage to the second low voltage Vss2 by the transfer signal CR of the previous stage, the next stage, and the next stage, and the gate-on voltage is reduced to the first low voltage Vss1. It becomes low and becomes gate-off voltage. Here, one stage SR lowers the voltage at the Q contact point to the second low voltage Vss2 not only by the next stage but also by the next stage transfer signal CR, so as to be driven with low power consumption, and the second low voltage Vss2. ) Is lower than the first low voltage Vss1, which is a gate-off voltage, but the second low voltage Vss2 value is sufficiently low even if the transfer signal CR applied from another stage changes, including ripple or noise. The included transistors do not flow leakage current, which reduces power consumption.

Hereinafter, a driving method of a display device for preventing a malfunction of the gate driver 500 as shown in FIGS. 2 and 3 will be described with reference to FIGS. 4 and 5.

4 is a waveform diagram of a driving signal used in a display device according to an exemplary embodiment of the present invention, and FIG. 5 is a flowchart illustrating a method of driving the display device according to an exemplary embodiment of the present invention.

4 and 5 will be described below.

When the power supply VCC is applied to the display device S 10, the power supply voltage ADVV and the low voltage Vss2 are generated in the display device to generate a base voltage capable of generating other voltages required for the display device. In FIG. 4, when the power supply VCC is applied, the power supply voltage AVDD rises twice and reaches the final power supply voltage AVDD. In the low voltage Vss2, the power supply voltage AVDD rises a second time. It can be confirmed that the voltage falls to the low voltage in time.

Thereafter, the oscillator 610 included in the signal controller 600 of the display device starts operation (S 20) to generate a gate clock signal CPV and is output to the gate driver 500. (S 30) In FIG. 4, the generation of the gate clock signal CPV is illustrated. The clock signals CKV and CKVB used in the gate driver 500 are generated by the gate clock signal CPV to control the gate driver 500. Here, the gate clock signal CPV and the first clock signal CKV have the same period but different voltage magnitudes, and the second clock signal CKVB is inverted with the first clock signal CKV.

Thereafter, the signal controller 600 receives the panel characteristic information signal SCL from the display panel 100 according to the I2C standard, and grasps the characteristics of the display panel 100 (S 40) to display an image. do. In FIG. 4, it can be seen that the panel characteristic information signal SCL is generated and disappeared for a predetermined period, and after the display panel 100 and the signal controller 600 exchange data according to the I2C standard for a certain period, all data is stored. When transmitted to the signal controller 600, it indicates that data is not transmitted or received.

When the display device is ready for normal operation through this procedure, the signal controller 600 outputs all control signals and image data DAT to display an image. (S 50)

As a result, the gate driver 500 receives a voltage (Vss2 low voltage, etc.) without an appropriate control signal in an initialization step from when the display device power supply (VCC) is turned on until normal operation of the display device. The gate clock signal CPV is generated and output so that the gate clock signal CPV is generated so that the clock signals CKV and CKVB are generated so that the gate driver 500 is also controlled so that no horizontal line defect occurs.

Hereinafter, referring to FIGS. 6 and 7, a result of experimenting whether or not a horizontal line defect occurs according to a timing at which the power voltage AVDD is applied is described.

6 and 7 illustrate whether a display device is defective due to a change in an application timing of a driving signal according to an exemplary embodiment of the present invention.

6 and 7 determine whether a failure occurs in the gate driver 500 according to a timing at which the power supply voltage AVDD is applied in the display device.

First, referring to FIG. 6, in FIG. 6, the power supply voltage AVDD is applied as shown in FIG. 4. However, this illustrates only one of five cases (case 1). FIG. 5 is a diagram used to classify a case of applying the voltage AVDD into a total of five.

First, case 1 is a case where the power supply voltage AVDD is applied immediately after the power supply Vcc is applied. In this case, there is no other control voltage transmitted to the gate driver 500.

Case 2 is a case where the low voltage Vss2 is applied at a sufficiently low voltage and at the same time the power supply voltage AVDD is applied. In this case, there is no other control voltage transmitted to the gate driver 500.

Case 3 is a case in which the power supply voltage AVDD is applied while the display panel 100 and the signal controller 600 exchange the panel characteristic information signal SCL using I2C standard communication.

Case 4 is a case where the power supply voltage AVDD is applied when the gate clock signal CPV starts to be applied, and a control signal such as STH is also applied.

Case 5 is a case where the power supply voltage AVDD is applied in accordance with the time when the display panel is allowed to perform normal display operation through an initialization process.

Referring to FIG. 7, the five cases shown in FIG. 6 were identified based on a total of four embodiments.

First, the first embodiment 140AT20-L is an embodiment (denoted DECA) using the gate driver 500 of FIGS. 2 and 3, and was tested on a panel on which a high temperature reliability test (HTOL) was performed.

The second embodiment 140AT19-2 is an embodiment using the gate driver 500 of FIGS. 10 and 11 to be described later (indicated by MAM), and was tested on a panel on which a high temperature reliability test (HTOL) was performed.

The third embodiment 140AT22 is an embodiment that uses the gate driver 500 of FIGS. 2 and 3 to test a panel that has not been subjected to the high temperature reliability test (HTOL).

The fourth embodiment 156AR24 is an embodiment using the gate driver 500 of FIGS. 10 and 11, which will be described later, and was tested on a panel on which a high temperature reliability test (HTOL) was performed.

In FIG. 7, o is a case where a failure occurs, and x is a case where a failure does not occur.

First, in the third embodiment 140AT22, no failure occurred in any case. This is not because the third embodiment 140AT22 is a good display device, but the amorphous semiconductor constituting the channel of the transistor included in the gate driver 500 does not undergo a characteristic change without undergoing a high temperature reliability test (HTOL). The third embodiment (140AT22) also has a possibility of failure when used for a long time.

On the other hand, in the case of performing the high temperature reliability test (HTOL) it can be confirmed that only case 4 and case 5 did not cause a failure.

The reason why the case 4 and the case 5 did not occur is that the voltage applied to the gate driver 500 (generated based on the power supply voltage AVDD) and the clock signal (generated based on the gate clock signal CPV) together. This is because it is applied to prevent the gate driver 500 from malfunctioning.

Therefore, when the gate clock signal CPV is immediately generated by the oscillator 610 after the power supply voltage AVDD is applied as in the exemplary embodiment of the present invention, the gate driver 500 prevents the malfunction of the gate driver 500 and results in a horizontal line as shown in FIG. 8. Defect does not occur. In particular, as shown in FIG. 7, even when a characteristic of the amorphous semiconductor of the gate driver 500 is changed through a high temperature reliability test (HTOL), defects do not occur. .

9 illustrates a structure of a signal controller according to another embodiment different from FIG. 1B.

9 is a block diagram of a signal controller and an oscillator located outside the signal controller according to another embodiment of the present invention.

In FIG. 9 and FIG. 1B, the same contents are omitted below.

In the embodiment of FIG. 9, the oscillator 610 is external to the signal controller 600, unlike the embodiment of FIG. 1B. As a result, when the power supply VCC is applied to the display device, the oscillator 610 receives the power supply VCC directly and operates the oscillator 610 separately from the signal controller 600. As the oscillator 610 operates, a gate clock signal CPV is generated, and the generated gate clock signal CPV is transferred to the DC / DC IC 650 and the level is converted so that the first clock signal CKV and the first clock signal are generated. Two clock signals CKVB are generated. The generated first clock signal CKV and second clock signal CKVB are transmitted to the gate driver 500.

In the embodiment of FIG. 9, the oscillator 610 operates before the signal controller 600 operates normally. As a result, the gate driver 500 does not malfunction due to the clock signals CKV and CKVB applied in the initialization step from when the display device is turned on until the display device operates normally.

The oscillator 610 according to the embodiment of FIG. 9 may operate only in an initialization step.

Meanwhile, in the embodiment of FIG. 9, the timing generator 611 generates the control signals STVP, TP, REV, DE, CPV, and the like only according to the output signal of the LVDS receiver 601. different. That is, the external clock signal RCLK received by the LVDS receiver 601 is converted and transferred to the timing generator 611 to form a basis for generating various control signals (STVP, TP, REV, DE, CPV, etc.).

Hereinafter, the gate driver 500 according to another exemplary embodiment of the present invention will be described with reference to FIGS. 10 and 11.

FIG. 10 is a block diagram illustrating the gate driver and the gate line of FIG. 1 according to another embodiment, and FIG. 11 is an enlarged circuit diagram of one stage and one gate line in FIG. 10.

In FIG. 10, the gate driver 500 is shown in detail.

First, the gate driver 500 includes a plurality of stages SR1 -SRn + 1 connected dependently to each other. Each stage SR1-SRn + 1 has two input terminals IN1 and IN2, two clock input terminals CK1 and CK2, a voltage input terminal Vin receiving a low voltage Vss corresponding to the gate-off voltage, A reset terminal RE, an output terminal OUT, and a transfer signal output terminal CRout.

First, the first input terminal IN1 is connected to the transfer signal output terminal CRout of the previous stage stage and receives the transfer signal CR of the previous stage. The first stage has no first stage stage, so the first input terminal ( IN1) receives a scan start signal STVP.

The second input terminal IN2 is connected to the output terminal OUT of the next stage and receives a gate voltage of the next stage. Here, in the case of the last n + 1th stage SRn + 1 (dummy stage), the next stage does not exist, and thus the scan start signal STVP is applied to the second input terminal IN2.

The first clock CKV is applied to the first clock terminal CK1 of the odd stage of the plurality of stages, and the second clock CKVB having an inverted phase is applied to the second clock terminal CK2. On the other hand, the second clock CKVB is applied to the first clock terminal CK1 of the even-numbered stage, and the first clock CKV is applied to the second clock terminal CK2 to the same terminal when compared to the odd-numbered stage. The phase of the input clock is reversed.

A low voltage Vss corresponding to the gate-off voltage is applied to the voltage input terminal Vin, and is connected to the transfer signal output terminal CRout of the dummy stage SRn + 1 positioned at the end of the reset terminal RE.

The dummy stage SRn + 1 is a stage that generates and outputs a dummy gate voltage unlike other stages SR1 -SRn. That is, while the gate voltage output from the other stages SR1 -SRn is transferred through the gate line to apply a data voltage to the pixel to display an image, the dummy stage SRn + 1 may not be connected to the gate line. It is connected to the gate line of a dummy pixel (not shown) which does not display an image even though it is connected to the gate line, and thus is not used to display an image. (See Figure 10)

The operation of the gate driver 500 will be described below.

First, the first stage SR1 receives the first and second clock signals CKV and CKVB provided from the outside through the first clock input terminal CK1 and the second clock input terminal CK2. The scan start signal STVP is provided through IN1, the low voltage Vss corresponding to the gate-off voltage is provided to the voltage input terminal Vin, and the second stage SR2 is provided through the second input terminal IN2. The gate voltage is output through the output terminal OUT by receiving the gate voltage (voltage output from the OUT terminal), and the transfer signal CR is output from the transfer signal output terminal CRout. The signal is transferred to the first input terminal IN1 of the second stage SR2.

The second stage SR2 receives the second clock signal CKVB and the first clock signal CKV provided from the outside through the first and second clock input terminals CK1 and CK2, respectively, The transfer signal CR of the first stage SR1 is input through the input terminal IN1, the voltage Vss corresponding to the gate-off voltage is applied to the voltage input terminal Vin, and the second input terminal IN2. The gate voltage provided from the third stage SR3 is input to each other, and the gate voltage of the second gate line is output through the output terminal OUT, and the transfer signal output terminal CRout outputs the transfer signal CR to generate a third voltage. The signal is transferred to the first input terminal IN1 of the stage SR3.

In the same manner as described above, the n-th stage SRn receives the first and second clock signals CKV and CKVB provided from the outside through the first and second clock terminals CK1 and CK2, and the first input terminal. The transfer signal CR of the n-th stage SRn-1 through IN1, the low voltage Vss corresponding to the gate-off voltage is applied to the voltage input terminal Vin, and the second input terminal IN2. The gate voltages received from the n-th stage SRn-1 are respectively input through the gate voltages of the n-th gate line through the output terminal OUT, and the transfer signal CR is output from the transfer signal output terminal CRout. ) Is output to the first input terminal IN1 of the n + 1th dummy stage SRn + 1.

The structure of the entire gate driver 500 has been described with reference to FIG. 10. Hereinafter, the structure of the gate driver connected to one gate line will be described in more detail with reference to FIG. 11.

Referring to FIG. 11, each stage SR of the gate driver 500 according to the present exemplary embodiment includes an input unit 510 ′, a pull-up driver 511 ′, a transfer signal generator 512 ′, and an output unit 513 ′. ) And a pull-down driver 514 '.

The input unit 510 'includes one transistor (fourth transistor Tr4), and an input terminal and a control terminal of the fourth transistor Tr4 are commonly connected (diode connected) with the first input terminal IN1. The output terminal is connected to the Q contact. The input unit 510 ′ transfers a high voltage to the Q contact when a high voltage is applied to the first input terminal IN1.

The pull-up driver 511 'includes two transistors (a seventh transistor Tr7 and a twelfth transistor Tr12) and two capacitors (a second capacitor C2 and a third capacitor C3). . First, the control electrode and the input electrode of the twelfth transistor Tr12 are commonly connected to receive the first clock signal CKV or the second clock signal CKVB through the first clock terminal CK1, and the output electrode is connected to the pull electrode. Is connected to the -down drive unit 514 '. The input electrode of the seventh transistor Tr7 also receives the first clock signal CKV or the second clock signal CKVB through the first clock terminal CK1, and a control terminal and an output terminal are connected to the pull-down driver. And a seventh transistor Tr7 connected to 514 '. Here, the second capacitor C2 is connected between the input electrode and the control electrode of the seventh transistor Tr7, and the third capacitor C3 is connected between the control electrode and the output electrode of the seventh transistor Tr7. It is.

The transfer signal generator 512 ′ includes one transistor (a fifteenth transistor Tr15) and one capacitor (a fourth capacitor C4). The first clock signal CKV or the second clock signal CKVB is input to the input electrode of the fifteenth transistor Tr15 through the first clock terminal CK1, and a control electrode is output from the input unit 510. It is connected to the Q contact and the control electrode and the output electrode is connected to the fourth capacitor (C4). The transfer signal generator 512 outputs the transfer signal CR according to the voltage at the Q contact point and the first clock signal CKV.

The output unit 513 ′ includes one transistor (first transistor Tr1) and one capacitor (first capacitor C1). The control electrode of the first transistor Tr1 is connected to the Q contact point, the input electrode receives the first clock signal CKV or the second clock signal CKVB through the first clock terminal CK1, and The output electrode is connected to the first capacitor C1 and the output terminal is connected to the gate line. The output unit 513 'outputs a gate voltage according to the voltage at the Q contact and the first clock signal CKV.

The pull-down driver 514 'is a portion for removing a charge present on the stage SR so as to smoothly output the gate-off voltage, thereby lowering the potential of the Q contact and lowering the voltage output to the gate line. Play a role. The pull-down driver 514 'includes nine transistors (second transistor Tr2, third transistor Tr3, fifth transistor Tr5, sixth transistor Tr6, and eighth transistor Tr8 through eleventh. And a transistor Tr11 and a thirteenth transistor Tr13.

First, the fifth transistor Tr5, the tenth transistor Tr10, and the eleventh transistor Tr11 correspond to the first input terminal IN1 to which the transfer signal CR of the front stage SR is input and the gate off voltage. The low voltage Vss is connected in series between the voltage input terminals Vin to which the low voltage Vss is applied. The second clock signal CKVB or the first clock signal CKV is input to the control terminals of the fifth and eleventh transistors Tr5 and Tr11 and the tenth transistor Tr10 is inputted through the second clock terminal CK2. The control terminal receives the first clock signal CKV or the second clock signal CKVB through the first clock terminal CK1. In addition, a Q contact is connected between the eleventh transistor Tr11 and the tenth transistor Tr10, and the first transistor of the output unit 513 ′ is connected between the tenth transistor Tr10 and the fifth transistor Tr5. It is connected to the output terminal of Tr1), that is, the gate line.

The pair of transistors Tr6 and Tr9 are connected in parallel between the Q contact and the low voltage Vss. The control signal of the sixth transistor Tr6 receives the transfer signal CR of the dummy stage through the reset terminal RE, and the next stage of the control terminal of the ninth transistor Tr9 through the second input terminal IN2. The gate voltage of is input.

The pair of transistors Tr8 and Tr13 are connected between the outputs of the two transistors Tr7 and Tr12 of the pull-up driver 511 'and the low potential level Vss, respectively. The control terminals of the eighth and thirteenth transistors Tr8 and Tr13 are commonly connected to the output terminal of the first transistor Tr1 of the output unit 513 ', that is, the gate line.

Finally, the pair of transistors Tr2 and Tr3 are connected in parallel between the output of the output 513 'and the low potential level Vss. The control terminal of the third transistor Tr3 is connected to the output terminal of the seventh transistor Tr7 of the pull-up driver 511 ', and the control terminal of the second transistor Tr2 is connected to the control terminal of the third transistor Tr3 through the second input terminal IN2. The gate voltage of the next stage is input.

When the gate voltage of the next stage is input through the second input terminal IN2, the pull-down driving unit 514 ′ converts the voltage of the Q contact into a low voltage Vss through the ninth transistor Tr9 and the second transistor. It serves to change the voltage output to the gate line through (Tr2) to a low voltage (Vss). In addition, when the transfer signal CR of the dummy stage is applied through the reset terminal RE, the voltage of the Q contact is changed once more to the low voltage Vss through the sixth transistor Tr6. On the other hand, when a high voltage is applied to the second clock terminal CK2 to which a voltage having a phase opposite to that of the first clock terminal CK1 is applied, the voltage output to the gate line through the fifth transistor Tr5 is converted into a low voltage Vss. )

As also described with reference to FIG. 10, both stages of the first and second clock signals CKV and CKVB are input to each stage of the gate driver 500, and the first and second clock signals CKV and CKVB are provided for each stage. The inputs are alternately input to the first and second clock terminals CK1 and CK2.

The transistors Tr1-Tr13 and Tr15 formed in the stage SR may be NMOS transistors.

The gate voltage output from the stage SR is transferred through the gate line. As shown in FIG. 11, the gate line may be represented as having a resistor Rp and a capacitance Cp. These values are values that one gate line generally has, and may have different values according to the structure and characteristics of the display area 300.

In FIG. 11, a fourteenth transistor Tr14 formed on the opposite side of the gate line 121 is illustrated. The fourteenth transistor Tr14 is a transistor for discharging the gate-on voltage applied to the gate line 121, and one fourteenth transistor Tr14 is formed for one gate line.

The input terminal of the fourteenth transistor Tr14 is connected to one end of the gate line 121, the control terminal is connected to the next gate line 121, and the output terminal has a low voltage (Vss) corresponding to the gate off voltage. Is approved. That is, when the gate-on voltage is applied to the gate line of the next stage, the voltage applied to the gate line of the present stage is discharged to have a low voltage Vss voltage value. As a result, even after the gate-off voltage is applied, the charge remaining in the gate line is removed to prevent the thin film transistor Trsw in the pixel from malfunctioning.

The fourteenth transistor Tr14 may be formed or omitted depending on the embodiment. That is, the embodiment does not include the fourteenth transistor Tr14 in FIG. 10, and the embodiment includes the fourteenth transistor Tr14 in FIG. 11.

As described above, the gate driver 500 of FIGS. 10 and 11 is also applied with the gate clock signal CPV generated by the oscillator 610 of the signal controller 600 so that the gate driver 500 does not operate without an appropriate control signal. Do not.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

100: display panel 300: display area
400: printed circuit board 450: flexible printed circuit film
460: data driver IC 500: gate driver
600: signal controller 610: oscillator

Claims (19)

Turning on the display device;
Generating an gate clock signal by operating the oscillator upon receiving the power;
Determining, by the signal controller, characteristics of the display panel; And
And displaying an image on the display panel according to a control signal generated by the signal controller. In claim 1,
And the gate clock signal generated by the oscillator is used only in an initialization step from when the display device is turned on until the display device operates normally. In claim 2,
And the oscillator is located inside the signal controller. 4. The method of claim 3,
The signal controller further includes an LVDS receiver, an image data corrector, a mini LVDS transmitter, and a timing generator,
And the control signal generated by the signal controller is generated by the timing generator based on an external clock signal received through the LVDS receiver. 5. The method of claim 4,
The control signal comprises the gate clock signal,
In the initialization step, the timing generator generates the gate clock signal based on the output of the oscillator,
And the timing generator generates the gate clock signal based on an external clock signal received by the LVDS receiver when the display device is normalized. The method of claim 5,
Displaying an image on the display panel according to the control signal generated by the signal controller is
Generating a first clock signal and a second clock signal used in the gate driver of the display device based on the gate clock signal generated by the timing generator;
The first clock signal has the same period as the gate clock signal, but has a different voltage, and the second clock signal is generated by inverting the first clock signal. The method of claim 6,
The signal controller further includes an I2C transceiver and a ROM map.
And the I2C transceiver and ROM map are used by the signal controller to determine characteristics of a display panel. In claim 7,
Wherein the signal controller to determine the characteristics of the display panel
And the signal controller receives and receives extended display identity data (EDID) information of the display panel of the display device using I2C standard communication for transmitting data through an SDA line and an SCL line. In claim 2,
And the oscillator is located outside the signal controller. The method of claim 9,
The signal controller includes an LVDS receiver, an image data corrector, a mini LVDS transmitter, and a timing generator,
And the control signal generated by the signal controller is generated by the timing generator based on an external clock signal received through the LVDS receiver. 11. The method of claim 10,
The control signal comprises the gate clock signal,
The gate clock signal is generated directly by the oscillator in the initialization step,
And the timing generator generates the gate clock signal based on an external clock signal received by the LVDS receiver when the display device is normalized. 12. The method of claim 11,
Generating a first clock signal and a second clock signal used in the gate driver of the display device based on the gate clock signal generated by the oscillator or the timing generator;
The first clock signal has the same period as the gate clock signal, but has a different voltage, and the second clock signal is generated by inverting the first clock signal. The method of claim 12,
The signal controller further includes an I2C transceiver and a ROM map.
And the I2C transceiver and ROM map are used by the signal controller to determine characteristics of a display panel. In claim 13,
Wherein the signal controller to determine the characteristics of the display panel
And the signal controller receives and receives extended display identity data (EDID) information of the display panel of the display device using I2C standard communication for transmitting data through an SDA line and an SCL line. In claim 1,
The display device
A display area including a gate line, and
A gate driver connected to one end of the gate line and including a plurality of stages and integrated on a substrate;
The stage may receive a clock signal, a first low voltage, a second low voltage lower than the first low voltage, a transfer signal of at least one of the preceding stages, and a transfer signal of at least two of the following stages and receive a first low voltage to turn off the first low voltage. A method of driving a display device that outputs a gate voltage. 16. The method of claim 15,
And a voltage at the low level of the transfer signal is the second low voltage. 17. The method of claim 16,
The stage may include an input unit, a pull-up driver, a pull-down driver, an output unit, and a transmission signal generator. In claim 1,
The display device
A display area including a gate line, and
A gate driver connected to one end of the gate line and including a plurality of stages and integrated on a substrate;
The stage may be configured to output a gate voltage having a first low voltage as a gate-off voltage by receiving a clock signal, a low voltage, at least one transfer signal among the preceding stages, and at least two transfer signals among the next stages. . The method of claim 18,
The gate driver includes an input unit, a pull-up driver, a transfer signal generator, an output unit, and a pull-down driver.

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