KR102023641B1

KR102023641B1 - Shift register and method for driving the same

Info

Publication number: KR102023641B1
Application number: KR1020130009396A
Authority: KR
Inventors: 김태상
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-01-28
Filing date: 2013-01-28
Publication date: 2019-09-20
Also published as: KR20140096613A

Abstract

The shift register of the present invention includes a first switching TFT (thin film transistor) for turning on by a start signal applied to a gate electrode to supply a pulse signal of a high potential driving voltage to a first node; A pull-up TFT that is turned on by a pulse signal of a high potential driving voltage formed at the first node and outputs an output signal to an output terminal while a clock signal is applied; A second switching TFT turned on by an output signal boosted by the clock signal to supply the high potential driving voltage to the first node; A third switching TFT turned on by a reset signal supplied to a gate electrode to supply a low potential driving voltage to the first node; And a pull-down TFT which is turned on by the reset signal supplied to the gate electrode to supply the low potential driving voltage to the output terminal to lower the output signal.

Description

SHIFT REGISTER AND METHOD FOR DRIVING THE SAME}

The present invention relates to a shift register with improved driving reliability and a driving method thereof.

With the development of various portable electronic devices such as mobile communication terminals and notebook computers, there is an increasing demand for a flat panel display device that can be applied thereto. In response to this, liquid crystal display (LCD), plasma display (PDP), and organic light emitting display (OLED) have been commercialized.

The gate driving circuit of the display devices includes a shift register for sequentially supplying gate pulses to the plurality of gate lines. The shift register sequentially outputs a gate pulse through a plurality of stages including a plurality of transistors and capacitors.

Recently, a gate in panel (GIP) method has been applied to incorporate a thin film transistor (TFT) of the shift register into a substrate of a display panel.

The TFT constituting the shift register of the GIP method serves to supply a gate pulse to the TFT of each pixel formed in the display panel. Therefore, not only basic TFT characteristics such as mobility, leakage current, etc., but also durability and electrical reliability that can maintain a long lifespan are very important. The semiconductor layer of the TFT is formed of amorphous silicon or polycrystalline silicon. The amorphous silicon has advantages in that the film forming process is simple and the production cost is low, but electrical reliability is not secured.

In order to solve such a problem, researches using an oxide semiconductor as a semiconductor layer of a TFT have been recently conducted. Oxide semiconductors are evaluated as amorphous and stable materials, and by using oxide semiconductors as TFT semiconductor layers, TFTs can be manufactured at low temperatures using existing process equipment without additional process equipment. There are several advantages, including the elimination of the process.

FIG. 1 is a circuit diagram of a shifter register according to the prior art including an oxide TFT, and FIG. 2 is a diagram showing a drive waveform of the shift register shown in FIG. 1 shows a circuit of one stage among a plurality of stages constituting the shift register.

1 and 2, the shift register according to the related art includes an input start signal VST, a reset signal RST, a plurality of clock signals CLK and CLKB, an initialization signal Vinitial, and a driving power supply VDD. VSS is used to generate a scan signal having a high potential driving voltage VDD or a low potential driving voltage VSS level, and sequentially supplies scan signals generated in a plurality of stages to gate lines of the display panel. To this end, each stage of the shift register comprises a first TFT (T1) to an eighth TFT (T8) and a capacitor (C).

The first to sixth TFTs T1 to T6 are switching TFTs, which are turned on by the start signal VST, the reset signal RST, the boosting clock signal CLKB, or the initialization signal Vinitial to be Q nodes or QBs. The driving voltages VDD and VSS are supplied to the node.

The seventh TFT T7 is a full up TFT for outputting the high potential voltage VDD, and is turned on by a signal input to the Q node to output a scan signal having a high potential voltage to the output terminal OUT.

The eighth TFT T8 is a full down TFT for outputting the low potential voltage VSS, and is turned on by a signal input to the QB node to output a scan signal of the low potential voltage to the output terminal. That is, the scan signal of the high potential voltage is lowered to the low potential voltage level.

Here, the QB node, which is the gate node of the fourth TFT T4 and the eighth TFT T8, maintains a high voltage for most of the time in one frame period (90% or more).

FIG. 3 is a diagram illustrating positive bias degradation (PBTS) characteristics of an oxide TFT constituting a shift register of a GIP type according to the related art.

Referring to FIG. 3, the threshold voltage Vth is shifted in the positive direction due to the positive bias degradation PBTS of the fourth TFT T4 and the eighth TFT T8 connected to the QB node. There is a problem that affects the falling time operation due to the shift of the fourth TFT T4 and the eighth TFT T8 (pull down TFT).

Since the shift register according to the related art generates the output signals VGH and VGL by boosting the clock signal CLK, the output signal is affected by the clock signal CLK width. To increase the output time of the signal, it is necessary to increase the width of the clock signal (CLK width). However, if the width of the clock signal is increased, the high output signal (VGH) and the low output signal (VGL) overlap and the shift register does not operate normally. There is a problem.

In addition, when the fourth TFT (T4) and the eighth TFT (T8, pull-down TFT) is deteriorated, the noise of the signal applied to the Q node increases, so that a defect occurs in the multi output, and the voltage of the QB node is increased. The output characteristics of the sixth TFT T6 lowered to the low potential driving voltage VSS may be reduced to reduce driving reliability of the GIP shift register.

Bias (Bias Temperature Stress) characteristics of the oxide TFT are affected by the voltage level, time, and temperature of the gate bias. Vth) The shift phenomenon occurs clearly.

Therefore, when the shift register of the GIP method including the oxide TFT is applied, driving reliability of the shift register is degraded due to deterioration of the TFT according to the driving time, and distortion occurs in the output signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and it is a technical subject to improve the deterioration of TFT which comprises the GIP (gate in panel) shift register.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is a technical problem to improve driving reliability of a shift register of a GIP system and to prevent distortion of an output signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and the technical problem is to simplify the logic of the shift register to form a narrow bezel liquid crystal panel.

In addition to the technical task of the present invention mentioned above, other features and advantages of the present invention will be described below, or from such description and description will be clearly understood by those skilled in the art.

The present invention can improve deterioration of TFTs constituting a shift register of a GIP (gate in panel) method.

The present invention can improve the driving reliability of the shift register of the GIP system and can prevent distortion of the output signal.

The present invention can simplify the logic of the shift register of the GIP method, thereby forming a narrow bezel liquid crystal panel.

In addition, other features and advantages of the present invention may be newly understood through the embodiments of the present invention.

1 is a circuit diagram of a shifter resistor according to the prior art including an oxide TFT.
FIG. 2 is a diagram illustrating a driving waveform of the shift register illustrated in FIG. 1.
FIG. 3 is a diagram illustrating a positive bias degradation property of an oxide TFT constituting a shift register according to the prior art.
4 is a diagram schematically illustrating a display device to which a shift register is applied according to an exemplary embodiment of the present invention.
5 is a circuit diagram of a shift register according to an exemplary embodiment of the present invention.
6 is a diagram illustrating a driving waveform of a shift register according to an exemplary embodiment of the present invention.
7 is a diagram illustrating a method of driving a stage according to a driving waveform of a shift register according to an exemplary embodiment of the present invention.
8 is a diagram illustrating an output signal of a multi-stage shift register using four clock signals CLK.
9 is a diagram illustrating an effect of reducing TFT and signal lines of a shift register according to an exemplary embodiment of the present invention.

In the present specification, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same number as much as possible even though they are displayed on different drawings.

Hereinafter, a shift register and a driving method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

4 is a diagram schematically illustrating a display device to which a shift register is applied according to an exemplary embodiment of the present invention.

Referring to FIG. 4, in the liquid crystal display device to which the shift register 110 is applied according to an exemplary embodiment, the liquid crystal panel 100 displaying an image according to image data (data voltage) supplied by pixels arranged in a matrix form is provided. ; A backlight unit (not shown) for supplying light to the liquid crystal panel 100; It includes a driving circuit for driving a light source of the liquid crystal panel 100 and a backlight unit (not shown).

The liquid crystal panel 100 includes an opposing lower substrate (TFT array substrate) and an upper substrate (color filter array substrate), and a liquid crystal layer formed between the lower substrate and the upper substrate. The lower polarizing film is disposed on the rear surface of the lower substrate, and the upper polarizing film is disposed on the upper surface of the upper substrate.

The upper substrate of the liquid crystal panel 100 includes a color filter for converting light incident through the pixels of the lower substrate into color light to display a color image.

The lower substrate of the liquid crystal panel 100 includes M gate lines G1 to Gn and N data lines D1 to Dn. In addition, the shift register 110 is formed in a non-display area of the lower substrate by a GIP method.

Pixels are defined by crossing gate lines and data lines formed on a lower substrate, and each pixel includes a thin film transistor (TFT) and a storage capacitor Cst. In addition, the liquid crystal panel 100 may include a pixel electrode applying a data voltage to a pixel and a common electrode applying a common voltage Vcom.

The TFT of each pixel is switched by a scan signal supplied through the gate line, and when the TFT is turned on, a data voltage supplied through the data line is supplied to the pixel.

The arrangement state of the liquid crystal is changed in each pixel by the electric field difference between the data voltage and the common voltage, and the image is displayed by adjusting the transmittance of light incident from the backlight unit by adjusting the arrangement of the liquid crystal.

The driving circuit unit includes a main controller 200, a shift register 110 (gate driver), a backlight driver (not shown), and a power supply unit (not shown).

Here, the main controller 200 includes a timing controller (T-con) and a data driver as one chip, and includes a plurality of chips formed in the pad region of the liquid crystal panel 100 through a tape carrier package (TCP). It may be connected to the pad 300.

The main controller 200 converts the digital image data R, G, and B into analog image data (data voltage). Thereafter, an analog data voltage is supplied to each pixel through data lines of the liquid crystal panel 100.

The main controller 200 generates digital image data R, G, and B by arranging image signals from the outside in units of frames, and supplies the generated digital image data to a data driver.

In addition, the main controller 200 generates a gate control signal GCS for controlling the shift register 110 and a data control signal DCS for controlling the data driver using the input timing signal TS.

Here, the timing signal TS includes a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal CLK.

The gate control signal GCS may include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like.

The data control signal DCS includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE), a polarity control signal (POL), and the like. It may include.

Also, the main controller 200 uses the timing signal TS to start the start signal VST, the reset signal RST, and the clock signal CLK initialization signal Vinitial for driving the shift register 110 of the GIP method. Is generated and supplied to the shift register 110. In addition, the driving power supplies VDD and VSS are supplied to the shift register 110.

The shift register 110 generates a scan signal and supplies the scan signal to each of the plurality of gate lines, and includes a plurality of stages corresponding to the plurality of gate lines formed in the liquid crystal panel 100.

The shift register 110 generates a scan signal using the input start signal VST, the reset signal RST, and the clock signal CLK initialization signal Vinitial, and outputs the scan signal as an output signal to the liquid crystal panel 100. Are sequentially supplied to the gate lines. As the liquid crystal panel 100 is enlarged, the shift register 110 may be formed on the left and right sides of the non-display area (pad area) of the lower substrate.

5 is a circuit diagram of a shift register according to an exemplary embodiment of the present invention, and FIG. 6 is a diagram illustrating a driving waveform of the shift register according to an exemplary embodiment of the present invention.

5 and 6, each of the plurality of stages constituting the shift register 110 includes a switching block A and a buffer block B. Referring to FIG. The start signal VST, the reset signal RST, the clock signal CLK initialization signal Vinitial, and the driving power supplies VDD and VSS are supplied to the shift register 110 to generate a scan signal.

Here, the start signal VST is a pulse signal to start the rising of the output signal, and the reset signal RST is a pulse signal to start the falling of the output signal. That is, the output signal is started by the start signal VST, and the output signal is held until the reset signal RST is input.

The start signal VST and the reset signal RST are pulse signals that are turned off after maintaining the gate-on voltage level in two horizontal (2H) periods. The start signal VST starts outputting the output signal and resets the signal. The output of the output signal is terminated by RST. The start signal VST and the reset signal RST are signals for controlling the start and end of the output signal and do not overlap each other.

The clock signal CLK has a clock form in which the base voltage is repeated for a predetermined period after maintaining the gate-on voltage level in two horizontal (2H) periods, and is in phase with the start signal VST or in one horizontal (1H) period. This may have an overlapping phase. In FIG. 6, the clock signal CLK and the start signal VST overlap each other for one horizontal period 1H. However, the present invention is not limited thereto, and a clock signal whose phase is sequentially delayed by 1/2 clock or 2 clocks may be input to the stage ST.

The switching block A includes first to third switching TFTs 111, 112, and 113, a first capacitor Ca, and a second capacitor Cb. The buffer block B includes a pull-up TFT 114 and a pull-down TFT 115.

Such a plurality of switching TFTs 111, 112, 113 and the pull-up TFT 114 and the pull-down TFT 115 formed in the switching block A are N-type semiconductors formed of oxide. It may comprise a layer or a P-type semiconductor layer.

The switching block A raises the output signal using the input start signal VST, the reset signal RST, and the initialization signal Vinitial, and shifts the signal of the Q node (first node). The output signal is falling, i.e. the output signal is at a low potential voltage.

The buffer block B is shifted by the start signal VST, shifts the clock signal CLK of the high potential driving voltage VDD level according to the input signal, and outputs the output signal as a high potential driving voltage VDD level. ) Is reset to the low potential driving voltage VSS level according to the reset signal RST.

Here, the high potential driving voltage VDD may be supplied at + 20V to + 30V, and the low potential driving voltage VSS may be supplied at −10V to −20V.

7 is a diagram illustrating a method of driving a stage according to a driving waveform of a shift register according to an exemplary embodiment of the present invention.

Referring to FIG. 7 together with FIGS. 5 and 6, the first switching TFT 111 is turned on by the start signal VST supplied to the gate electrode. The source electrode of the first switching TFT 111 is connected to the first power line L1 to supply the high potential driving voltage VDD, and the drain electrode is connected to the Q node (first node) to supply the high potential driving voltage ( VDD) to the Q node (first node).

As shown in Fig. 7A, the first switching TFT 111 is turned on only when the start signal VST of the gate-on voltage level is supplied to supply the high potential driving voltage VDD to the Q node (first node). )

In addition, the first switching TFT 111 is turned on by the initialization signal Vinitial supplied to the gate electrode to supply the high potential driving voltage VDD to the Q node (first node) to supply the Q node (first node). Initialize The first switching TFT 111 is formed in a double gate structure to improve the driving failure caused by the negative shift of the initial threshold voltage Vth.

The gate electrode of the second switching TFT 112 is connected to the second node n2 connected to the output terminal OUT. The source electrode of the second switching TFT 112 is connected to the first power supply line L1 to supply the high potential driving voltage VDD, and the drain electrode is connected to the Q node (first node) to supply the high potential driving voltage ( VDD is supplied to the Q node (the first node).

Here, when the voltage of the Q node (first node) drops below the high potential driving voltage VDD at the 2VDD level after the clock signal CLK is terminated, the second switching TFT 112 has the clock signal CLK. It is turned on by the output signal boosted by to keep the Q node (first node) constant at the high potential drive voltage VDD. The second switching TFT 112 is turned on to charge the high potential driving voltage VDD to the first capacitor Ca formed between the Q node (first node) and the second node n2.

The third switching TFT 113 is turned on by the reset signal RST supplied to the gate electrode. The source electrode of the third switching TFT 113 is connected to the second power supply line L2 to supply the low potential driving voltage VSS, and the drain electrode is connected to the Q node (first node) to connect the low potential driving voltage ( VSS) is supplied to the Q node (first node).

As shown in FIG. 7B, the third switching TFT 113 is turned on only when the reset signal RST of the gate-on voltage level is supplied to supply the low potential driving voltage VSS to the Q node (first node). )

The first terminal of the first capacitor Ca is connected to the Q node (first node), and the second terminal is connected to the second node n2 connected to the output terminal OUT. The first first capacitor Ca maintains the Q node (first node) at a high potential driving voltage VDD so that the noise of the output signal is output to the output terminal OUT boosted by the clock signal CLK. ).

The first terminal of the second capacitor Cb is connected to the Q node (first node), and the second terminal is connected to the third node n3 to which the reset signal RST is supplied. The second capacitor Cb maintains the Q node (first node) and the third node n3 at a constant voltage to remove noise of the reset signal RST.

The gate electrode of the pull-up TFT 114 is connected to a Q node (first node), and is turned on by a pulse signal of a high potential driving voltage (VDD) level applied to the Q node (first node). The clock electrode CLK of the high potential driving voltage VDD level is supplied to the source electrode of the pull-up TFT 114. The drain electrode of the pull-up TFT 114 is connected to the output terminal OUT to output the output signal of the high potential driving voltage VDD to the output terminal OUT.

As shown in Fig. 7A, the pull-up TFT 114 is turned on by the clock signal of the high potential drive voltage VDD applied to the Q node (first node) by the start signal VST. The pull-up TFT 114 outputs an output signal to the output terminal OUT while the clock signal CLK is applied, and is turned off in synchronization with the reset signal RST signal. That is, the pull-up TFT 114 raises the output signal using the clock signal CLK of the high potential driving voltage VDD level and outputs the output signal to the output terminal OUT.

Here, the Q node (first node) is set to the high potential driving voltage VDD by the start signal VST, and the pull-up TFT 114 is turned on, and the output terminal is boosted to the level of 2VDD by the clock signal CLK. (Bootstrap)

6 and 7 (B), when the clock signal CLK ends, the pull-up TFT 114 is turned off so that the voltage at the output terminal drops from the 2VDD level to the VDD level. After that, the VDD level is maintained for a predetermined time (for example, 2.0us to 2.5us) before the reset signal (RST) is applied to the third switching TFT 113 and the pull-down TFT 115.

The gate electrode of the pull-down TFT 115 is connected to the third node n3. The source electrode of the pull-down TFT 115 is connected to the second power supply line L2 to supply the low potential driving voltage VSS. The drain electrode of the pull-down TFT 115 is connected to the output terminal OUT.

As shown in FIG. 7B, the pull-down TFT 115 is turned on by the reset signal RST of the high potential driving voltage VDD applied to the third node n3 to lower the output signal of the output terminal. It falls to the driving voltage VSS.

In the shift register according to an exemplary embodiment of the present invention, when the first switching TFT 111 is turned on, the high potential driving voltage VDD is supplied to the Q node (first node), and the third switching TFT 113 is turned on. At this time, the low potential driving voltage VSS is supplied to the Q node (first node). Through this, it is possible to prevent the pull-up TFT 114 connected to the Q node (first node) from being deteriorated positively or negatively.

8 is a diagram illustrating an output signal of a multi-stage shift register using four clock signals CLK.

As illustrated in FIG. 8, an output signal of a multi-stage shift register may be generated using four clock signals CLK having one horizontal (1H) period overlapped among two horizontal (2H) periods. That is, the four clock signals CLK are sequentially applied to m stages, so that output signals are sequentially generated in m stages. In FIG. 7, timings of the output signals for the N-1 th stage, the N th stage, the N + 1 th stage, and the N + 2 th stage among the m stages are shown.

Output lines of each of the m stages ST1 to STm constituting the shift register are connected to m gate lines GL1 to GLm formed on the liquid crystal panel, respectively.

Each of the m stages ST1 to STm is driven by the start pulse signal SVST, and the gate-on voltage level is sequentially shifted by one horizontal (1H) period according to the clock signals CLK1 to CLK4. Outputs an output signal (out). Accordingly, a scan pulse of the gate-on voltage level VDD is supplied to each of the gate lines GL1 through GLm for a predetermined horizontal period, and the low potential driving voltage VSS of the gate-off voltage level is applied after the predetermined horizontal period. Can be supplied.

The shift register according to an embodiment of the present invention eliminates the QB node that is essentially present in the shift register of the prior art, thereby improving the positive bias degradation (PBTS) phenomenon of the QB node and increasing the driving reliability of the shift register of the GIP method. have.

9 is a diagram illustrating an effect of reducing TFT and signal lines of a shift register according to an exemplary embodiment of the present invention.

Referring to FIG. 9, when comparing the logic of the shift register according to the exemplary embodiment of the present invention and the shift register according to the related art, the number of switching TFTs for increasing and decreasing the output signal may be reduced by three stages. have.

In the shift register according to the prior art, seven input signal lines are formed, whereas in the present invention, a signal line for supplying the clock signal CLKB to the QB node formed in the prior art is provided. Six input signal lines are formed.

This reduces the logic area of the GIP to form shift registers by 20% by reducing the number of TFTs and signal lines, and enables narrow bezel designs to increase product competitiveness. .

Those skilled in the art to which the present invention pertains will understand that the above-described present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: liquid crystal panel 110: shift register
111: first switching TFT 112: second switching TFT
113: third switching TFT 114: pull-up TFT
115: pull-down TFT Ca: first capacitor
Cb: second capacitor ST: stage
200: main controller 300: pad

Claims

A first switching thin film transistor (TFT) for turning on by a start signal applied to the gate electrode to supply a pulse signal of a high potential driving voltage to the first node;
A pull-up TFT that is turned on by a pulse signal of a high potential driving voltage formed at the first node and outputs an output signal to an output terminal while a clock signal is applied;
A second switching TFT turned on by an output signal boosted by the clock signal to supply the high potential driving voltage to the first node;
A third switching TFT turned on by a reset signal supplied to a gate electrode to supply a low potential driving voltage to the first node; And
And a plurality of stages including a pull-down TFT which is turned on by the reset signal supplied to a gate electrode and supplies the low potential driving voltage to the output terminal to lower the output signal.

According to claim 1,
A first capacitor connected to the first node, a first terminal connected to the first node, and a second node connected to the output terminal; and maintaining a first voltage at a constant voltage to remove noise of the output signal. Shift register.

According to claim 1,
A second capacitor having a first terminal connected to the first node and a second terminal connected to a third node supplied with the reset signal, and maintaining the third node at a constant voltage to remove noise of the reset signal; The shift register further includes.

According to claim 1,
And the pull-up TFT raises the output signal to output to the output terminal by using a clock signal of a high potential driving voltage level.

According to claim 1,
And the second switching TFT is turned on when the voltage of the first node drops below the high potential driving voltage after the clock signal is finished, thereby maintaining the first node at the high potential driving voltage.

According to claim 1,
The start signal is supplied to a gate electrode of the first switching TFT, a source electrode is connected to a first power line to which the high potential driving voltage is supplied, a drain electrode is connected to the first node,
A gate electrode of the second switching TFT is connected to the output terminal, a source electrode is connected to the first power line, a drain electrode is connected to the first node,
The reset signal is supplied to a gate electrode of the third switching TFT, a source electrode is connected to a second power supply line supplied with the low potential driving voltage, and a drain electrode is connected to the first node.
A gate electrode of the pull-up TFT is connected to the first node, a source electrode is connected to a signal line to which the clock signal is applied, a drain electrode is connected to the output terminal,
A shift register connected to a third node to which the reset signal is applied, a gate electrode of the pull-down TFT, a source electrode to a second power supply line to which the low potential driving voltage is supplied, and a drain electrode to the output terminal; .

According to claim 1,
And the first switching TFT is formed in a double gate structure, and is turned on by an initialization signal supplied to a gate electrode to supply the high potential driving voltage to the first node.

According to claim 1,
And a high potential driving voltage is formed at the first node by the start signal (VST) so that the pull-up TFT is turned on, and the pull-up TFT is turned on to bootstrap the output terminal through a clock signal.

In the driving method of any one of claims 1 to 8,
The pull-up TFT is turned on by the clock signal to form twice the high potential driving voltage at the output terminal.
When the clock signal is terminated, the pull-up TFT is turned off so that the voltage at the output terminal drops from the double high potential driving voltage to a high potential driving voltage.
The voltage of the output terminal is maintained at the high potential driving voltage for a predetermined time until a reset signal is applied to the pull-down TFT,
And the voltage at the output terminal drops to the low potential driving voltage by the reset signal.

The method of claim 9,
4. A method of driving a shift register, wherein four clock signals having one horizontal period overlapping one of two horizontal periods are sequentially applied to a plurality of stages to output an output signal which is sequentially shifted by one horizontal period.