KR20130032454A - Level shifting device - Google Patents

Level shifting device Download PDF

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Publication number
KR20130032454A
KR20130032454A KR1020110096037A KR20110096037A KR20130032454A KR 20130032454 A KR20130032454 A KR 20130032454A KR 1020110096037 A KR1020110096037 A KR 1020110096037A KR 20110096037 A KR20110096037 A KR 20110096037A KR 20130032454 A KR20130032454 A KR 20130032454A
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KR
South Korea
Prior art keywords
voltage
level
power supply
signal
level shifting
Prior art date
Application number
KR1020110096037A
Other languages
Korean (ko)
Inventor
김종환
Original Assignee
에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110096037A priority Critical patent/KR20130032454A/en
Publication of KR20130032454A publication Critical patent/KR20130032454A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE: Level shifting apparatus is provided to prevent competition between transistors and to level-shift input signals. CONSTITUTION: Level shifting apparatus includes a substrate voltage generation part(11), a compensation voltage generation part(12), a voltage selection part(13), and a level shifting circuit(14). The substrate voltage generation part generates a substrate voltage. The compensation voltage generation part generates a compensation voltage with a level higher than that of the substrate voltage. The voltage selection part selects one of the substrate voltage and the compensation voltage as a pull-down voltage according to the voltage level of a power supply. The level shifting circuit level-shifts input signals according to the pull-down voltage and outputs the same as output signals. [Reference numerals] (11) Substrate voltage generation part; (12) Compensation voltage generation part; (13) Voltage selection part; (14) Level system circuit;

Description

LEVEL SHIFTING DEVICE}

The present invention relates to a level shifting device, and more particularly, to a level shifting device for level shifting an input signal normally.

A semiconductor device is a device that realizes the human memory and recording capability by electronic means, and is used as a storage medium in computers, mobile phones, broadcasting devices, education and entertainment devices, and the like. The semiconductor device was introduced to the market in 1971, when the memory capacity was 1Kbit. Since then, the memory capacity of semiconductor devices has been phenomenal, such as increasing by four times in two to three years.

The semiconductor device receives a power supply voltage VDD and a ground voltage VSS from an external source, generates an internal voltage of a required level, and operates the same. The internal voltage includes the high voltage VPP that is higher than the power supply voltage VDD, the core voltage VCORE which is a level between the power supply voltage VDD and the ground voltage VSS, and the board voltage VBB that is lower than the ground voltage VSS. ). The high voltage VPP is used to drive a word line with a large loading, the core voltage VCORE is used to sense and amplify data, and the substrate voltage VBB is applied to the substrate so that the transistor It is used to control the threshold voltage Vt.

Meanwhile, the semiconductor device includes a level shifting device for shifting a level to an input signal. For example, the level shifting device outputs an input signal that toggles between the core voltage VCORE and the ground voltage VSS as an output signal that toggles between the power supply voltage VDD and the substrate voltage VBB. To this end, the level shifting device includes a plurality of transistors. However, in the level shifting device, when the level of the input signal is shifted at a low power supply voltage VDD due to the characteristics of the circuit, an unwanted current path occurs due to the fighting of the transistors. There is a problem with the output.

The present invention provides a level shifting device for level shifting an input signal correctly even when the level of the power supply voltage is lowered.

The present invention provides a substrate voltage generator for generating a substrate voltage, a compensation voltage generator for generating a compensation voltage higher than the substrate voltage, and pulls down one of the substrate voltage and the compensation voltage according to a level of a power supply voltage. And a level shifting circuit configured to level shift the input signal according to the pull-down voltage and output the output signal as an output signal.

The present invention selectively raises the level of the substrate voltage in order to solve the problem that the level of the power supply voltage is lowered and the fighting of the transistors in the level shifting device occurs. This prevents the fighting of the transistors in the level shifting device, so that the level shifting device correctly level shifts the input signal.

1 is a circuit diagram showing a level shifting device.
2 is a block diagram showing a level shifting apparatus according to an embodiment of the present invention.
3 is a circuit diagram illustrating the level shifting device of FIG. 2 in more detail.
4 is a timing diagram illustrating an operation of the level shifting apparatus of FIG. 3.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

1 is a circuit diagram showing a level shifting device.

As shown in FIG. 1, the level shifting device includes a signal inversion unit 1, a level shifting unit 2, and a signal output unit 3.

The signal inversion unit 1 inverts the input signal IN and outputs the inverted input signal INB. To this end, the signal inverting unit 1 includes a first inverter INV1 that uses the power supply voltage VDD as a pull-up voltage and uses the ground voltage VSS as the pull-down voltage. Here, the input signal IN is a signal that toggles to the level of the power supply voltage VDD and the ground voltage VSS.

The level shifting unit 2 shifts the level of the input signal IN and outputs the pre-output signal POUT. To this end, the level shifting unit 2 receives the input signal IN as a gate and receives the first PMOS transistor P1 and the inverting input signal INB disposed between the power supply voltage VDD terminal and the first node nd1. Is inputted to the gate and the output of the second PMOS transistor P2 and the second node nd2 disposed between the power supply voltage VDD terminal and the second node nd2 is inputted to the gate, and the first node nd1 and the substrate are inputted to the gate. The first NMOS transistor N1 disposed between the voltage VBB terminal and the output of the first node nd1 are input to the gate, and the second NMOS disposed between the second node nd2 and the substrate voltage VBB terminal. The transistor N2 is included.

The signal output unit 3 buffers the pre-output signal POUT and outputs it as an output signal OUT. To this end, the signal output unit 3 uses the power supply voltage VDD as the pull-up voltage, the second inverter INV2 using the substrate voltage VBB as the pull-down voltage, and the power supply voltage VDD as the pull-up voltage. And a third inverter INV3 using the substrate voltage VBB as the pull-down voltage. Here, the output signal is a signal that toggles to the level of the power supply voltage VDD and the substrate voltage VBB.

Looking at the operation of the level shifting device of such a configuration as follows.

First, when the input signal IN is input at the level of the ground voltage VSS, the level shifting unit 2 pulls up the first node nd1 to the power supply voltage VDD level, and accordingly, the second NMOS transistor. N2 is driven to generate the pre-output signal POUT at the substrate voltage VBB level.

Subsequently, the signal output unit 3 buffers the pre-output signal POUT and outputs the output signal POUT at the substrate voltage VBB level.

In another case, when the input signal IN is input at the level of the power supply voltage VDD, the signal inversion unit 1 generates the inverted input signal IN of the ground voltage VSS.

Subsequently, the level shifting unit 2 generates a pre-output signal POUT at the power supply voltage VDD level by driving the second node nd2 to the power supply voltage VDD level. Thereafter, the signal output unit 3 buffers the pre-output signal POUT and outputs the output signal POUT at the power supply voltage VDD level.

However, when the input signal IN transitions from the level of the ground voltage VSS to the level of the power supply voltage VDD while the level of the power supply voltage VDD is lowered, the second PMOS transistor in the level shifting unit 2 A current path between P2) and the second NMOS transistor N2 occurs, so that the correct output signal OUT is not generated. That is, when the input signal IN is at the level of the ground voltage VSS in the state where the level of the power supply voltage VDD is lowered, the pre-output signal POUT has the level of the substrate voltage VBB. At this time, when the input signal IN transitions to the level of the power supply voltage VDD, the driving capability of the second PMOS transistor P2 is lowered due to the level of the low power supply voltage VDD, thus fighting with the second NMOS transistor N2. fall behind in ftingting.

Accordingly, the level shifting unit 2 does not generate the pre-output signal POUT at the power supply voltage VDD level.

2 is a block diagram showing a level shifting apparatus according to an embodiment of the present invention.

As shown in FIG. 2, the level shifting apparatus includes a substrate voltage generator 11, a compensation voltage generator 12, a voltage selector 13, and a level shifting circuit 14.

The substrate voltage generation unit 11 generates the substrate voltage VBB by reducing the ground voltage VSS. To this end, the substrate voltage generation unit 11 includes a pressure reduction circuit.

The compensation voltage generator 12 reduces the ground voltage VSS to generate the compensation voltage VCV. In this case, the compensation voltage VCV is higher than the level of the substrate voltage VBB and lower than the level of the ground voltage VSS.

The voltage selector 13 detects the level of the power supply voltage VDD, selects one of the substrate voltage VBB and the compensation voltage VCV as the pull-down voltage VPD, and then selects a level shifting circuit. 14 to pass. More specifically, the voltage selector 13 transfers the compensation voltage VCV to the level shifting circuit 14 when the level of the power supply voltage VDD is low, and the level of the power supply voltage VDD is normal. In one case, the substrate voltage VBB is transferred to the level shifting circuit 14.

The level shifting circuit 14 outputs the output signal OUT by level shifting the input signal IN according to the pull-down voltage VPD.

3 is a circuit diagram illustrating the level shifting device of FIG. 2 in more detail.

As shown in FIG. 3, in the level shifting device, the voltage selector 13 detects the level of the power supply voltage VDD and outputs it as a detection signal DET. A first inverter INV11 that inverts DET and outputs the inverted detection signal DETB, and a first selector 132 that selects the compensation voltage VCV as a pull-down voltage VPD in response to the detection signal DET. The second selector 133 selects the substrate voltage VBB as the pull-down voltage VPD in response to the inversion detection signal DETB.

The level shifting circuit 14 includes a signal inversion unit 141, a level shifting unit 142, and a signal output unit 143.

The signal inverting unit 141 inverts the input signal IN and outputs the inverted input signal INB. To this end, the signal inverting unit 141 includes a second inverter INV12 that uses the power supply voltage VDD as the pull-up voltage and uses the ground voltage VSS as the pull-down voltage. Here, the input signal IN is a signal that toggles to the level of the power supply voltage VDD and the ground voltage VSS.

The level shifting unit 142 shifts the level of the input signal IN and outputs the pre-output signal POUT. To this end, the level shifting unit 142 receives the input signal IN as a gate, and includes a first PMOS transistor P11 and an inverting input signal INB disposed between the power supply voltage VDD terminal and the first node nd11. Is inputted to the gate and the output of the second PMOS transistor P12 and the second node nd12 disposed between the power supply voltage VDD terminal and the second node nd12 is inputted to the gate and pulled down with the first node nd11. The first NMOS transistor N11 disposed between the voltage VPD terminal and the output of the first node nd11 are input to the gate, and the second NMOS disposed between the second node nd12 and the pull-down voltage VPD terminal. The transistor N2 is included.

The signal output unit 143 buffers the pre-output signal POUT and outputs it as an output signal OUT. To this end, the signal output unit 143 uses the power supply voltage VDD as the pull-up voltage, the third inverter INV13 using the pull-down voltage VPD as the pull-down voltage, and the power voltage VDD as the pull-up voltage. And a fourth inverter INV14 using the pulldown voltage VPD as the pulldown voltage. Here, the output signal is a signal that toggles to the level of the power supply voltage VDD and the pull-down voltage VPD.

4 is a timing diagram illustrating an operation of the level shifting apparatus of FIG. 3.

As shown in FIG. 4, when the power supply voltage VDD is at a normal level, the detection signal DET is at a low level. Accordingly, the substrate voltage VBB is selected as the pull-down voltage VPD. Accordingly, the level shifting circuit 14 level-shifts the input signal IN having the ground voltage VSS level based on the substrate voltage VBB and outputs the output signal OUT having the substrate voltage VBB level. .

On the other hand, when the level of the power supply voltage VDD falls at the time T1, the detection signal DET becomes high level, and thus the compensation voltage VBV is selected as the pull-down voltage VPD. Accordingly, the level shifting circuit 14 outputs the output signal OUT having the compensation voltage VCV level by shifting the input signal IN having the ground voltage VSS level based on the compensation voltage VCV. .

In this state, when the input signal IN transitions to the power supply voltage VDD level at the time T2, the second node nd12 is pulled up to the power supply voltage VDD level, and as a result, the power supply voltage VDD level is increased. The output signal OUT is output. Referring to the operation of the level shifting circuit 14 in more detail, when the input signal IN of the power supply voltage VDD level is inverted and transferred to the second PMOS transistor P12, the second node nd12 supplies power. It is pulled up to the voltage VDD level. At this time, when the compensation voltage VCV is transferred to the second NMOS transistor N12 as the pull-down voltage VPD in the previous operation, the Vgs of the second NMOS transistor N12 is lowered to decrease the driving capability. Accordingly, the second PMOS transistor P12 becomes dominant in the fighting between the second PMOS transistor P12 and the second NMOS transistor N12, and accordingly, the second node nd12 pulls up to the power supply voltage VDD level. do. As a result, the level shifting circuit 14 outputs the pre-output signal POUT at the power supply voltage VDD level, and the signal output unit 143 buffers the output signal OUT at the power supply voltage VDD level. Will output

The level shifting device according to the embodiment of the present invention as described above selectively raises the level of the substrate voltage in order to solve the problem that the leveling of the power supply voltage is lowered and the fighting of the transistors occurs. This prevents the fighting of the transistors in the level shifting device, so that the level shifting device correctly level shifts the input signal.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. Will be apparent to those of ordinary skill in the art. For example, the logic gate and the transistor illustrated in the above embodiment may be implemented in different positions and types depending on the polarity of the input signal.

11: substrate voltage generator 12: compensation voltage generator
13: voltage selector 14: level shifting circuit

Claims (5)

A substrate voltage generator configured to generate a substrate voltage;
A compensation voltage generator configured to generate a compensation voltage having a level higher than that of the substrate voltage;
A voltage selector configured to select one of the substrate voltage and the compensation voltage as a pull-down voltage according to a power supply voltage level; And
A level shifting circuit for level shifting an input signal according to the pull-down voltage and outputting it as an output signal
Level shifting device comprising a.
The method of claim 1,
And the compensation voltage and the substrate voltage are lower than the ground voltage.
The method of claim 1,
The voltage selector selects the substrate voltage as the pull-down voltage when the level of the power supply voltage is normal, and selects the compensation voltage as the pull-down voltage when the level of the power supply voltage is lower than normal. Shifting device.
The method of claim 1,
The voltage selector
A power supply voltage level detection unit for detecting the level of the power supply voltage and outputting the detected signal as a detection signal;
A first inverter for inverting the detection signal and outputting the inverted detection signal;
A first selector configured to select the compensation voltage as the pull-down voltage in response to the detection signal; And
And a second selector configured to select the substrate voltage as the pull-down voltage in response to the inversion detection signal.
The method of claim 1,
The level shifting circuit
A signal inversion unit inverting the input signal and outputting the inverted input signal;
A level shifting unit for shifting the level of the input signal and outputting the pre-output signal; And
And a signal output unit which buffers the pre-output signal and outputs the output signal as the output signal.
KR1020110096037A 2011-09-23 2011-09-23 Level shifting device KR20130032454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110096037A KR20130032454A (en) 2011-09-23 2011-09-23 Level shifting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110096037A KR20130032454A (en) 2011-09-23 2011-09-23 Level shifting device

Publications (1)

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KR20130032454A true KR20130032454A (en) 2013-04-02

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KR1020110096037A KR20130032454A (en) 2011-09-23 2011-09-23 Level shifting device

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