KR20110125029A - Nonvolatile memory device and program method thereof - Google Patents

Abstract

PURPOSE: A nonvolatile memory device and a program method thereof are provided to reduce the threshold voltage distribution of a memory cell by reducing a noise voltage of a noise voltage in a common source line. CONSTITUTION: In a nonvolatile memory device and a program method thereof, a program voltage is applied. A selection verification operation is performed. The selection verification operation selects memory cells to be programmed. The memory cells are programmed to a target program states. An consecutive verification operation is performed. The consecutive verification operation precharges the bit line of the memory cells and determines whether a programming is performed or not.

Description

Nonvolatile memory device and its program method {NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF}

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device and a program method thereof for reducing noise of a common source line.

Semiconductor memory devices are generally classified into volatile memory and nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, while nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Nonvolatile memory devices include various types of memory cell transistors. Nonvolatile memory devices include flash memory, ferroelectric RAM (FRAM), magnetic RAM (MRAM), and phase change RAM (PRAM), depending on the structure of the memory cell transistor. do.

Flash memory devices are classified into NOR flash memory devices and NAND flash memory devices according to cell array structures. The NOR flash memory device has a structure in which memory cell transistors are independently connected to a bit line and a word line, respectively. Thus, NOR flash memory devices have excellent random access time characteristics. On the other hand, the NAND flash memory device has a structure in which a plurality of memory cell transistors are connected in series. Such a structure is called a cell string structure and requires one bit line contact per cell string. Therefore, the NAND flash memory device has excellent characteristics in terms of integration degree.

The flash memory device includes a memory cell array for storing data. The memory cell array is composed of a plurality of memory blocks. Each memory block consists of a plurality of pages. Each page consists of a plurality of memory cells. Each memory cell is divided into an on cell and an off cell according to a threshold voltage distribution. The on cell is an erased cell and the off cell is a programmed cell. The flash memory device performs an erase operation on a memory block basis and a read or write operation on a page basis due to a structural feature.

The flash memory device has a cell string structure. The cell string includes a string select transistor (SST) connected to a string select line (SSL), memory cells connected to a plurality of word lines (WL), and a ground select line (ground select). and a ground select transistor (GST) connected to the line: GSL. The string select transistor is connected to a bit line BL, and the ground select transistor is connected to a common source line CSL.

Meanwhile, when a noise voltage occurs in the common source line CSL, the noise voltage of the common source line CSL may cause a malfunction of the flash memory device. For example, a particular memory cell may be verified as programmed even though it is not sufficiently programmed (or written). When the corresponding memory cell is read after the program operation is completed, the memory cell may be read as an unprogrammed memory cell due to such a malfunction.

It is an object of the present invention to provide a nonvolatile memory device and a program method thereof that can reduce noise of a common source line.

A program method of a nonvolatile memory device for programming a plurality of memory cells into a plurality of target program states according to an embodiment of the present invention, the method comprising: applying a program voltage; Performing a selective verify operation to select memory cells to be programmed to some target program states of the plurality of target program states; And pre-charging the bit lines of the memory cells selected by the selection verifying operation to perform a sequential verifying operation to determine whether the program is programmed.

In an embodiment, the selective verify operation is performed before the sequential verify operation.

In an embodiment, in performing the selection verify operation, bit lines of memory cells to be programmed to the some target program states are selectively precharged.

In example embodiments, a program verification result may be determined according to each program state of the precharged memory cells.

In an embodiment, the non-precharged memory cells are determined to be program failed.

In an embodiment, the sequential verify operation is performed for each of the some target program states.

In example embodiments, the sequential verify operation selectively precharges the memory cells according to a program verify result of the selective verify operation or the sequential verify operation previously performed.

In the embodiment, in the sequential verification operation, the memory cells determined to have been program-passed are selectively precharged.

In an embodiment, in the sequential verification operation, a ground voltage is applied to a bit line of a memory cell determined to be program failed.

In example embodiments, the sequential verify voltage applied in the performing the sequential verify operation may be higher than the select verify voltage applied in the performing the select verify operation.

In example embodiments, the program voltage applied in the programming may be higher than the sequential verify voltage.

In an embodiment, the programming, performing the selective verification, and performing the sequential verification constitute one program loop, and the program loop is repeated a predetermined number of times.

In an embodiment, the program voltage applied in the programming step is increased by a predetermined increment every time the program loop is increased.

In an embodiment, the target program state consists of one erase state and a plurality of program states.

In example embodiments, the plurality of program states may be determined according to the number of data bits that the memory cell can store.

In an embodiment, a nonvolatile memory device may include: memory cells connected to a word line and a bit line and programmed into a plurality of target program states; Data input / output circuits connected to each of the bit lines to precharge the bit lines and read data stored in the memory cells; And control logic to control the data input / output circuits to apply a program voltage to the word line and to perform a program verify operation for determining whether the memory cells are programmed, wherein the program verify operation includes the plurality of target programs. A select verify operation for selecting the memory cells to be programmed to the target program states of some of the states, and a sequential verify operation for determining whether to program by precharging a bit line of the memory cells selected by the select verify operation. do.

In example embodiments, the control logic performs the selective verification operation before the sequential verification operation.

In example embodiments, data input / output circuits of memory cells to be programmed to the some target program states precharge respective bit lines during the selection verify operation.

In example embodiments, the sequential verify operation may be performed for each of the plurality of target program states, and during the sequential verify operation, the data input / output circuits may be configured to the program verify result of the selective verify operation or the previously performed sequential verify operation. Selectively precharge each bit line accordingly.

In some example embodiments, the data input / output circuits of the memory cells determined to have been program-passed precharge each bit line.

The nonvolatile memory device according to the present invention can reduce the noise voltage of the common source line during a program operation, and reduce the widening of the threshold voltage distribution of the memory cell by reducing the noise voltage of the common source line.

1 is a block diagram illustrating a nonvolatile memory device in accordance with an embodiment of the present invention.
FIG. 2 is a circuit diagram exemplarily illustrating a structure of a memory cell array shown in FIG. 1.
3 is a diagram illustrating an error of a threshold voltage of a memory cell.
4 is a diagram illustrating the number of on cells when a program verify voltage is applied to a selected word line.
5 is a diagram illustrating a threshold voltage distribution of a memory cell affected by a noise voltage present in a common source line.
6 is a diagram illustrating a program state of a multi-level cell according to an embodiment of the present invention.
7 is a flowchart illustrating a program operation according to an embodiment of the present invention.
8 is a diagram illustrating a program verify voltage of a multi-level cell according to an embodiment of the present invention.
9 is a diagram illustrating a bias condition of a program operation according to an embodiment of the present invention.
10 is a flowchart illustrating a program operation according to an embodiment of the present invention.
11 is a block diagram illustrating a user device including a nonvolatile memory device according to an embodiment of the present invention.
12 is a block diagram illustrating another user device including a nonvolatile memory device according to an embodiment of the present invention.
FIG. 13 is a block diagram illustrating an example computing system equipped with the data storage device of FIG. 11.

Advantages and features of the present invention, and methods for achieving the same will be described with reference to embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Although specific terms are used herein. It is used for the purpose of illustrating the present invention and is not intended to limit the scope of the present invention as defined in the meaning limitations or claims.

The expression " and / or " is used herein to mean including at least one of the elements listed before and after. In addition, the expression “connected / combined” is used to include directly connected to or indirectly connected to other components. In this specification, the singular forms also include the plural unless specifically stated otherwise in the phrases. Also, as used herein, "comprising" or "comprising" means to refer to the presence or addition of one or more other components, steps, operations and elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating a nonvolatile memory device in accordance with an embodiment of the present invention.

The nonvolatile memory device according to the embodiment of the present invention will be configured as a NAND flash memory device. However, it will be understood that the nonvolatile memory device is not limited to the NAND flash memory device. For example, the nonvolatile memory device may be configured as one of nonvolatile memory devices such as a NOR flash memory device, a phase-change RAM (PRAM), a ferroelectric RAM (FRAM), and a magnetic RAM (MRAM).

Referring to FIG. 1, the flash memory device 100 may include a memory cell array 110, a row decoder 120, control logic 130, and a data input / output circuit. output circuit 140). The control logic 130 also includes a voltage generator 135.

The memory cell array 110 includes memory cells for storing data. The plurality of memory cells constitute a page. A plurality of pages constitute a block. The flash memory device performs a read or write operation in units of pages and an erase operation in units of blocks due to structural features.

Each memory block is composed of a plurality of cell strings connected to a plurality of bit lines BL0 to BLm. As an example, one block is shown in FIG. Each cell string includes a string select transistor (SST) connected to a string select line SSL and a plurality of memory cells connected to a plurality of word lines WL0 to WLn. M0 to Mn) and a ground select transistor GST connected to a ground select line GSL. The string select transistor SST is connected to the bit line BL0, and the ground select transistor GST is connected to a common source line CSL.

Each memory cell of the memory cell array 110 may store single bit data or multi bit data. A memory cell that stores single bit data is called a single level cell (SLC), and a memory cell that stores two or more bits of multi bit data is called a multi level cell (MLC). The single level cell SLC has an erase state and one program state according to a threshold voltage. The multi-level cell MLC has an erase state and a plurality of program states according to a threshold voltage.

The row decoder 120 is connected to the memory cell array 110 through a plurality of word lines. The row decoder 120 receives an address ADDR. The row decoder 120 selects a block or page of the memory cell array 110 according to a row address. The control logic 130 controls overall operations of the flash memory device 100 in response to a command CMD and a control signal CTRL of an external device (for example, a host, a memory controller, and a memory interface). For example, the control logic 130 controls read, write (or program) and erase (or erase) operations of the flash memory device 100. For this operation, the control logic 130 controls the voltage generator 135 to generate a bias voltage.

The voltage generator 135 included in the control logic 130 generates a bias voltage to be provided to the bit line during read, write, and erase operations. In addition, the voltage generator 135 generates a bias voltage to be provided to the word line during read, write and erase operations. For example, in a read operation, the voltage generator 135 generates a select read voltage V _RD provided to the selected word line, an unselect read read voltage V _READ provided to the unselected word line, and the like. As another example, during a write operation, the voltage generator 135 generates a program voltage V _PGM , a verify voltage V _VRF , and the like.

The data input / output circuit 140 is connected to the memory cell array 110 through a plurality of bit lines BL0 to BLm. The data input / output circuit 140 includes a plurality of data input / output circuits 141_0 to 141_m. Each of the data input / output circuits 141_0 to 141_m is connected to a plurality of bit lines BL0 to BLm, respectively. The data input / output circuit 140 outputs and receives data through a data input / output buffer (not shown).

The data input / output circuit 140 reads data stored in a selected memory cell among a plurality of memory cells through a bit line. The read data is output to the outside of the flash memory device through the data input / output buffer. In addition, the data input / output circuit 140 temporarily stores data to be programmed in the selected memory cell among the plurality of memory cells. Data stored in the data input / output circuit 140 is programmed in a corresponding memory cell during a program operation. The operation of the data input / output circuit 140 is performed under the control of the control logic 130.

In the program operation, the flash memory device 100 applies a program voltage V _PGM to a selected word line and then performs a program verify operation. The program verify operation is an operation for verifying whether the threshold voltage of the memory cell has reached a target program state. The program verify operation is performed simultaneously on a plurality of memory cells connected to the select word line. Accordingly, the plurality of memory cells include cells that require program verification and cells that do not. Here, the memory cell that does not require program verification will be a memory cell having a threshold voltage lower than the target program state. Alternatively, a memory cell that does not require program verification may be a memory cell whose threshold voltage reaches a target program state. Alternatively, a memory cell that does not require program verification may be a memory cell programmed from different temporary program states when the memory cell is programmed from a temporary program state to a target program state.

A program verifying operation according to an exemplary embodiment of the present invention includes a selective verify operation and a sequential verify operation. In the selection verify operation, the data input / output circuit 140 selectively precharges the corresponding bit line according to the temporary program state of the stored data. For example, the data input / output circuit 140 applies a bit line voltage to a bit line so that memory cells programmed from the same temporary program state are precharged. On the other hand, the data input / output circuit 140 applies a ground voltage to the bit line so that memory cells programmed from the temporary program state except for the temporary program state in which the select verify operation is performed are not precharged.

If it is determined that the memory cell is a program pass by the selective verify operation, that is, if it is determined to be an off cell, the subsequent sequential verification operation is performed only for the memory cell determined as the off cell. In the sequential verification operation, the data fetching circuit 140 selectively precharges each bit line according to the result of the selective verification operation performed previously or the sequential verification operation performed previously. For example, the data input / output circuit 140 may be connected to a bit line such that a bit line of a memory cell program-passed (i.e., determined as an off cell) is precharged in a previously performed selective verify operation or a sequential verify operation previously performed. Apply a bit line voltage. On the other hand, the data input / output circuit 140 is grounded to the bit line so that the bit line of the program fail (ie, determined as on-cell) memory cell is not precharged in the selective verification operation or the previously performed sequential verification operation. Apply voltage.

Thus, according to an embodiment of the present invention, a memory cell that does not require program verification (for example, a memory cell having a threshold voltage lower than a target program state, a memory cell reaching a target program state, or a different temporary program) The memory cell programmed from the state will not flow on cell current during subsequent program verify operations. When the on cell current decreases, noise of the common source line CSL generated when current flows in the common source line CSL will be reduced. This operation will be described in detail with reference to FIG. 7 described below.

FIG. 2 is a circuit diagram exemplarily illustrating a structure of a memory cell array shown in FIG. 1.

Referring to FIG. 2, one memory block included in the memory cell array 110 is illustrated. The memory cell array 110 includes a plurality of memory blocks, and each memory block includes a plurality of cell strings connected to the plurality of bit lines BL0 to BLm. Each cell string includes a plurality of memory cells M0 to Mn connected between the bit line BL and the common source line CSL. Each cell string includes a string select transistor SST connected to a string select line SSL, a plurality of memory cells connected to a plurality of word lines WL0 to WLn, and a ground select connected to a ground select line GSL. And a transistor GST.

The string select transistor SST is connected to the bit line BL0, and the ground select transistor GST is connected to the common source line CSL. In addition, the resistors R _P0 to R _Pm represent a resistance component present in the common source line CSL. For example, the resistors R _P0 to R _Pm represent parasitic resistances or parasitic capacitances of the common source line CSL (hereinafter referred to as parasitic resistances).

In the program verify operation or the read operation, the amount of current flowing through the cell string depends on the number of on cells. The common source line voltage V _CSL varies depending on the amount of current flowing in the cell string. In order to examine the change of the common source line voltage V _CSL according to the number of on cells, the following two assumptions are made. First, the memory cell M0 connected to the select word line WL0 is in an erased state, and the memory cell M0_1 connected to the select word line WL0 is in a program state. Second, when the memory cells connected to the select word line WL0 are on cells, it is assumed that currents flowing through the respective cell strings are i0 and i1.

According to this assumption, the common source line voltage V _CSL varies according to the number of on cells. For example, only the memory cell M0 connected to the select word line WL0 of the bit line BL0 is an on cell, and the memory cell M0_1 connected to the select word line WL0 of the bit line BL1 is an off cell. In this case, the voltage across the resistor R _P0 becomes (i0 × R _P0 ), and a common source line voltage V _CSL is generated. As another example, when the memory cells M0 and M0_1 connected to the selection word line WL0 of the bit lines BL0 and BL1 are on cells, the voltage across the resistor R _P0 is (i0 × R _P0 ). The voltage across the resistor R _P1 becomes (i1 × R _P1 ), and a common source line voltage V _CSL is generated. This means that in the read or program verify operation, if the number of on cells is changed, the common source line voltage V _CSL may also be changed. Accordingly, the program verifying operation according to an exemplary embodiment of the present invention may reduce the number of on cells by selectively precharging the memory cells through the selective program verifying operation and the sequential program verifying operation.

3 is a diagram illustrating an error of a threshold voltage of a memory cell.

Referring to FIG. 3, one memory cell included in a memory cell array (see 110 of FIG. 1) is illustrated. When a current flows in the common source line CSL, a voltage change of the common source line CSL may occur due to a parasitic resistance. The voltage change of the common source line becomes the noise voltage of the common source line CSL, that is, the common source line voltage V _CSL .

Meanwhile, the control gate G of the memory cell is controlled according to the voltage provided from the voltage generator (see 135 in FIG. 1). The voltage generator 135 generates a voltage V _GG based on the ground GND. However, the channel formed during the program verify operation or the read operation of the memory cell is controlled according to the voltage difference V _GS between the control gate G and the source S of the memory cell. Therefore, there is a voltage difference V _CSL between the voltage V _GG actually supplied to the control gate G of the memory cell and the voltage V _GS affecting channel formation of the memory cell.

The common source line voltage V _CSL may generate a detection error of the data input / output circuit (see 120 of FIG. 1) during a program verify operation or a read operation. This common source line voltage V _CSL is dependent on or off depending on the data of the memory cells. Thus, the common source line voltage V _CSL is not constant, frequently changes, and cannot be easily removed.

4 is a diagram illustrating the number of on cells when a program verify voltage is applied to a selected word line.

Referring to FIG. 4, an exemplary voltage distribution of a single level cell SLC storing one bit of data is illustrated. The memory cell is divided into an erase state E and a program state P according to a threshold voltage. In a read operation, the select word line is provided with a select read voltage V _RD . On the other hand, during the program verify operation, the program verify voltage V _VRF is provided to the selected word line. When the program verify voltage V _VRF is applied, the cells identified as on cells among the memory cells are cells included in the hatched portion. That is, the memory cell in the erase state E is identified as an on cell. Among the cells to be programmed in the program state P, the memory cell P ′ whose threshold voltage has not yet exceeded the program verification voltage V _VRF may be identified as an on cell.

As described with reference to FIG. 2, the common source line CSL is generally connected to the ground terminal through a metal line. Since a resistance component exists in the metal line, when a current flows in the common source line _CSL , a change in the common source line voltage V _CSL occurs. Here, the common source line voltage V _CSL is proportional to the cell current due to the on cell. For example, when the number of on cells of the memory cells connected to the selected word line increases so that the amount of current flowing through the common source line CSL increases, the common source line voltage V _CSL may increase. The change in the common source line voltage V _CSL becomes noise existing in the common source line CSL.

5 is a diagram illustrating a threshold voltage distribution of a memory cell affected by a noise voltage present in a common source line.

Referring to FIG. 5, threshold voltage distributions of memory cells that are not sufficiently programmed are shown. As described above, when the number of on cells increases during the program verify operation, the amount of current flowing through the common source line CSL increases. When the amount of current flowing through the common source line CSL increases, the common source line voltage V _CSL increases due to the influence of parasitic resistance and the like. As the common source line voltage V _CSL increases, the amount of current sensed by the data input / output circuit (see 140 of FIG. 1) decreases.

When the amount of current sensed by the data input / output circuit 120 decreases, the threshold voltage distribution of the memory cell is considered to have reached the program state P, thereby completing the program operation. That is, even though the memory cell is not sufficiently programmed, the memory cell may be verified as programmed and the program operation may be completed. In this case, the threshold voltage distribution of the memory cell is widened due to the memory cells distributed in the hatched portion in FIG. 5. After the program operation is completed, memory cells whose threshold voltage does not exceed the program verify voltage V _VRF may be read into the unprogrammed memory cells.

6 is a diagram illustrating a program state of a multi-level cell according to an embodiment of the present invention.

The multi-level cell MLC has an erase state and a plurality of program states according to a threshold voltage. In multi-level cells (MLC), it is important to narrowly manage the threshold voltage distribution of a plurality of program states in order to increase the reliability of data. As shown in FIG. 6, in order to narrowly manage the threshold voltage distribution, the multi-level cell MLC may perform target program states from the temporary program states TST1 to TST4 formed by a temporary program operation. ST1 to ST16). The temporary program states TST1 to TST4 and the target program states ST1 to ST16 are determined according to the data value of the page. For example, the temporary program states TST1 to TST4 and the target program states ST1 to ST16 may include data of the first and second lower bit LSB pages and the first and second higher bit MSB pages. It will depend on the value.

In FIG. 6, a threshold voltage distribution of a multi-level cell (MLC) that stores four bits of data is illustrated. The memory cell is programmed to any one of sixteen states ST1 to ST16 according to the data value of the page. In order to narrowly manage the threshold voltage distribution, the memory cell is programmed from the temporary program state TST1 to the target program states ST2 to ST4. This programming method is shown by arrow ①. Further, as shown by arrows (2), (3), and (4), the memory cell is each of the target program states ST5 to ST8, ST9 to ST12, and ST13 to ST16 from the temporary program states TST2, TST3, and TST4, respectively. Is programmed.

For convenience of explanation, the memory cell programmed from the temporary program state TST1 will be described as an example. A memory cell having a temporary program state (TST1, that is, a '11' state) maintains a target program state (ST1, that is, a '1111' state) according to the first and second high order bits MSB. Alternatively, a memory cell having a temporary program state (TST1, that is, an '11' state) may be configured to have a target program state (ST2, that is, a '0111' state), a target program according to the first and second high order bits MSB. It is programmed to a state ST3 (that is, a '0011' state) and a target program state (ST4, that is, a '1011' state). In other words, the memory cell is programmed to the target program state based on the temporary program state. Therefore, according to an embodiment of the present invention, in the target program verifying operation, the program verifying operation is performed not only for the target program state but also for the temporary program state. In addition, during the target program verify operation, the memory cells are selectively precharged according to the temporary program state and the target program state.

7 is a flowchart illustrating a program operation according to an embodiment of the present invention.

The flash memory device (see 100 of FIG. 1) uses an incremental step pulse program (ISPP) scheme to narrow the threshold voltage distribution of the memory cell. According to the incremental step pulse program (ISPP) scheme, the control logic (see 130 of FIG. 1) controls the voltage generator (135 of FIG. 1) so that the program voltage applied to the selected word line is increased step by step. Since a program voltage increased by a predetermined increment ΔV is applied to the selected word line until the program operation is completed, the program operation is composed of a plurality of program loops program loop_1 to program loop_m.

Each of the program loops includes a program operation and a program verify operation. In a program operation, a memory cell is programmed according to a given bias condition (e.g., a program voltage applied to a word line and a bit line voltage applied to a bit line). In the program verify operation, whether the memory cell has been programmed up to the target program state is verified. The control logic 130 will repeatedly execute the program loop within a predetermined number of times until all the memory cells are programmed.

Although not shown, the program verifying operation includes a precharge period, a development period, a sensing period, and a discharge period. A predetermined voltage is applied to the bit line in the precharge period, a verification voltage V _VRF is applied to the word line in the development period, and the state of the memory cell is determined in the sensing period. It will be appreciated that the program verify operation may be identical to the read operation except that the read data is not output externally.

The program verifying operation includes a plurality of selective verifying operations (selective verify_1 to selective verify_n) and a plurality of sequential verifying operations (sequential verify_1 to sequential verify_n). The selective verify operation is to verify the memory cell according to the temporary program state to reduce the on cell current before verifying whether it is programmed to the target program state. The sequential verification operation verifies a memory cell according to a result of the selective verification operation performed previously or the sequential verification operation performed previously. Thus, each of the sequential verify operations is performed after the select verify operations. Further, each of the sequential verify operations will be performed by the number of target program states that can be programmed from the temporary program state. In FIG. 7, each of the sequential verification operations is configured of a plurality of sequential verify operations sequential verify_1a to sequential verify_1z.

As illustrated in FIG. 1, each of the data input / output circuits (refer to 141_0 to 141_m in FIG. 1) is configured to correspond to the bit lines BL0 to BLm, respectively. While the selection verify operation is performed, each of the data input / output circuits 141_0 to 141_m selectively activates each bit line according to the temporary program state of the stored data. For example, during the selection verification operation, each of the data input / output circuits 141_0 to 141_m precharges the corresponding bit line for each temporary program state of the stored data.

When the selection verify operation is completed, the program state (eg, program pass or fail) of the memory cell connected to the precharged bit line is determined according to the state of the memory cell, and the program state is stored in the corresponding data input / output circuit. On the other hand, the program state (eg, program pass or fail) of a memory cell (ie, a memory cell programmed from another temporary program state) connected to a non-precharged bit line is program failed and stored in the corresponding data input / output circuit. .

A memory cell determined as a program fail (i.e., a memory cell determined as an on cell) by the selective verify operation does not perform a subsequent sequential verify operation. In other words, only the memory cells identified as off cells by the select verify operation are verified in subsequent sequential verify operations. Therefore, the number of on cells can be reduced during the sequential verification operation.

During the sequential verification operation, each of the data input / output circuits 141_0 to 141_m selectively activates each bit line according to the selection verification operation performed previously or the sequential verification result previously performed. For example, during the sequential verification operation, each of the data input / output circuits 141_0 to 141_m is determined as a memory cell (ie, an off cell) determined as a program pass in the previously performed selective verification operation or the previously performed sequential verification operation. Pre-charge only the bit lines). In other words, memory cells that do not approach the target program state are excluded from the sequential verify operation. Therefore, the number of on cells can be reduced during the sequential verification operation.

8 is a diagram illustrating a program verify voltage of a multi-level cell according to an embodiment of the present invention.

As described with reference to FIG. 7, one program verify operation according to an embodiment of the present invention includes a plurality of selective verify operations and a plurality of sequential verify operations. Referring to FIG. 8, the control logic (see 130 of FIG. 1) applies each of the selection verify voltages V _SLVRF11 , V _SLVRF01 , V _SLVRF00 , and V _SLVRF10 to the select word line, thereby corresponding to the corresponding select verify operations ( Perform selective verify 11, selective verify 01, selective verify 00, and selective verify 10). In addition, the control logic 130 applies each of the sequential verify voltages V _SQVRFxx11 , V _SQVRFxx01 , V _SQVRFxx00 , and V _SQVRFxx10 to the selected word line, so that the corresponding sequential verify operations (sequential verify 11, sequential verify 01, sequential verify 00, and sequential verify 10).

For better understanding of the program verifying operation described with reference to FIG. 7, the program operation of the memory cell programmed from the temporary program state TST1 to the target program states ST2, ST3, and ST4 will be described with reference to FIGS. 1 and 8. Let's do it.

The control logic 130 applies a program voltage V _PGM to the selected word line for programming to the target program states ST2, ST3, and ST4 according to the data stored in the data input / output circuit 140. Thereafter, the control logic 130 applies program verify voltages V _VRF to the selected word line to perform a program verify operation. That is, the control logic 130 sequentially _applies the first select verify voltage V _SLVRF11 and the first through third sequential verify voltages V _SQVRFxx11 to the select word line.

While the first selective verify operation 11 for the temporary program state TST1 is performed, memory cells programmed from the temporary program state TST1 (that is, memory cells whose target program states are ST2, ST3, and ST4). ) Only the data input / output circuitry precharges each bit line. When the control logic 130 _applies the first select verify voltage V _SLVRF11 to the select word line, the program state (eg, program pass or fail) of the memory cell connected to the precharged bit line is the state of the memory cell. The program state is stored in the corresponding data input / output circuit. At this time, the data input / output circuits of the memory cells that are not programmed from the temporary program state TST1 (that is, memory cells programmed from the temporary program states TST2, TST3, and TST4) are programmed to fail the program state (that is, the memory cells On cell).

After the first selective verify 11 is performed, the first sequential verify 11a for the target program state ST2 is performed. While the first sequential verify operation 11a is performed, the data input / output circuit of the memory cell determined to be an off-cell (ie, the data input / output circuit that is stored in the program path as a result of the verification of the first selective verify operation 11) is stored. ) Only precharges each bit line. When the control logic 130 _applies the first sequential verify voltage V _SQVRF0111 to the select word line, the program state (eg, program pass or fail) of the memory cell connected to the precharged bit line is the state of the memory cell. The program state is stored in the corresponding data input / output circuit.

After the first sequential verify operation 11a is performed, a second sequential verify operation 11b for the target program state ST3 is performed. While the second sequential verify 11b is performed, the data input / output circuit of the memory cell determined to be off-cell (ie, the data input / output circuit which has been stored in the program path as a result of the verification of the first sequential verify 11a) is stored. ) Only precharges each bit line. When the control logic 130 _applies the second sequential verify voltage V _SQVRF0011 to the select word line, the program state (eg, program pass or fail) of the memory cell connected to the precharged bit line is the state of the memory cell. The program state is stored in the corresponding data input / output circuit. At this time, the on-cell current flows in the memory cell having a threshold voltage larger than the first sequential verification voltage V _SQVRF0111 and the memory cell having a threshold voltage smaller than the second sequential verification voltage V _SQVRF0011 . That is, the on-cell current flows through the memory cell where the threshold voltage is between the section A.

Meanwhile, among the memory cells programmed from the temporary program state TST2 to the target program states ST5, ST6, ST7, and ST8, a memory cell having a threshold voltage between the section B has a second sequential verify operation. On cell current will not flow while 11b) is performed. This is because the data input / output circuits of the memory cells programmed from the temporary program states TST2, TST3, and TST4 other than the temporary program state TST1 have the program state program-failed during the first selective verify operation. This is because the bit line is not precharged at the time of the second sequential verify operation 11 (ie, determined to be on cell). Thus, the on cell current will be reduced.

After the second sequential verify 11b is performed, a third sequential verify 11c for the target program state ST4 is performed. While the third sequential verify 11c is performed, the data input / output circuit of the memory cell determined to be off-cell (ie, the data input / output circuit is stored in the program path as a result of the verification of the second sequential verify 11b). ) Only precharges each bit line. When the control logic 130 _applies the third sequential verify voltage V _SQVRF1011 to the select word line, the program state (eg, program pass or fail) of the memory cell connected to the precharged bit line is the state of the memory cell. The program state is stored in the corresponding data input / output circuit. At this time, an on-cell current flows in the memory cell having a threshold voltage greater than the second sequential verification voltage V _SQVRF0011 and the memory cell having a threshold voltage smaller than the third sequential verification voltage V _SQVRF1011 . That is, the on-cell current flows through the memory cell where the threshold voltage is between the C sections.

Meanwhile, among the memory cells programmed from the temporary program state TST2 to the target program states ST5, ST6, ST7, and ST84, the memory cell in which the threshold voltage is between the C sections is a third sequential verify operation. On cell current will not flow while 11c) is performed. This is because the data input / output circuits of the memory cells programmed from the temporary program states TST2, TST3, and TST4 other than the temporary program state TST1 are stored as program fail (i.e., in the first selection verify operation). This is because the bit line is not precharged at the time of the third sequential verify 11c. Thus the on cell current will be reduced.

9 is a diagram illustrating a bias condition of a program operation according to an embodiment of the present invention.

8 and 9, the control logic (see 130 in FIG. 1) may program the program voltage V _PGM for programming to target program states according to data stored in the data input / output circuit (140 in FIG. 1). Applies to the selected word line. Thereafter, the control logic 130 applies program verify voltages V _VRF to the selected word line to perform a program verify operation. That is, the control logic 130 may include the first select verify voltage V _SLVRF11 , the first through third sequential verify voltages V _SQVRFxx11 , the second select verify voltage V _SLVRF01 , and the fourth through seventh sequential verify voltages. V _SQVRFxx01 , third select verify voltage V _SLVRF00 , eighth through eleventh sequential verify voltages V _SQVRFxx00 , fourth select verify voltage V _SLVRF10 , and twelfth through fifteenth verify voltages (V _SQVRFxx10 ) is sequentially applied to the selected word line.

Since the program voltage increased by a predetermined increment ΔV is applied to the select word line until the program operation is completed, the program verify voltages (selective verify voltages and sequential verify voltages) are also applied whenever the program voltage is applied. It is applied sequentially. The program verify voltages (selective verify voltages and sequential verify voltages) that are applied are gradually increased in the order in which they are applied. That is, the first selective verify voltage V _SLVRF11 is the smallest voltage value, and the fifteenth sequential verify voltage V _SQVRF1110 is the largest voltage value. Also, each of the program verify voltages (selective verify voltages and sequential verify voltages) is applied with a voltage smaller than the program voltage.

10 is a flowchart illustrating a program operation according to an embodiment of the present invention. Program operations according to an embodiment of the present invention will be described with reference to FIGS. 1 and 10.

The control logic 130 applies a program voltage V _PGM to the selected word line for programming to the target program state according to the data stored in the data input / output circuit 140 (step S110). After applying the program voltage V _PGM , the control logic 130 performs a selective verify operation according to the temporary program state (S120). During the select verify operation, each of the data input / output circuits 140 selectively precharges the corresponding bit line only when the select verify operation for the temporary program state of the stored data is performed. The control logic 130 will control the voltage generator 135 such that the select verify voltage V _SLVRF is applied to the select word line. When the selection verify operation is completed, the program state of the memory cell connected to the precharged bit line is determined according to the state of the memory cell, and the program state is stored in the corresponding data input / output circuit.

After the selection verify operation is performed, the control logic 130 performs a sequential verification operation according to the target program state that can be programmed from the temporary program state where the selection verify operation is performed (step S130). During the sequential verification operation, each of the data input / output circuits 140 selectively precharges the corresponding bit line according to the selective verification operation performed previously or the sequential verification result performed previously. That is, each of the data input / output circuits 140 precharges only the bit lines of the memory cells that have been program-passed in the selective verify operation or the sequential verify operation previously performed.

The control logic 130 will control the voltage generator 135 such that the sequential verify voltage V _SQVRF is applied to the selected word line. When the sequential verification operation is completed, the program state of the memory cell connected to the precharged bit line is determined according to the state of the memory cell, and the program state is stored in the corresponding data input / output circuit.

The sequential verification operation consists of a plurality of sequential verification operations. The control logic 130 determines whether or not the sequential verification operation is performed on all target program states that can be programmed from the temporary program state in which the selective verifying operation is performed (step S140). If the sequential verify operation for all target program states that can be programmed from the temporary program state in which the selective verify operation is performed is not performed, the control logic 130 thresholds the sequential verify operation (step S130) for the remaining target program states. It executes sequentially from the small target program state.

If the sequential verify operation is performed on all target program states that can be programmed from the temporary program state on which the select verify operation has been performed, the control logic 130 determines whether the select verify operation is performed on all the temporary program states. (Step S150). This temporary program state will be determined by the number of bits that the memory cell can store. If the selective verify operation is not performed for all the temporary program states, the control logic 130 sequentially performs the selective verify operation (step S120) for the remaining temporary program states from the temporary program state having a small threshold voltage level.

If the selective verify operation for all the temporary program states and the sequential verify operation for all the target program states are performed sequentially according to the magnitude of the threshold voltage, the control logic 130 determines whether all of the memory cells to be programmed are programmed through. Check (S160 step). If all of the memory cells to be programmed are programmed, the control logic 130 ends the program operation. If all of the memory cells to be programmed are not programmed, the control logic 130 applies the program voltage within a predetermined number of times (step S110), select verification operation (step S120), and sequential verification operation (step S130). Repeatedly

A program verifying operation according to an exemplary embodiment of the present invention includes a selective verify operation and a sequential verify operation. In the selection verify operation, the data input / output circuit 140 selectively precharges the corresponding bit line according to the temporary program state of the stored data. In the sequential verification operation, the data fetching circuit 140 selectively precharges each bit line according to the result of the selective verification operation performed previously or the sequential verification operation performed previously. Thus, memory cells that do not require program verification (e.g., memory cells with threshold voltages lower than the target program state, memory cells that reach the target program state, or memory cells programmed from different temporary program states) On-cell current will not flow during subsequent program verify operations. When the on cell current decreases, the noise voltage of the common source line CSL generated when current flows in the common source line CSL will be reduced.

11 is a block diagram illustrating a user device including a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 11, the data storage device 1000 may be a solid state drive (hereinafter, referred to as 'SSD'). The SSD 1100 may include an SSD controller 1200, a buffer memory device 1300, and a storage medium 1400. The SSD 1100 according to an embodiment of the present invention may further include a temporary power supply circuit including super capacitors. The temporary power supply circuit may supply power such that the SSD 1100 is normally terminated when sudden power off occurs.

The SSD 1100 is operated in response to an access request of the host 1500. That is, in response to a request from the host 1500, the SSD controller 1200 is configured to access the storage medium 1400. For example, SSD controller 1200 is configured to control read, write, and erase operations of storage medium 220. Data to be stored in the storage medium 1400 is temporarily stored in the buffer memory device 1300. In addition, the data read from the storage medium 1400 is temporarily stored in the buffer memory device 1300. Data stored in the buffer memory device 1300 is transmitted to the storage medium 1400 or the host 1500 under the control of the SSD controller 1200.

The SSD controller 1200 is connected to the storage medium 1400 through a plurality of channels CH0 to CHn. Each of the channels CH0 to CHn is connected to a plurality of nonvolatile memory devices NVM00 to NVM0i and NVn0 to NVni. The plurality of nonvolatile memory devices may share a channel. The storage medium 1400 may be configured as a NAND flash memory device according to an embodiment of the present invention. However, it will be appreciated that the storage medium 220 is not limited to NAND flash memory devices. For example, the storage medium 1400 is configured as one of nonvolatile memory devices such as a NOR flash memory device, a phase-change RAM (PRAM), a ferroelectric RAM (FRAM), and a magnetic RAM (MRAM). Can be.

The storage medium 1400 of the data storage device 1000 according to an exemplary embodiment of the present invention performs a program verifying operation including a selective verifying operation and a sequential verifying operation. Thus, memory cells that do not require program verification (e.g., memory cells with threshold voltages lower than the target program state, memory cells that reach the target program state, or memory cells programmed from different temporary program states) On-cell current will not flow during subsequent program verify operations. When the on cell current decreases, noise of the common source line CSL generated when current flows in the common source line CSL will be reduced. Due to the storage medium 1400, the reliability of the data storage device 1000 may be improved.

12 is a block diagram illustrating another user device including a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 12, the memory system 2000 includes a memory controller 2200 and a nonvolatile memory device. The memory system 2000 may include a plurality of nonvolatile memory devices. The memory system 2000 according to an embodiment of the present invention includes a plurality of nonvolatile memory devices 2900.

The memory controller 2200 is connected to the host 2100 and the nonvolatile memory device 2900. In response to a request from the host 2100, the memory controller 2200 is configured to access the nonvolatile memory devices 2900. For example, the memory controller 2200 is configured to control read, write and erase operations of the nonvolatile memory devices 2900. The memory controller 2200 is configured to provide an interface between the nonvolatile memory devices 2900 and the host 2100. The memory controller 2200 is configured to drive firmware for controlling the nonvolatile memory devices 2900.

The memory controller 2200 may include random access memory (RAM), a central processing unit (CPU), a host interface, an error correcting code (ECC), and a memory interface. And well known components, such as). The RAM 2600 may be used as a working memory of the central processing unit 2400. The central processing unit 2400 controls overall operations of the memory controller 2200.

The host interface 2300 may include a protocol for exchanging data between the host 2100 and the memory controller 2200. For example, the memory controller 2200 may include a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-Express) protocol, and an advanced technology attachment (ATA) protocol. Through one of a variety of interface protocols, such as Serial ATA (SATA) protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol. Host).

The error correction block 2700 may be configured to detect and correct an error of data read from the nonvolatile memory devices 2900. The error correction block 2700 may be provided as a component of the memory controller 2200. As another example, the error correction block 2700 may be provided as a component of each of the nonvolatile memory devices 2900. The memory interface 2500 may interface the nonvolatile memory devices 2900 and the memory controller 2200.

It will be appreciated that the components of the memory controller 2200 are not limited to the components mentioned above. For example, the memory controller 2200 may further include a read only memory (ROM) that stores code data necessary for an initial booting operation and data for interfacing with the host 2100.

The memory controller 2200 and the nonvolatile memory devices 2900 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2200 and the nonvolatile memory devices 2900 may be integrated into a single semiconductor device such that a personal computer memory card international association (PCMCIA) card, a compact flash (CF) card, and smart media are provided. Cards, memory sticks, multi media cards (MMC, RS-MMC, MMC-micro), secure digital (SD) cards (SD, Mini-SD, Micro-SD, SDHC), UFS ( niversal flash storage).

As another example, the memory controller 2200 and the nonvolatile memory devices 2900 may include a solid state drive (SSD), a computer, a portable computer, an ultra mobile personal computer (UMPC), a workbench. Work stations, netbooks, personal digital assistants, web tablets, wireless phones, mobile phones, digital cameras, digital voice recorders (digital audio recorder), digital audio player (digital audio player), digital video recorder (digital video recorder), digital video player (digital video player), device capable of transmitting and receiving information in a wireless environment, home network One of various electronic devices constituting a computer, One of various electronic devices constituting a computer network, Various electronic devices constituting a telematics network One of them, one of various components constituting a computer system, may be applied to a radio frequency identification (RFID) device or an embedded system.

As another example, the nonvolatile memory device 2900 or the memory controller 2200 may be mounted in various types of packages. For example, nonvolatile memory device 2900 or memory system 2000 may include a package on package (POP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in -line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP) , small outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), thin quad flat package (TQFP), system in package (SIP), multi chip package (MCP), wafer-level fabricated It can be packaged and implemented in the same way as a package (WFP) or wafer-level processed stack package (WSP).

The nonvolatile memory device 2900 of the memory system 2000 according to an exemplary embodiment of the present invention performs a program verifying operation including a selective verifying operation and a sequential verifying operation. Thus, memory cells that do not require program verification (e.g., memory cells with threshold voltages lower than the target program state, memory cells that reach the target program state, or memory cells programmed from different temporary program states) On-cell current will not flow during subsequent program verify operations. When the on cell current decreases, noise of the common source line CSL generated when current flows in the common source line CSL will be reduced. Due to the nonvolatile memory device 2900, the reliability of the memory system 2000 may be improved.

FIG. 13 is a block diagram illustrating an example computing system equipped with the data storage device of FIG. 11.

The computer system 3000 according to the present invention includes a network adapter 3100, a central processing unit 3200, a data storage device 3300, a RAM 3400, a ROM 3500, and the like, which are electrically connected to the system bus 3700. User interface 3600.

The network adapter 3100 provides an interface between the computer system 3000 and external networks. The central processing unit 3200 performs various operations for driving an operating system or an application program resident in the RAM 3400. The data storage device 3300 stores various data necessary for the computer system 3000. For example, the data storage device 3300 may include an operating system for operating the computer system 3000, an application program, various program modules, program data, and the like. User data and the like are stored.

The RAM 3400 may be used as a working memory of the computer system 3000. At boot time, the RAM 3400 includes an operating system, an application program, various program modules, and program data required to drive programs read from the data storage device 3300. Is loaded. The ROM 3500 stores a basic input / output system (BIOS), which is a basic input / output system that is activated before the operating system is started at boot time. Information exchange occurs between the computer system 3000 and the user via the user interface 3600.

In addition, the computer system 3000 may further include a battery or a modem. In addition, although not shown in the drawings, it is well understood that a computer system according to the present invention may be further provided with an application chipset, a camera image processor (CIS), a mobile DRAM, or the like. Will be.

100: flash memory device
110: memory cell array
120: row decoder
130: control logic
135: voltage generator
140: data input and output circuit

Claims (10)

A program method of a nonvolatile memory device for programming a plurality of memory cells into a plurality of target program states:
Applying a program voltage;
Performing a selective verify operation to select memory cells to be programmed to some target program states of the plurality of target program states; And
And pre-charging the bit lines of the selected memory cells to perform a sequential verification operation for determining whether to program the bit lines. The method of claim 1,
The selective verify operation is performed before the sequential verify operation. The method of claim 1,
And in the performing the select verify operation, bit lines of memory cells to be programmed to the some target program states are selectively precharged. The method of claim 3, wherein
And a program verification result according to each program state of the precharged memory cells. The method of claim 3, wherein
And the non-precharged memory cells are determined to be program failed. The method of claim 1,
The sequential verify operation is performed on each of the some target program states. The method according to claim 6,
And the sequential verifying operation selectively precharges the memory cells according to a program verifying result of the selective verifying operation or the previously performed sequential verifying operation. The method according to claim 6,
And in the sequential verify operation, selectively precharge a memory cell determined to be a program pass. The method of claim 1,
And the sequential verify voltage applied in performing the sequential verify operation is higher than the select verify voltage applied in performing the select verify operation. Memory cells connected to each of the word line and the bit line and programmed with a plurality of target program states;
Data input / output circuits connected to each of the bit lines to precharge the bit lines and read data stored in the memory cells; And
And a control logic for applying the program voltage to the word line and controlling the data input / output circuits to perform a program verify operation for determining whether the memory cells are programmed.
The program verify operation may include a select verify operation for selecting the memory cells to be programmed to target program states of some of the plurality of target program states, and precharge the bit lines of the memory cells selected by the select verify operation. Nonvolatile memory device including a sequential verify operation for determining whether or not a program.

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