KR100938044B1 - Non volatile memory device and multi level cell programming method thereof - Google Patents

Abstract

A multi-level cell program method of a nonvolatile memory device of the present invention includes applying different data for each cell so that different threshold voltages are set for a plurality of main cells and indicator cells, and programming the main cells and indicator cells. Performing an operation, performing a first verify operation on the main cell and the indicator cell based on a first verify voltage, and a threshold voltage of the first cell among the indicator cells is greater than the first verify voltage. Sequentially repeating the program operation and the first verify operation until the threshold voltage of the first cell is greater than the first verify voltage, and a second verify operation based on a second verify voltage for the main cell. Characterized in that it comprises the step of performing.

Indicator Cell, MLC

Description

Non-volatile memory device and multi level cell programming method

The present invention relates to a non-volatile memory device and a multi-level cell program method of a non-volatile memory device, and more particularly, to a multi-level cell nonvolatile memory device and a program for more efficiently executing a higher bit program for a specific cell. It is about a method.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

Attempts have been made to store more than one bit of data in one cell in order to increase the density of such nonvolatile memory devices. Programming a nonvolatile memory device to store a plurality of bits of data as described above is called a multi-level cell (MLC) programming method. For example, when programming to store 2 bits, a total of four data can be stored in one cell such as '11, 10, 01, 00 ', and the density can be logically increased.

The multilevel cell program method typically includes programming a corresponding cell by applying a program voltage to a word line of a selected cell, and a program verifying operation of determining a program state of the corresponding cell. Unlike a single level cell, a lower bit program operation and an upper bit program operation are separately divided, and in the case of the upper bit program operation, two or more program verify operations are performed based on different verify voltages.

In this case, the program verification (first verification) is performed based on the first verification voltage and the program verification (second verification) is performed based on the second verification voltage higher than the first verification voltage regardless of whether the verification is completed. do. However, according to the configuration in which the program voltage is applied in units of pages, since the program voltage is not programmed to be greater than or equal to the second verification voltage in a situation where the programming voltage is not greater than or equal to the first verification voltage, the second verification is performed in a situation where the first verification is not completed. There is a problem that the efficiency is low.

In order to solve the above problems, the problem to be solved by the present invention is to provide a nonvolatile memory device having an indicator cell.

In addition, an object of the present invention is to provide a multi-level cell program method of a nonvolatile memory device capable of omitting some verification operations using the indicator cell.

The multi-level cell program method of the nonvolatile memory device of the present invention for solving the above problems is the step of applying different data for each cell to set different threshold voltages for a plurality of main cells and indicator cells, and the main Performing a program operation on a cell and an indicator cell, performing a first verify operation on the main cell and the indicator cell based on a first verify voltage, and a threshold voltage of the first cell among the indicator cells Sequentially repeating the program operation and the first verifying operation until the first verifying voltage is greater than the first verifying voltage; and a second verifying voltage for the main cell when the threshold voltage of the first cell is greater than the first verifying voltage. And performing a second verification operation based on the reference.

In addition, the multi-level cell program method of the nonvolatile memory device of the present invention includes applying different data for each cell so that different threshold voltages are set for a plurality of main cells and indicator cells, and for the main cell and the indicator cells. Performing a program operation, performing a first verify operation on the main cell and the indicator cell based on a first verify voltage, and wherein a threshold voltage of a first cell of the indicator cells is greater than the first verify voltage. Sequentially repeating the program operation and the first verify operation until they become large; and when the threshold voltage of the first cell is greater than the first verify voltage, the second verify voltage for the main cell and the indicator cell based on the second verify voltage. Performing a second verify operation, wherein a threshold voltage of a second one of the indicator cells Sequentially repeating the program operation, the first verifying operation, and the second verifying operation until it is greater than the voltage; and if the threshold voltage of the second cell is greater than the second verifying voltage, the main cell and the indicator cell Performing a third verify operation with respect to a third verify voltage, and perform the program operation, the first verify operation, and the second until the threshold voltage of a third cell of the indicator cells is greater than the third verify voltage. Repeatedly performing a verify operation and a third verify operation; and performing a fourth verify operation on the main cell based on a fourth verify voltage when the threshold voltage of the third cell is greater than the third verify voltage. Characterized in that it comprises a step.

In addition, the nonvolatile memory device of the present invention includes a plurality of indicator cells that are subject to verification when verifying whether the main cell is programmed, an indicator cell page buffer that outputs a verification completion signal according to whether the indicator cell is programmed, and the verification And a control logic circuit for changing the verify voltage supply condition by controlling the high voltage generator in accordance with the completion signal.

According to the configuration of the present invention described above, it is possible to shorten the time required for the verification process of the MLC program. That is, unlike the conventional method in which the verification operation is sequentially performed based on the first to Nth verification voltages regardless of whether the threshold voltage is increased, whether to perform the verification operation of the next step according to the increase of the threshold voltage of the indicator cell. The present invention provides a program method capable of determining whether or not to verify some verification operations.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1A to 1D are diagrams illustrating threshold voltage distribution by a multi-level cell program.

1A shows a threshold voltage distribution according to a lower bit program operation.

According to the program operation, cells having threshold voltages greater than or equal to the verification voltage PV1 become program cells.

1B illustrates a threshold voltage distribution according to a 2-bit MLC program operation.

Four different threshold voltage distributions are formed according to the low bit program operation and the high bit program operation, and the verification voltages for the respective bits are also different.

In this case, the verification of the lower bit program is performed based on the second voltage PV2, and the verification of the upper bit program is performed based on the first voltage PV1 or the third voltage PV3.

1C illustrates a threshold voltage distribution according to a 3-bit MLC program operation.

Eight different threshold voltage distributions are formed according to the low bit program operation, the first high bit program operation, and the second high bit program operation, and the verification voltages for each of them are also different.

At this time, the verification of the lower bit program is performed based on the fourth voltage PV4, and the verification of the first higher bit program is performed based on the second voltage PV2 or the sixth voltage PV6. The verification of the higher order bit program is performed based on the first voltage PV1, the third voltage PV3, the fifth voltage PV5, or the seventh voltage PV7.

1D illustrates a threshold voltage distribution according to a 4-bit MLC program operation.

Sixteen different threshold voltage distributions are formed according to the low bit program operation, the first high bit program operation, the second high bit program operation, and the third high bit program operation, and the verification voltages for each of them are also different.

In this case, the verification for the lower bit program is performed based on the eighth voltage PV8, and the verification for the first upper bit program is performed based on the fourth voltage PV4 or the twelfth voltage PV12. 2 The verification for the upper bit program is performed based on the second voltage PV2, the sixth voltage PV6, the tenth voltage PV10, or the fourteenth voltage PV14, and the verification for the third higher bit program. Is the first voltage PV1, the third voltage PV3, the fifth voltage PV5, the seventh voltage PV7, the ninth voltage PV9, the eleventh voltage PV11, the thirteenth voltage PV13, or The operation is performed based on the fifteenth voltage PV15.

FIG. 2A is a diagram illustrating a distribution of threshold voltages by a 3-bit multi-level cell program, FIG. 2B is a flowchart illustrating a typical verify operation for the 3-bit multi-level cell program, and FIG. This is a waveform diagram showing a program voltage and a verification voltage which are commonly applied when programming a level cell.

First, data to be programmed is input to a page buffer connected to a specific cell to be programmed (step 210).

Each cell of the memory cell array is connected to a page buffer through a bit line. The data to be programmed for a specific cell is input to and stored in each register included in the page buffer.

Next, data input to the page buffer is applied to a bit line and a program operation is performed (step 220).

Data stored in the page buffer is applied to each bit line, and the voltage level of the bit line becomes high level or low level according to the stored data. A program voltage is applied to a word line vertically connected to the bit line. The program voltage is applied only to a word line connected to a cell to be programmed, and a pass voltage of a lower level is applied to other word lines. Therefore, when the bit line of a particular cell is at a low level, when a program voltage is applied to the word line, the cell is programmed and other cells remain in the erased state.

On the other hand, the program voltage is repeatedly applied several times as the program voltage is increased by a certain amount according to the ISPP (Incremental Step Pulse Programming) method. According to this process, when the threshold voltage of the program target cells rises above a certain voltage, the program operation is stopped. As such, the step of determining whether the threshold voltages of the corresponding cells has risen above a specific voltage is referred to as a verify operation. Let's look at this more specifically.

First, a verification operation is performed based on the first verification voltage PV (i) (step 230).

In the state where the bit line of the cell to be verified is precharged to a high level, a verify voltage PV (i) is applied to the word line and a pass voltage is applied to the word line.

If the cell is programmed, that is, if the threshold voltage of the cell is greater than the verify voltage PV (i), the cell is not turned on, so that no current path is formed in the cell string containing the cell, The voltage level is kept high.

However, if the cell is not programmed (either erased or programmed and not programmed), that is, if the threshold voltage of the cell is less than the verify voltage PV (i), the cell is turned on to include the cell. A current path is formed in the cell string, so that the voltage level of the bit line, which was precharged to the high level, transitions to the low level. Since the voltage level of the bit line is different depending on whether it is programmed as above, it is applied to the sensing node and stored in the register of the page buffer.

Next, a verification operation is performed based on the second verification voltage PV (i + 1) (step 240).

The same operation as in the verification operation of step 230 is performed. However, the word line to be verified is different in that a second verification voltage PV (i + 1) is applied.

Next, a verification operation is performed based on the third verification voltage PV (i + 2) (step 250).

The same operation as in the verification operation of step 230 is performed. However, the word line to be verified is different in that a third verification voltage PV (i + 2) is applied.

Next, a verification operation is performed based on the fourth verification voltage PV (i + 3) (step 260).

The same operation as in the verification operation of step 230 is performed. However, the word line to be verified is different in that a fourth verification voltage PV (i + 3) is applied.

As described above, after one program pulse is applied, the verify operation is performed by continuously applying the first verify voltage to the fourth verify voltage.

However, assuming that there is a cell to be programmed above the first verify voltage, since the cell is not programmed above the first verify voltage, it is difficult to be programmed above the second to fourth verify voltages. Performing the second to fourth verifications in an incomplete situation has a problem of low efficiency.

Referring to FIG. 2C, the above contents can be more clearly understood.

As shown, different verification voltages are applied four times to check whether the program is completed for each state after the program voltage is applied.

That is, after one program operation, the first to fourth verification operations are sequentially performed regardless of whether the first verification is completed.

3 is a circuit diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

The nonvolatile memory device may include a main cell array 310 in which externally input data is stored through a program operation, and a main cell page configured to temporarily store data to be stored in the main cell or to read and temporarily store data stored in the main cell. A buffer 312, an indicator cell array 320 provided for the verify operation, and an indicator cell page buffer 322 for temporarily storing data to be stored in the indicator cell array or reading and temporarily storing data stored in an indicator setting. do.

In addition, a control logic circuit 330 for controlling the operation of a high voltage generator according to the verification completion signal output from the indicator cell page buffer, and a program voltage, various verification voltages, read voltages or erased by the control logic circuit 330. A high voltage generator 340 for outputting a voltage or the like, and a switch block 350 for selectively applying the generated high voltage to each word line of the cell.

The main cell array 310 may input and output memory cells for storing data, word lines WL0, WL1,..., WLn for selecting and activating the memory cells, and data of the memory cells. It includes bit lines BL0, BL1, ..., BLm, and the plurality of word lines and the plurality of bit lines are arranged in a matrix form. The main cell array includes a plurality of strings in which the memory cells are connected in series, drain select transistors (DSLs) for selectively connecting a specific memory cell and a bit line, and selectively connecting a specific memory cell and a common source line. Source select transistors (SSL).

Gates of the memory cells are connected to word lines, and a set of memory cells commonly connected to the same word line is called a page. A plurality of strings connected to each bit line are connected in parallel to a common source line to form a block.

The page buffer 312 of the main cell will be described with reference to the drawings.

4 is a diagram illustrating a page buffer used in a nonvolatile memory device according to an embodiment of the present invention.

The nonvolatile memory device includes a memory cell array and a page buffer in which data is stored.

The page buffer may include a bit line selector 400 for selectively connecting a specific bit line BLe or BLo and a sensing node SO, a first register 410 and a second register 420 for storing specific data, And a data comparator 430 and a data input unit 440 for comparing the data stored in the first register 410 with the data stored in the second register 420 and transferring the data stored in the second register 420 to the sensing node SO.

The bit line selector 400 may include an NMOS transistor N406 connecting the even bit line BLe and the sensing node SO in response to a first bit line select signal BSLe, and an odd bit line select signal. And an NMOS transistor N408 connecting the odd bit line BLo and the sensing node SO in response to BSLo.

Therefore, according to the voltage level of the specific bit line selection signal BSLe or BSLo, the specific bit line and the sensing node are selectively connected.

In addition, the bit line selector 400 connects the even bit line BLe and the control signal input terminal in response to a control signal input terminal for applying a control signal VIRPWR of a specific level and an even discharge signal DISCHe. An NMOS transistor N102 and an NMOS transistor N404 connecting the odd bit line BLo and a control signal input terminal in response to the odd discharge signal DISCHo.

Therefore, the specific bit line is precharged to a high level or discharged to a low level according to the voltage level of the control signal.

The first register 410 includes a latch 412 including two inverters IV414 and IV416, an NMOS transistor N412 connected to the first node MSB of the latch, and a second node MSB_N of the latch. And an NMOS transistor N414 and an inverter IV412 connected to each other, and a PMOS transistor P412 that is turned on according to the voltage level of the second node and outputs a high level voltage Vdd as the MSB verification signal MSBVER_N. It also includes an NMOS transistor N416 connected between the connection node N4 of the NMOS transistors N412 and N414 and ground.

The NMOS transistor N412 is connected between the first node MSB and a connection node N4 and turned on in response to an MSB reset signal MSBRST, and the NMOS transistor N414 is connected to the second node MSB_N. It is connected between the connection nodes N4 and turned on in response to the MSB set signal MSBSET.

The NMOS transistor N416 is connected between the connection node N4 and ground, and is turned on according to the voltage level of the sensing node SO to supply a ground voltage to the connection node N4.

The second register 420 includes a latch 422 composed of two inverters IV424 and IV426, an NMOS transistor N422 connected to the first node LSB of the latch, and a second node LSB_N of the latch. And an NMOS transistor N424 and an inverter IV422 connected to each other, and a PMOS transistor P422 that is turned on according to the voltage level of the second node and outputs a high level voltage Vdd as a verification signal LSBVER_N. It also includes an NMOS transistor N426 connected between the connection node N9 of the NMOS transistors N422 and N424 and ground.

The NMOS transistor N422 is connected between the first node LSB and a connection node N9 to be turned on in response to an LSB reset signal LSBRST, and the NMOS transistor N424 is connected to the second node LSB_N. It is connected between the connection nodes N9 and turned on in response to the lower bit set signal LSBSET.

The NMOS transistor N426 is connected between the connection node N9 and ground, and is turned on according to the voltage level of the sensing node SO to supply a ground voltage to the connection node N9.

The data comparison unit 430 converts the logical product data of the data stored in the first register 410 and the data stored in the second register 420 to the sensing node SO in response to the higher bit program signal MSBPROG. To pass.

The data comparison unit 430 includes a first comparison circuit 432 and a second comparison circuit 434. The first comparison circuit 432 includes NMOS transistors N432 and N436. The NMOS transistors N432 and N436 are connected in series between the sensing node SO and the node N7. The NMOS transistor N432 is turned on in response to the higher bit program signal MSBPROG, and the NMOS transistor N436 is turned on in response to the potential of the node N12 to connect the sensing node SO and the node N7. Or disconnect.

The second comparison circuit 434 includes NMOS transistors N434 and N438. The NMOS transistors N434 and N438 are connected in series between the sensing node SO and the node N12. An NMOS transistor N434 is turned on in response to the higher bit program signal MSBPROG, and an NMOS transistor N438 is turned on in response to a potential of the node N7 so that the sensing node SO and the node N12 are turned on. Connect or disconnect.

In the operation of the data comparator 430, the high-level upper bit program signal MSBPROG is applied while the precharge transistor P450 is turned on for a predetermined time and the sensing node SO is precharged to a high level. Done. At this time, the voltage level of the sensing node SO varies according to the voltage levels of the node N7 of the first comparison circuit 432 and the node N12 of the second comparison circuit 434. same.

Comparison circuit operation N7 node potential N12 node potential Sense Node (SO) Potential N436, N438 TR Turn-on High High High N438 TR Turn On High Low Low N436 TR Turn On Low High Low N436, N438 TR Turn Off Low Low Precharge Level Maintenance

As shown in the table, whether the NMOS transistors N436 and N438 are turned on is determined according to the voltage levels of the node N7 of the first comparison circuit 432 and the node N12 of the second comparison circuit 434. It is determined whether the potential of the node affects the sensing node SO. However, when the potentials of both nodes are at the low level, both transistors are turned off to stop the AND-transmission of data. In this case, the potential of the sensing node SO is determined according to the precharged level.

The data input circuit 440 includes NMOS transistors N442 and N444. The NMOS transistor N442 is connected between the first node MSB and the input / output terminal YA and is turned on in response to the data input signal DATALOAD. When the NMOS transistor N442 is turned on, the data of the input / output terminal YA is transferred to the first node MSB of the first register 410. The NMOS transistor N444 is connected between the second node MSB_N and the input / output terminal YA and is turned on in response to an inverted data input signal DATALOAD_N. When the NMOS transistor N444 is turned on, the data of the input / output terminal YA is transferred to the second node MSB_N.

Therefore, when the high level input signal DATALOAD is applied while the input / output terminal YA is grounded, the NMOS transistor N442 is turned on so that the first node MSB becomes a low level. When the input signal DATALOAD_N is applied, the NMOS transistor N444 is turned on so that the second node MSB_N goes low and data is input.

On the other hand, data transfer transistors N456 and N458 are connected between the nodes N7 and N12 and the sensing node SO of each bit register. The NMOS transistor N456 is connected between the sensing node SO and the node N4 and is turned on in response to a data transmission signal DATTRAN. Therefore, when the NMOS transistor N456 is turned on, the data of the node N7 is transferred to the sensing node SO.

The NMOS transistor N458 is connected between the sensing node SO and the node N7 and is turned on in response to a low bit program signal LSBPROG. Therefore, when the NMOS transistor N458 is turned on, the data of the node N12 is transferred to the sensing node SO.

In addition, the precharge PMOS transistor P450 connected between the power supply voltage VDD and the sensing node SO is turned on in response to the low level precharge signal PRECH_N. When the PMOS transistor 450 is turned on, the power supply voltage VDD is applied to the sensing node SO, and the sensing node SO is precharged to the power supply voltage VDD level.

In addition, data pass transistors N450, N452, and N454 for transferring data applied to the nodes N7 and N12 to an external terminal are included.

The MSB pass element N452 is implemented as an NMOS transistor and is connected between the node N7 and the node N8 to operate in response to the MSB pass signal MSBPASS. The LSB pass element N454 is implemented as an NMOS transistor, and is connected between the node N12 and the node N8 to operate in response to the LSB pass signal LSBPASS. The data pass device N450 is implemented as an NMOS transistor and transfers the voltage applied to the node N8 to the inverter IV450 in response to the pass signal PASS.

However, the page buffer as described above is just one embodiment, and other types of page buffers may be used according to the present invention. In other words, a page buffer including three latches may be used to facilitate 3-bit MLC operation.

Next, the indicator cell array 320 will be described. The indicator cell is a characteristic component of the present invention and is used as a target of the verification in place of the main cell when verifying whether the main cell is programmed, and is used to determine whether the verification operation is completed based on a specific verification voltage. That is, the verification operation is performed on the indicator cell based on a specific verification voltage, and when the verification operation is completed, the verification operation based on the higher verification voltage is performed. Therefore, it includes a memory cell having the same characteristics as the memory cell included in the main cell, the configuration of the indicator cell block is configured in the same way as the main cell block.

That is, as shown in the dotted line of FIG. 3, the indicator cells include a plurality of strings connected in series, drain select transistors (DSLs) for selectively connecting a specific indicator cell and a bit line, and a common memory cell and a common source. Source select transistors SSL for selectively connecting a line.

Next, the indicator cell page buffer 322 will be described.

The indicator cell page buffer 322 temporarily stores data to be stored in the indicator cell or reads and temporarily stores data stored in an indicator setting. Therefore, the configuration is the same as the main cell page buffer 312 described above.

Meanwhile, the indicator cell page buffer 322 performs a verification operation based on a specific verification voltage and outputs a verification completion signal to the control logic circuit 330 when the verification operation is completed.

In order to look at the verification completion signal in more detail, refer to FIG. 4 again.

'0' or '1' data is stored in the second node MSB_N of the first register 410 according to externally input data. When '0' data is stored in the second node MSB_N, it is assumed to be a program object, and when '1' data is stored, it is an erase object.

Data stored in the second node MSB_N is applied to the bit line via the sensing node, and according to each data, the voltage applied to the bit line has a low level or a high level value, and according to the voltage applied to the bit line. The program operation proceeds.

On the other hand, when the verify operation is performed, the voltage level of the bit line varies depending on whether the program is programmed. If the cell is programmed above the verify voltage, the high level voltage is maintained. Otherwise, the bit line has a low level voltage. The voltage of the bit line is applied to the sensing node and it is determined whether the NMOS transistor N416 of the first resistor is turned on according to the voltage applied to the sensing node.

When the cell is programmed above the verify voltage, a high level voltage is applied to the sensing node to turn on the NMOS transistor N416 of the first resistor. Otherwise, a low level voltage is applied to the sensing node, and the NMOS transistor N416 of the first resistor is turned off.

Meanwhile, during the verify operation, a high level MSBRST signal is applied to the NMOS transistor N412 of the first register. Therefore, when the corresponding cell is programmed above the verify voltage, both of the NMOS transistors N412 and N416 are turned on and high level data, that is, '1' data is stored in the second node.

Meanwhile, when '0' data is stored in the second node as a cell to which the corresponding cell is programmed, the sensing node has a low level value when the corresponding cell is not programmed above the verify voltage. Therefore, the NMOS transistor N416 is not turned on, so that '0' data is maintained as it is.

Meanwhile, when '1' data is stored in the second node as a cell to be erased, the sensing node may have a low level value because the cell may not be programmed. Therefore, the NMOS transistor N416 is not turned on, so that '1' data is maintained as it is.

As a result, '0' data is stored in the second node only when the program is programmed but not programmed above the verify voltage.

In the case where all of the cells to be programmed are programmed above the verify voltage by repeatedly applying the program pulse, '1' data is stored in the second node MSB_N of each page buffer, which is applied to the gate of the PMOS transistor P412. Turning off the transistor causes the MSB verification signal MSBVER_N to float. This signal is applied to the control logic circuit 330.

Meanwhile, the verification operation as described above may be performed in the second register in the same manner, and the process of outputting the verification result LSB verification signal MSBVER_N is the same.

Now, the verification operation of the present invention will be described.

5 is a flowchart illustrating a multi-level cell program verification operation according to an embodiment of the present invention, and FIG. 6 is a circuit diagram illustrating an indicator cell and an indicator cell page buffer according to an embodiment of the present invention.

First, prior to the program operation, data to be programmed for the main cell array 310 is input to the main cell page buffer 312 (step 510).

Each cell is connected to the page buffer through a bit line. The data to be programmed for a particular cell is input to and stored in each register included in the page buffer.

Next, the data to be programmed for the indicator cell array 320 is input to the indicator cell page buffer 322 (step 520).

Referring to FIG. 6, the indicator cell block 320 includes a first cell 610 and a second verify voltage to perform a first verify operation based on a first verify voltage PV (i). A second cell 620 to perform a second verification operation based on (PV (i + 1)) and a third verification operation based on a third verification voltage PV (i + 2); The third cell 630 includes a fourth cell 640 to perform a fourth verification operation based on the fourth verification voltage PV (i + 3).

In this case, each cell may be configured of a plurality of cells. That is, a plurality of cells to which each verification operation is performed may be plural, and when one cell of the plurality of cells is programmed above the verification voltage, the verification operation based on the next verification voltage may be configured. That is, a first cell group includes a plurality of cells to perform a first verify operation, a second cell group includes a plurality of cells to perform a second verify operation, and a plurality of cells to perform a third verify operation. And a third cell group including a third cell group, a fourth cell group including a plurality of cells to perform a fourth verification operation, and the like.

In addition, the indicator cell page buffer 322 may include a first page buffer 612 for temporarily storing data to be input to the first cell 610 and a second temporarily storing data to be input to the second cell 620. A page buffer 622, a third page buffer 632 for temporarily storing data to be input to the third cell 630, and a fourth page buffer 642 for temporarily storing data to be input to the fourth cell 640 ).

Therefore, the first page buffer stores data for setting the threshold voltage of the indicator cell higher than the first verify voltage and lower than the second verify voltage in FIG. 2A, and the threshold voltage of the indicator cell is second verified in the second page buffer. Data for setting higher than the voltage and lower than the third verify voltage is stored.

The third page buffer stores data for setting the threshold voltage of the indicator cell higher than the third verify voltage and lower than the fourth verify voltage, and the fourth page buffer stores the threshold voltage of the indicator cell higher than the fourth verify voltage. The data that you set up is stored. Each page buffer outputs the above-mentioned verification completion signal when the corresponding cell is programmed above the verification voltage.

On the other hand, when each cell is configured in plural, a plurality of page buffer groups connected to each cell group are included. That is, a first page buffer group connected to the first cell group, a second page buffer group connected to the second cell group, a third page buffer group connected to the third cell group, and the fourth cell group; Fourth page buffer group to be connected is included.

Meanwhile, the illustrated example is based on a 3-bit multi-level cell program method, and the 2-bit multi-level cell program method is capable of verifying operations using only a few indicator cells. Preferably, when n-bit multi-level cell programs are desired, 2 ^ (n-1) indicator cells and an indicator page buffer are required.

Meanwhile, according to an exemplary embodiment, the fourth cell performing the fourth verification operation may not be included. This is because the fourth verify operation is the last operation, that is, since there is no fifth verify operation to proceed according to whether the fourth verify operation is completed, the completion of the verify operation by the fourth cell is not used.

7 is a circuit diagram illustrating an indicator cell and an indicator cell page buffer according to another embodiment of the present invention.

The indicator cell block 320 refers to the first cell 710 and the second verify voltage PV (i + 1) to perform the first verify operation based on the first verify voltage PV (i). And a second cell 720 to perform a second verify operation, and a third cell 730 to perform a third verify operation based on the third verify voltage PV (i + 2).

In addition, the indicator cell page buffer 322 may include a first page buffer 712 for temporarily storing data to be input to the first cell 610 and a second to temporarily store data to be input to the second cell 620. The page buffer 722 includes a third page buffer 732 that temporarily stores data to be input to the third cell 630.

Accordingly, data for setting the threshold voltage of the indicator cell to be higher than the first verify voltage and lower than the second verify voltage in FIG. 2A is stored in the first page buffer, and the threshold voltage of the indicator cell is stored in the second page buffer. Data that is set higher than the verify voltage and lower than the third verify voltage is stored.

The third page buffer also stores data for setting the threshold voltage of the indicator cell to be higher than the third verify voltage and lower than the fourth verify voltage.

In addition, as described above, when the cell and the page buffer which perform the last verification operation are not included, 2 ^ (n-1) -1 indicator cells and the indicator page buffer are required.

Next, referring again to FIG. 5, data input to each page buffer is applied to a bit line and a program operation is performed (step 530).

Not only the main cell but also the indicator cell, data input to each page buffer is applied to the bit line, and a program operation is performed. Since the main cell and the indicator cell are connected by the same word line, the same program voltage is applied.

Data stored in the page buffer is applied to each bit line, and the voltage level of the bit line becomes high level or low level according to the stored data. A program voltage is applied to a word line vertically connected to the bit line. The program voltage is applied only to a word line connected to a cell to be programmed, and a pass voltage of a lower level is applied to other word lines. Therefore, when the bit line of a particular cell is at a low level, when a program voltage is applied to the word line, the cell is programmed and other cells remain in the erased state.

On the other hand, the program voltage is repeatedly applied several times as the program voltage is increased by a certain amount according to the ISPP (Incremental Step Pulse Programming) method.

Now let's look at the verification operation.

First, a verification operation is performed based on the first verification voltage PV (i) (step 540).

In this case, the verifying operation is a process of determining whether the threshold voltage of the first cell 610 is greater than the first verifying voltage PV (i). To this end, while the bit line of the cell to be verified is precharged to a high level, the verify voltage PV (i) is applied to the word line and the pass voltage is applied to the word line.

Meanwhile, the verification operation is performed not only on the indicator cell but also on the main cell included in the same page. That is, the verify operation is performed on the main cell based on the first verify voltage.

If the cell is programmed, that is, if the threshold voltage of the cell is greater than the verify voltage PV (i), the cell is not turned on, so that no current path is formed in the cell string containing the cell, The voltage level is kept high.

However, if the cell is not programmed (either erased or programmed and not programmed), that is, if the threshold voltage of the cell is less than the verify voltage PV (i), the cell is turned on to include the cell. A current path is formed in the cell string, so that the voltage level of the bit line, which has been precharged to the high level, is transitioned to the low level. Since the voltage level of the bit line is different depending on whether it is programmed as described above, it is applied to the sensing node and stored in the register of the page buffer.

When the threshold voltage rises above the first verify voltage according to the verify operation, the process proceeds to the verify operation step based on the second verify voltage. Otherwise, the program operation (step 530) and the first verify operation are performed again. The operation is repeated sequentially (step 542).

On the other hand, when the threshold voltage of the first cell 610 does not rise above the first verification voltage, the high level signal MSBVER_N signal is output from the first page buffer 612, which is transmitted to the control logic circuit 330. Is entered. The control logic circuit 330 controls the high voltage generator 340 so that the first verification voltage is continuously applied to the word line.

However, when the threshold voltage of the first cell 610 rises above the first verify voltage, the verify completion signal MSBVER_N signal in the floating state is output from the first page buffer 612, which is transmitted to the control logic circuit 330. Is entered. The control logic circuit 330 controls the high voltage generator 340 to apply the second verification voltage to the word line. That is, the verify operation based on the second verify voltage is performed.

That is, unlike the usual case, after verifying that the first cell, which is the indicator cell, is programmed to be greater than or equal to the first verification voltage, the verification operation based on the second verification voltage is performed.

Next, a verification operation is performed based on the second verification voltage PV (i + 1) (step 550).

In this case, the verifying operation is a process of determining whether the threshold voltage of the second cell 620 is greater than the second verifying voltage PV (i + 1). To this end, while the bit line of the cell to be verified is precharged to a high level, a verification voltage PV (i + 1) is applied to the word line and a pass voltage is applied to the word line.

Meanwhile, the verification operation is performed not only on the indicator cell but also on the main cell included in the same page. That is, the verify operation is performed on the main cell based on the second verify voltage.

If the cell is programmed, that is, if the threshold voltage of the cell is greater than the verify voltage PV (i + 1), the cell is not turned on, so no current path is formed in the cell string that contains the cell. The voltage level of the line is kept high.

However, if the cell is not programmed (either erased or programmed and not programmed), that is, if the threshold voltage of the cell is less than the verify voltage PV (i + 1), the cell is turned on and A current path is formed in the included cell string, and accordingly, the voltage level of the bit line which has been precharged to the high level is shifted to the low level. Since the voltage level of the bit line is different depending on whether it is programmed as above, it is applied to the sensing node and stored in the register of the page buffer.

When the threshold voltage rises above the second verification voltage according to the verification operation, the process proceeds to the verification operation based on the third verification voltage. Otherwise, the program operation 530, the first verification operation and The second verification operation is repeatedly performed sequentially (step 552).

On the other hand, when the threshold voltage of the second cell 620 does not rise above the second verification voltage, the high level signal MSBVER_N signal is output from the second page buffer 622, which is sent to the control logic circuit 330. Is entered. The control logic circuit 330 controls the high voltage generator 340 so that the second verification voltage is continuously applied to the word line.

However, when the threshold voltage of the second cell 620 rises above the second verify voltage, the verify completion signal MSBVER_N signal in the floating state is output from the second page buffer 622 to the control logic circuit 330. Is entered. The control logic circuit 330 controls the high voltage generator 340 to apply the third verification voltage to the word line. That is, the verify operation based on the third verify voltage is performed.

Next, a verification operation is performed based on the third verification voltage PV (i + 2) (step 560).

In this case, the verifying operation is a process of determining whether the threshold voltage of the third cell 630 is greater than the third verifying voltage PV (i + 2). To this end, while the bit line of the cell to be verified is precharged to a high level, a verify voltage PV (i + 2) is applied to the word line and a pass voltage is applied to the word line.

Meanwhile, the verification operation is performed not only on the indicator cell but also on the main cell included in the same page. That is, the verify operation is performed on the main cell based on the third verify voltage.

If the cell is programmed, that is, if the threshold voltage of the cell is greater than the verify voltage PV (i + 2), the cell is not turned on, so that no current path is formed in the cell string that contains the cell. The voltage level of the line is kept high.

However, if the cell is not programmed (either erased or programmed and not programmed), that is, if the threshold voltage of the cell is less than the verify voltage PV (i + 2), the cell is turned on and A current path is formed in the included cell string, and accordingly, the voltage level of the bit line which has been precharged to the high level is shifted to the low level. Since the voltage level of the bit line is different depending on whether it is programmed as above, it is applied to the sensing node and stored in the register of the page buffer.

When the threshold voltage rises above the third verify voltage according to the verify operation, the process proceeds to the verify operation based on the fourth verify voltage. Otherwise, the program operation 530, the first verify operation, The second verify operation and the third verify operation are sequentially repeated (step 562).

On the other hand, when the threshold voltage of the third cell 630 does not rise above the third verification voltage, the high level signal MSBVER_N signal is output from the third page buffer 632, which is transmitted to the control logic circuit 330. Is entered. The control logic circuit 330 controls the high voltage generator 340 so that the third verification voltage is continuously applied to the word line.

However, when the threshold voltage of the third cell 630 rises above the third verify voltage, the verify completion signal MSBVER_N signal in the floating state is output from the third page buffer 632, which is transmitted to the control logic circuit 330. Is entered. The control logic circuit 330 controls the high voltage generator 340 to apply the fourth verification voltage to the word line. That is, the verification operation based on the fourth verification voltage is performed.

Next, a verification operation is performed based on the fourth verification voltage PV (i + 3) (step 570).

In this case, the verifying operation is a process of determining whether the threshold voltage of the fourth cell 640 is greater than the fourth verifying voltage PV (i + 3). To this end, while the bit line of the cell to be verified is precharged to a high level, a verify voltage PV (i + 3) is applied to the word line and a pass voltage is applied to the word line.

Meanwhile, the verification operation is performed not only on the indicator cell but also on the main cell included in the same page. That is, the verify operation is performed on the main cell based on the fourth verify voltage.

If the cell is programmed, that is, if the threshold voltage of the cell is greater than the verification voltage PV (i + 3), the cell is not turned on, so that no current path is formed in the cell string that contains the cell. The voltage level of the line is kept high.

However, if the cell is not programmed (either erased or programmed and not programmed), that is, if the threshold voltage of the cell is less than the verify voltage PV (i + 3), the cell is turned on and A current path is formed in the included cell string, and accordingly, the voltage level of the bit line which has been precharged to the high level is shifted to the low level. Since the voltage level of the bit line is different depending on whether it is programmed as described above, it is applied to the sensing node and stored in the register of the page buffer.

The program operation is completed only when the threshold voltage rises above the fourth verify voltage according to the verify operation (574). Otherwise, the program operation is performed again (530), the first verify operation, the second verify operation, The third verify operation and the fourth verify operation are sequentially repeated (step 572).

On the other hand, when the threshold voltage of the fourth cell 640 does not rise above the fourth verification voltage, the high level signal MSBVER_N signal is output from the fourth page buffer 642, which is sent to the control logic circuit 330. Is entered. The control logic circuit 330 controls the high voltage generator 340 so that the fourth verification voltage is continuously applied to the word line.

However, when the threshold voltage of the fourth cell 630 rises above the fourth verify voltage, the verify completion signal MSBVER_N signal in the floating state is output from the fourth page buffer 642 to the control logic circuit 330. Is entered. The control logic circuit 330 controls the high voltage generator 340 to stop the application of the program voltage.

Meanwhile, when the indicator cell and the indicator cell page buffer which perform the last verification operation are not included as shown in the embodiment of FIG. 7, the fourth verification operation performed by the indicator cell may not be performed. However, this is merely that the fourth verification operation performed in the indicator cell is not performed, and the fourth verification operation performed in the main cell is normally performed.

As described above, the verification operation is performed based on the threshold voltage of the indicator cell, and the verification operation is performed based on the higher verification voltage only when the indicator cell is programmed above the specific verification voltage.

Now, a program voltage and a verify voltage application waveform according to an embodiment of the present invention will be described.

FIG. 8A is a waveform diagram illustrating a program voltage and a verify voltage applied when programming a 2-bit multi-level cell. FIG. 8B is a waveform diagram illustrating a program voltage and verify voltage applied when programming a 3-bit multi-level cell. FIG. 8C. Is a waveform diagram showing a program voltage and a verification voltage applied when a 4-bit multi-level cell is programmed.

Referring to FIG. 8A, in the 2-bit multi-level cell program method, a verify operation is performed at the first verify voltage PV1 and the second verify voltage PV3. However, according to the present invention, the verification operation by the second verification voltage is performed only when the indicator cell is programmed to be greater than or equal to the first verification voltage PV1. Meanwhile, the verification by the first verification voltage and the verification by the second verification voltage are performed, but when verification by the first verification voltage is completed, only verification by the second verification voltage is performed.

Referring to FIG. 8B, in the 3-bit multi-level cell program method, verification operations are performed on the first verify voltage PV1, the second verify voltage PV3, the third verify voltage PV5, and the fourth verify voltage PV7. This is done. However, according to the present invention, the verification operation by the second verification voltage is performed only when the indicator cell is programmed to be greater than or equal to the first verification voltage PV1. Similarly, the verification operation by the third verification voltage is performed only when the indicator cell is programmed to be greater than or equal to the second verification voltage PV3, and the fourth verification is performed when the indicator cell is programmed to be greater than or equal to the third verification voltage PV1. Verification by the verification voltage is performed.

Referring to FIG. 8C, in the case of a 4-bit multi-level cell programming method, a first verify voltage PV1, a second verify voltage PV3, a third verify voltage PV5, a fourth verify voltage PV7, and a fifth verify The verification operation is performed on the voltage PV9, the sixth verification voltage PV11, the seventh verification voltage PV13, and the eighth verification voltage PV15. However, according to the present invention, the verification operation by the second verification voltage is performed only when the indicator cell is programmed to be greater than or equal to the first verification voltage PV1. Similarly, the verification operation by the third verification voltage is performed only when the indicator cell is programmed to be greater than or equal to the second verification voltage PV3, and the fourth verification is performed when the indicator cell is programmed to be greater than or equal to the third verification voltage PV1. Verification by the verification voltage is performed. In addition, the verification operation by the fifth verification voltage is performed only when the indicator cell is programmed to be greater than or equal to the fourth verification voltage, and the verification operation by the sixth verification voltage is only performed when the indicator cell is programmed to be greater than or equal to the fifth verification voltage. Is performed, and the verification operation by the seventh verification voltage is performed only when the indicator cell is programmed to be greater than or equal to the sixth verification voltage, and the verification operation by the eighth verification voltage is performed only when the indicator cell is programmed by more than the seventh verification voltage. Verification is performed.

1A to 1D are diagrams illustrating threshold voltage distribution by a multi-level cell program.

2A is a diagram illustrating a distribution of threshold voltages by a 3-bit multi-level cell program. 2B is a flow chart illustrating a typical verify operation for the 3-bit multi-level cell program.

FIG. 2C is a waveform diagram illustrating a program voltage and a verification voltage that are typically applied when programming a 3 bit multi-level cell. FIG. 3 is a circuit diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a page buffer used in a nonvolatile memory device according to an embodiment of the present invention.

5 is a flowchart illustrating a multi-level cell program verify operation according to an embodiment of the present invention.

6 is a circuit diagram illustrating an indicator cell and an indicator cell page buffer according to an embodiment of the present invention.

7 is a circuit diagram illustrating an indicator cell and an indicator cell page buffer according to another embodiment of the present invention.

8A is a waveform diagram illustrating a program voltage and a verify voltage applied when a 2-bit multi-level cell is programmed.

8B is a waveform diagram illustrating a program voltage and a verify voltage applied when a 3-bit multi-level cell is programmed.

8C is a waveform diagram illustrating a program voltage and a verify voltage applied when a 4-bit multi-level cell is programmed.

Description of the main parts of the drawing

310: main cell array 312: main cell page buffer

320: indicator cell array 322: indicator cell page buffer

330: control logic circuit 340: high voltage generator

350: switch block

Claims (22)

Applying different data for each cell so that different threshold voltages are set for a plurality of main cells and indicator cells; Performing a program operation on the main cell and the indicator cell; Performing a first verify operation on the main cell and the indicator cell based on a first verify voltage; Sequentially repeating the program operation and the first verify operation until the threshold voltage of the first cell among the indicator cells is greater than the first verify voltage; And performing a second verify operation on the main cell based on a second verify voltage when the threshold voltage of the first cell is greater than the first verify voltage. Program method. The method of claim 1, further comprising sequentially repeating the program operation, the first verify operation, and the second verify operation until the second verify operation is completed with respect to the main cell. A multi-level cell program method of a nonvolatile memory device. 3. The nonvolatile memory device of claim 2, wherein the repetitively performing the step comprises stopping performing the first verify operation when the first verify operation is completed with respect to the main cell. 4. Multi-level cell programming method. The method of claim 1, wherein the performing of the first verify operation includes applying a first verify voltage to a word line of a first cell to which data is applied such that a threshold voltage is higher than the first verify voltage and lower than a second verify voltage. And performing the verify operation. The method of claim 1, wherein the performing of the second verify operation comprises applying a second verify voltage to a word line of a second cell to which data is applied so that a threshold voltage is higher than the second verify voltage. A multi-level cell program method of a nonvolatile memory device, characterized in that. The multi-level cell program method of claim 1, wherein the performing of the program operation comprises applying a program voltage by increasing a predetermined level whenever the program operation is repeated. A plurality of indicator cells which are subject to verification when verifying whether the main cell is programmed; An indicator cell page buffer for outputting a verification completion signal depending on whether the indicator cell is programmed; And a control logic circuit configured to change a verification voltage supply condition by controlling a high voltage generator according to the verification completion signal. 8. The nonvolatile memory device of claim 7, wherein at least two indicator cells are included in an N-bit multi-level cell program operation. 8. The method of claim 7, wherein the indicator cell comprises a first cell in which data for setting the threshold voltage is higher than the first verify voltage and lower than the second verify voltage when the 2-bit multi-level cell program scheme is applied. Nonvolatile memory device, characterized in that. The method of claim 7, wherein the indicator cell comprises: a first cell in which data for setting a threshold voltage higher than a first verify voltage and lower than a second verify voltage when a 3-bit multi-level cell program scheme is applied; A second cell storing data for setting a threshold voltage higher than the second verify voltage and lower than a third verify voltage; And a third cell configured to store data for setting a threshold voltage higher than the third verify voltage and lower than a fourth verify voltage. 8. The method of claim 7, wherein the indicator cell includes a plurality of cells that store data for setting a threshold voltage higher than the first verify voltage and lower than the second verify voltage when the 2-bit multi-level cell program method is applied. A nonvolatile memory device comprising one cell group. 8. The method of claim 7, wherein the indicator cell includes a plurality of cells that store data for setting a threshold voltage higher than a first verify voltage and lower than a second verify voltage when a 3-bit multi-level cell program scheme is applied. 1 cell group, A second cell group including a plurality of cells storing data for setting a threshold voltage higher than the second verify voltage and lower than a third verify voltage; And a third cell group including a plurality of cells storing data for setting a threshold voltage higher than the third verify voltage and lower than a fourth verify voltage. The nonvolatile memory device of claim 9, further comprising a first cell page buffer configured to output a first verify completion signal according to whether the first cell is programmed. The method of claim 10, further comprising: a first cell page buffer configured to output a first verify completion signal according to whether the first cell is programmed; A second cell page buffer configured to output a second verify completion signal according to whether the second cell is programmed; And a third cell page buffer configured to output a third verify completion signal according to whether the third cell is programmed. The nonvolatile memory device of claim 11, further comprising a first cell page buffer group configured to output a first verify completion signal according to whether the first cell group is programmed. The method of claim 12, wherein the first cell page buffer group outputs a first verify completion signal according to whether the first cell group is programmed; A second cell page buffer group for outputting a second verify completion signal according to whether the second cell group is programmed; And a third cell page buffer group configured to output a third verify completion signal according to whether the third cell group is programmed. 15. The nonvolatile memory device of claim 13 or 14, wherein the control logic circuit is configured to apply an n + 1 verify voltage when an n-th verify completion signal is input. The nonvolatile memory device of claim 15, wherein the control logic circuit is configured to apply an n + 1 verification voltage when one or more n-th verification completion signals are input. The nonvolatile memory device of claim 15, wherein the control logic circuit is configured to apply an n + 1 verification voltage when the nth verification completion signal is input to a predetermined number or more. Applying different data for each cell so that different threshold voltages are set for a plurality of main cells and indicator cells; Performing a program operation on the main cell and the indicator cell; Performing a first verify operation on the main cell and the indicator cell based on a first verify voltage; Sequentially repeating the program operation and the first verify operation until the threshold voltage of the first cell among the indicator cells is greater than the first verify voltage; Performing a second verify operation on the main cell and the indicator cell based on a second verify voltage when the threshold voltage of the first cell is greater than the first verify voltage; Sequentially repeating the program operation, the first verifying operation, and the second verifying operation until the threshold voltage of a second cell of the indicator cells is greater than the second verifying voltage; Performing a third verify operation on the main cell and the indicator cell based on a third verify voltage when the threshold voltage of the second cell is greater than the second verify voltage; Sequentially repeating the program operation, the first verify operation, the second verify operation, and the third verify operation until the threshold voltage of the third cell among the indicator cells is greater than the third verify voltage; And performing a fourth verify operation on the main cell based on a fourth verify voltage when the threshold voltage of the third cell is greater than the third verify voltage. Program method. The method of claim 20, wherein the program operation, the first verify operation, the second verify operation, the third verify operation, and the fourth verify operation are sequentially performed until the fourth verify operation is completed with respect to the main cell. And repeatedly performing a repeating step. 22. The method of claim 21, wherein the step of performing the repetition sequentially comprises stopping the performing of the completed verify operation when the first verify operation, the second verify operation, or the third verify operation is completed with respect to the main cell. And a multi-level cell program method of a nonvolatile memory device.

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