KR20110111218A - On-die termination circuit, data output buffer, semiconductor memory device - Google Patents

Abstract

An on-die termination (ODT) circuit of a semiconductor memory device includes a termination resistor and a termination controller. The termination resistor is connected to an external pin and provides a termination resistor to a transmission line connected to the external pin. The termination controller is connected to the termination resistor and varies the resistance of the termination resistor in response to a plurality of bits of strength code reflecting the data rate.

Description

ON-DIE TERMINATION CIRCUIT, DATA OUTPUT BUFFER, SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to on-die termination, and more particularly to an on-die termination circuit, a data output buffer, a semiconductor memory device.

On-die termination (OTT) has been introduced to improve signal integrity by minimizing signal reflection at the interface between the memory controller and the semiconductor memory device. The ODT circuit can suppress signal reflection by providing a termination resistor (RTT) that matches the impedance of the transmission line.

As operating voltages decrease, there is a need to reduce power consumption in these ODT circuits.

One object of the present invention to solve the above problems is to provide an on-die termination circuit that can reduce power consumption.

Another object of the present invention is to provide a data output buffer which can reduce power consumption.

Another object of the present invention is to provide a semiconductor memory device including the data output buffer.

In order to achieve the above object, an on-die termination (OTT) circuit of a semiconductor memory device includes a termination resistor and a termination controller. The termination resistor is connected to an external pin and provides a termination resistor to a transmission line connected to the external pin. The termination controller is connected to the termination resistor and varies the resistance of the termination resistor in response to a plurality of bits of strength code reflecting the data rate.

In one embodiment, the termination controller may decrease the resistance value of the termination resistor as the data rate is higher, and increase the resistance value of the termination resistor as the data rate is decreased.

In one embodiment, the termination controller may generate a plurality of bit termination control signals that are activated in response to the strength code and the output enable signal. A plurality of transistors each of which is connected to a power supply voltage and turned on in response to each bit of the termination control signal; And a plurality of resistors connected between each of the plurality of transistors and the external pin.

An on-die termination circuit according to another embodiment of the present invention for achieving the above object includes a terminating portion and an adjusting portion. The termination is connected between a supply voltage having a fixed voltage level and an adjustment node connected to an external pin and provides a termination resistor to a channel connected to the external pin in response to a plurality of bits of digital control code. The adjusting unit is connected to the adjusting node, and changes the bit value of the digital control code based on a result of comparing the voltage of the adjusting node with a reference voltage so that the termination resistor is matched with an external resistor connected to the external pin. do.

The terminal may include a plurality of PMOS transistors connected between the power supply voltage and the adjustment node, and each bit of the digital control code may be applied to a gate of the PMOS transistors.

In order to achieve the above another object, the data output buffer of the semiconductor memory device includes a driver and a controller. The driver is connected to an external pin and provides a driver impedance to the transmission line while performing a driver operation for providing read data to a memory controller through a transmission line connected to the external pin. The control unit is connected to the driving unit, and controls the driving unit to perform the driver operation in response to an output enable signal, the driving control signal for controlling the driving unit by combining the strength code reflecting the read data and the data rate Create The driver impedance is varied according to the strength code.

In one embodiment, the output enable signal is activated in a read mode, and the controller combines the read data and the strength code to generate a pull-up driving control signal and a pull-down driving control signal, and output the The pull-up driving control signal and the pull-down driving control signal may be provided to the driver in response to the enable signal.

The driving unit is connected between a power supply voltage and the external pin, the pull-up driver for receiving the pull-up driving control signal from the control unit; And a pull-down driver connected between a ground voltage and the external pin and receiving the pull-down driving control signal from the controller.

The power supply voltage may be 0.2V.

In order to achieve the above another object, the semiconductor memory device includes a memory core and a data output buffer. The memory core stores data and generates read data based on the stored data. The data output buffer outputs the read data provided from the memory core to a memory controller through an external pin and provides a variable driver impedance in response to a plurality of bits of strength code reflecting a data rate on the transmission line in a read mode. .

According to embodiments of the present invention, it is possible to reduce the current consumption by providing a termination resistor or a driver impedance that varies according to the data rate.

1 is a block diagram illustrating an on-die termination (ODT) circuit according to an embodiment of the present invention.
2A and 2B illustrate a strength code providing circuit according to embodiments of the present invention.
3 is a circuit diagram illustrating an example of the ODT circuit of FIG. 1.
4 is a block diagram illustrating a data output buffer according to an embodiment of the present invention.
5 is a block diagram illustrating a data output buffer of FIG. 4.
FIG. 6 is a circuit diagram illustrating the data output buffer of FIG. 5.
7 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
8 is a block diagram illustrating an ODT circuit according to another embodiment of the present invention.
FIG. 9 is a circuit diagram illustrating the ODT circuit of FIG. 8.
10 is a block diagram illustrating an off-chip driver (OCD) according to an embodiment of the present invention.
FIG. 11 is a circuit diagram illustrating the OCD of FIG. 10.
12 is a block diagram illustrating a memory module according to an example embodiment.
13A to 13F illustrate examples of a memory module according to example embodiments.
14 is a diagram illustrating a memory system according to an embodiment of the present invention.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may exist in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same or similar reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

1 is a block diagram illustrating an on-die termination (ODT) circuit according to an embodiment of the present invention.

Referring to FIG. 1, the ODT circuit 100 includes a termination controller 110 and a termination resistor 120.

The terminating resistor 120 is connected to the external pin 210. The terminating resistor unit 120 provides a terminating resistor to a transmission line connected to the external pin 210. The external pin 210 may be a data input / output pin, a data strobe pin, a data mask pin, a termination data strobe pin, or the like. Here, the term “pin” broadly refers to an electrical interconnection to an integrated circuit and includes, for example, a pad or other electrical contact point on the integrated circuit.

The termination resistor 120 may perform a pull-up termination operation for providing the termination resistor connected between the power supply voltage and the external pin 210. When the terminating resistor unit 120 performs the pull-up termination operation, the voltage of the transmission line connected to the external pin may be maintained as a power supply voltage. Accordingly, since a current flows in the termination resistor 120 and the transmission line only when data having a low level is transmitted to the transmission line, the termination resistor 120 performing the pull-up termination operation may include an ODT circuit. Compared to the conventional center termination operation in which a current path is formed to consume DC current, power consumption can be reduced.

The termination controller 110 is connected to the termination resistor 120. The termination controller 110 varies the resistance value of the termination resistor in response to a plurality of bits of strength code SCD reflecting a data rate. The data rate refers to a toggle rate of data input to the semiconductor memory device through an operating frequency of the semiconductor memory device including the ODT circuit 100 or an external pin 210. In addition, a plurality of bits of strength (Tm) code SCD may be input from the memory controller through a control pin. For example, the control pin may be an ODT pin. In addition, the strength code CD may be generated in a semiconductor memory device (eg, EMRS) including the ODT circuit 100.

The termination controller 110 may generate an termination control signal TCS for controlling the termination resistor 120 based on the strength code SCD and the output enable signal OEN. The output enable signal OEN may be activated in a read mode in which data is output through a transmission line connected to the external pin 210. When the output enable signal OEN is activated, the termination controller 110 may generate an termination control signal TCS that controls the termination resistor 120 so as not to provide the termination resistor. For example, the termination controller 110 generates an termination control signal TCS having a predetermined logic level in response to the activated output enable signal OEN, and the termination resistor 120 generates the predetermined logic level. The termination resistor and the external pin 210 may be disconnected in response to the termination control signal TCS.

When the output enable signal OEN is deactivated, the termination controller 110 may generate an termination control signal TCS for controlling the termination resistor 120 to provide the termination resistor. In addition, the termination controller 110 may change the logic level of the termination control signal TCS to vary the resistance value of the termination resistor in response to the strength code TCS. For example, when the strength code TCS indicates that the operating frequency is in the first range, the terminating resistor unit 120 may be controlled to provide a terminating resistor having a first resistance value in response to the terminating control signal TCS. Can be. In addition, when the strength code TCS indicates that the operating frequency is in the first range, the terminating resistor unit 120 may be controlled to provide a terminating resistor having a second resistance value in response to the terminating control signal TCS. . Here, when the first range is faster than the second range, the first resistance value may be smaller than the second resistance value.

2A and 2B illustrate a strength code providing circuit according to embodiments of the present invention.

Referring to FIG. 2A, the strength code providing circuit 10 may be implemented with an extended mode register set (EMRS). The EMRS 10 receives data rate information DRI, that is, an operating frequency FOP, and provides a plurality of bits of strength code SCD according to the operating frequency FOP. The EMRS 10 may be included in a semiconductor memory device or may be included in a memory controller external to the semiconductor memory device.

Referring to FIG. 2B, the strength code providing circuit 20 may include a plurality of comparators 21, 22, and 23. The comparator 21 compares the operating frequency FOP and the first reference frequency FR1 and outputs the first strength code SCD1 according to the result. The comparator 22 compares the operating frequency FOP and the second reference frequency FR2 and outputs a second strength code SCD2 according to the result. The comparator 23 compares the operating frequency FOP and the third reference frequency FR3 and outputs a third strength code SCD3 according to the result. For example, when the first reference frequency FR1 is lower than the second reference frequency FR2 and the second reference frequency FR2 is lower than the third frequency FR3, the operating frequency FOP is the first reference frequency FR1. ) And SCD1 may be at a low level, SCD2 is at a high level, and SCD3 may be at a high level. That is, the strength code SCD may be. In addition, when the operating frequency FOP is between the second reference frequency FR2 and the third reference frequency FR3, the strength code SCD may be [001]. In addition, if the operating frequency is higher than the third reference frequency FR3, the strength code SCD may be [000].

3 is a circuit diagram illustrating an example of the ODT circuit of FIG. 1.

Referring to FIG. 3, the termination controller 110 may include a first selector 111, a second selector 112, and a third selector 113. The first selector 111, the second selector 112, and the third selector 113 may each be implemented as a multiplexer. The termination resistor 120 is connected to the external pin 210 and has a first transistor 121, a first resistor R1, a second transistor 122, a second resistor R2, a third transistor 123, and the like. It may include a third resistor (R3).

The first selector 111 includes a first input terminal connected to a power supply voltage VDDQ, a second input terminal connected to a ground voltage VSSQ, a selection terminal to which an output enable signal OEN is applied, and a first termination control signal. It may have an output terminal from which TCS1 is output. The first selector 111 may selectively output the power supply voltage VDDQ or the first strength code SCD1 as the first termination control signal TCS1 in response to the output enable signal OEN.

The first transistor 121 may have a source connected to the power supply voltage VDDQ, a gate connected to the output terminal of the first selector 111, and a drain connected to the first resistor R1. The first resistor R1 may be connected between the first transistor 121 and the external pin 210. The first transistor 121 may be turned on / off in response to the first termination control signal TCS1, and the first resistor R1 may be connected to the external pin 210 according to the on / off state of the first transistor 121. Can be electrically connected to or disconnected from.

The second selector 112 includes a first input terminal connected to a power supply voltage VDDQ, a second input terminal connected to a ground voltage VSSQ, a selection terminal to which an output enable signal OEN is applied, and a second termination control signal. (TCS2) may have an output terminal output. The third selector 112 may selectively output the power supply voltage VDDQ or the second strength code SCD2 as the second termination control signal TCS2 in response to the output enable signal OEN.

The second transistor 122 may have a source connected to the power supply voltage VDDQ, a gate connected to the output terminal of the second selector 112, and a drain connected to the second resistor R2. The second resistor R2 may be connected between the second transistor 122 and the external pin 210. The second transistor 122 may be turned on / off in response to the second termination control signal TCS2, and the second resistor R2 may be external pin 210 according to the on / off state of the second transistor 122. Can be electrically connected to or disconnected from.

The third selector 113 includes a first input terminal connected to a power supply voltage VDDQ, a second input terminal connected to a ground voltage VSSQ, a selection terminal to which an output enable signal OEN is applied, and a third termination control signal. It may have an output terminal through which TCS3 is output. The third selector 113 may selectively output the power supply voltage VDDQ or the third strength code SCD3 as the third termination control signal TCS3 in response to the output enable signal OEN.

The third transistor 123 may have a source connected to the power supply voltage VDDQ, a gate connected to the output terminal of the third selector 113, and a drain connected to the second resistor R2. The third resistor R3 may be connected between the third transistor 123 and the external pin 210. The third transistor 123 may be turned on / off in response to the third termination control signal TCS3, and the third resistor R3 may be external pin 210 according to the on / off state of the third transistor 123. Can be electrically connected to or disconnected from.

When the output enable signal OEN is activated in a read mode in which data is output through a transmission line connected to the external pin 210, the first selector 111 is a power supply voltage as the first termination control signal TCS1. Outputs the VDDQ, the second selector 112 outputs the power supply voltage VDDQ as the second termination control signal TCS2, and the third selector 113 outputs the power supply voltage as the third termination control signal TCS2. Outputs (VDDQ). The first to third transistors 121, 122, and 123 are turned off in response to the first to third termination control signals TCS1, TCS2, and TCS3 having logic high levels, respectively. The first to third resistors R1, R2, and R3 may be electrically disconnected from the external pin 210 by the first to third transistors 121, 122, and 123 turned off, respectively. Accordingly, the ODT circuit 100 may not perform the termination operation in the read mode.

When the output enable signal OEN is deactivated, the first to third selectors 111, 112, and 113 are first to third strengths as the first to third termination control signals TCS1, TCS2, and TCS3, respectively. Output the codes SCD1, SCD2, SCD3. The first to third transistors 121, 122, and 123 are turned on / off according to logic levels of the first to third strength codes SCD1, SCD2, and SCD3, respectively. The first to third resistors R1, R2, and R3 are electrically connected to / from the external pin 210 by the first to third transistors 121, 122, and 123 turned on / off, respectively. Can be blocked.

For example, when the strength code SCD is turned on, only the first transistor 121 is turned on and only the first resistor R1 is electrically connected to the external pin 210. Accordingly, the termination resistor unit 120 may provide a termination resistor composed of the first resistor R1. For example, when the strength code is [001], the first transistor 121 and the second transistor 122 are turned on, and the first resistor R1 and the second resistor R2 are electrically connected to the external pin 210. Is connected. Accordingly, the termination resistor unit 120 may provide a termination resistor including the first resistor R1 and the second resistor R2 connected in parallel. For example, when the strength code is [000], the first to third transistors 121, 122, and 123 are turned on and the first to third resistors R1, R2, and R3 are electrically connected to the external pin 210. Is connected. Accordingly, the termination resistor unit 120 may provide a termination resistor including first to third resistors R1, R2, and R3 connected in parallel. The first and second resistors R1 and R2 may have substantially the same resistance values, and the third resistor R3 may have a resistance value that is half of the second resistance. For example, each of the first resistor R1 and the second resistor R2 may have a resistance value of about 200 Ω, and the third resistor R3 may have a resistance value of about 100 200 Ω. In this case, when the strength code SCD is [011], the termination resistor may have a resistance value of about 200 Ω, and when the strength code SCD is [001], the termination resistor may have a resistance value of about 100 Ω. When the strength code SCD is [000], the termination resistor may have a resistance value of about 50 Ω.

In FIG. 2, each of the first to third resistors R1, R2, and R3 is illustrated as a single resistor, but in some embodiments, each of the first to third resistors R1, R2, and R3 may be connected in parallel. And resistors for controlling the connection of the resistors and the connection of the resistors.

As described above, the strength code SCD reflects a data rate or an operating frequency (FOP, data toggle rate), so that the data rate is high (that is, the strength code SCD is [000]). ) Can charge and discharge the channel quickly. In addition, when the data rate is low (that is, when the strength code (SCD) is low), the termination resistance may be increased to reduce the DC current flowing along the channel to reduce current consumption.

4 is a block diagram illustrating a data output buffer according to an embodiment of the present invention.

Referring to FIG. 4, the data output buffer 300 includes a controller 310 and a driver 350.

The driver 350 is connected to the external pin 210. The driver 350 provides a driver impedance to the transmission line while performing a driver operation for providing read data DOUT to the memory controller through a transmission line connected to the external pin 210. The external pins 210 may be input / output data input / output pins, data strobe pins, or the like. The driver 1120 may perform a pull-up termination operation as the termination operation.

The control unit 310 is connected to the driving unit 350. The controller 310 controls the driving unit 350 to perform the driving operation in response to the output enable signal OEN, and combines the read data DOUT and the strength code SCDI reflecting the data rate to the driving unit 350. Generates a driving control signal (DCS) to control. The driver impedance is varied according to the strength code (SCDI).

5 is a block diagram illustrating a data output buffer of FIG. 4.

Referring to FIG. 5, the data output buffer 300 includes a controller 310 and a driver 320. The controller 310 includes a pre-driver 320 and a driving controller 330. The driver 350 includes a pull-up driver 360 and a pull-down driver 370.

The pre-driver 320 may receive the read data DOUT from the memory core, invert the read data DOUT, and provide the inverted read data DOUTB to the driving controller 330. The driving control unit 330 combines the read data DOUT, the strength code SCDI, and the read data DOUT to generate a pull-up driving control signal PUDCS, and inverts the read data DOUTB and the strength code. SCDI) combines to generate a pull-down driving control signal PDDCS, and generates a pull-up driving control signal PUDCS and a pull-down driving control signal PDDCS in response to the output enable signal OEN. 350).

While the pull-up driver 360 performs a driving operation in response to the pull-up driving control signal PUDCS, a resistance value is changed according to the pull-up driving control signal PUDCS on a transmission line connected to the external pin 201. Provides pull-up driver impedance. While the pull-down driver 370 performs a driving operation in response to the pull-down driving control signal PDDCS, a resistance value is changed according to the pull-down driving control signal PDDCS on a transmission line connected to the external pin 210. Provides a pull-down driver impedance.

FIG. 6 is a circuit diagram illustrating the data output buffer of FIG. 5.

Referring to FIG. 6, the pre-driver 320 may include an inverter 321. The driving controller 330 may include first to third NAND gates 331 to 333, first to third selectors 334 to 336, first to third end gates 341 to 343, and fourth to third. Sixth selectors 344 ˜ 346 may be included. The pull-up driver 360 may include first to third PMOS transistors 361 to 363 and first to third resistors R1, R2, and R3. The first to third PMOS transistors 361 to 363 are connected to a power supply voltage VDDQ, and the first to third resistors R1, R2, and R3 are first to third PMOS transistors 361, respectively. 363) is connected between each of the external pins 210. The pull-down driver 370 may include first to third NMOS transistors 371 to 373 and fourth to sixth resistors R4, R5, and R6. The first to third NMOS transistors 371 to 373 are connected to the ground voltage VSSQ, respectively, and the first to third NMOS transistors 371 to 373 are first to third NMOS transistors 371. 373) is connected between each of the external pins 210.

The inverter 321 may invert the read data DOUT received from the memory core and output the inverted read data DOUTB. The first to third NAND gates 331 to 333 perform NAND operations on the read data DOUT and the first to third strength codes SCDI1, SCDI2, and SCDI3, respectively. The first to third AND gates 341 to 343 perform an AND operation on each of the inverted read data DOUTB and the first to third strength codes SCDI1, SCDI2, and SCDI3. Each of the first to third selectors 334 to 336 receives an output enable signal OEN as a selection signal, receives a power supply voltage VDDQ as a first input signal, and first to third NAND gates. Each output may be received as a second input signal. Each of the fourth to sixth selectors 344 to 346 receives an output enable signal OEN as a selection signal, receives a ground voltage VSSQ as a first input signal, and first to third and gates. Each of the outputs 341 to 343 may be received as a second input signal.

When the output enable signal OEN is inactivated, each of the first to third selectors 334 to 336 outputs a high level pull-up driving control signal PUDCS, and the fourth to sixth selectors 344. Each of the 346 outputs a low level pull-down driving control signal PDDCS. Accordingly, the first to third PMOS transistors 361 to 363 are turned off by the high-level pull-up driving control signal PUDCS and the low-level pull-down driving control signal PNDCS is turned off. The first to third NMOS transistors 371 to 373 are turned off. Accordingly, the first to third resistors R1, R2, and R3 are electrically disconnected from the external pins 210, respectively, and the fourth to sixth resistors R4, R5, and R6 are respectively external pins 210. Electrically isolated from the

When the output enable signal OEN is activated in the read mode, each of the first to third selectors 334 to 336 controls the output of each of the first to third NAND gates 331 to 333. Output to the pull-up driver 360 as a signal PUDCS, and each of the fourth to sixth selectors 344 to 346 pulls the output of each of the first to third and gates 341 to 343. It may output to the pull-down driver 370 as a -down driving control signal PNDCS.

In both of the reads, the pull-up driver 360 and the pull-down driver 370 may provide a driver impedance while performing a driving operation based on the read data DOUT. For example, when the read data DOUT has a logic high level, since the inverted read data DOUTB has a logic low level, the output of the first to third end gates 341 to 343 may be the first to third times. Regardless of the strength codes SCDI1, SCDI2, and SCDI3, they are all at the logic low level. Accordingly, each of the fourth to sixth selectors 344 to 346 may output the low-level pull-down driving control signal PDDCS. Accordingly, the first to third NMOS transistors 371 to 373 are turned on and off, and the fourth to sixth resistors R4, R5, and R6 are electrically disconnected from the external pin 210, respectively. Since the read data DOUT has a logic high level, an output of the NAND gates 334, 335, and 336 is opposite to a logic level of each of the first to third strength codes SCDI1, SCDI2, and SCDI3. Will have For example, when the strength code SCDI is [100], the output of the NAND gates 334, 335, and 336 becomes [011]. Accordingly, the pull-up driving control signal PUDCS is applied to the pull-up driver 360. Accordingly, the first PMOS transistor 361 is turned on, the second and third PMOS transistors 362 and 363 are turned off, and the first resistor R1 is electrically connected to the external pin 210. And the second and third resistors R2 and R3 are electrically disconnected from the external pin 210. Therefore, while a pull-up driver impedance including the first resistor R1 is provided to a transmission line connected to the external pin 210, data having a logic high level may be transmitted through the transmission line.

For example, when the read data DOUT has a logic low level, the output of the first to third NAND gates 331 to 333 is independent of the first to third strength codes SCDI1, SCDI2, and SCDI3. All are at logic high levels. Accordingly, each of the first to third selectors 334 to 336 may output a high level pull-up driving control signal PUDCS. Accordingly, the first to third PMOS transistors 361 to 363 are turned on and off, and the first to third resistors R1, R2, and R3 are electrically disconnected from the external pin 210, respectively. Since the read data DOUT has a logic low level, the output of the AND gates 344, 345, and 346 may have the same logic level as that of each of the first to third strength codes SCD1, SCD2, and SCD3. To have. For example, if the strength code SCDI is [100], the output of the AND gates 334, 335, and 336 becomes [100]. Accordingly, the pull-down driving control signal PDDCS of [100] is applied to the pull-down driver 370. Accordingly, the first NMOS transistor 371 is turned on, the second and third NMOS transistors 372 and 373 are turned off, and the fourth resistor R4 is electrically connected to the external pin 210. And the fifth and sixth resistors R5 and R6 are electrically disconnected from the external pin 210. Therefore, while a pull-down driver impedance including the fourth resistor R4 is provided to the transmission line connected to the external pin 210, data having a logic low level may be transmitted through the transmission line.

As described with reference to FIG. 4, the strength code SCDI reflects a data rate or an operating frequency FOP (toggle rate of data), so that the case where the data rate is high (that is, the strength code SCDI) In the case of [111], the terminal resistor can be made small to charge and discharge the channel in a short time. In addition, when the data rate is low (that is, when the strength code (SCDI) is [100]), the termination resistance can be increased to reduce the current consumption by reducing the DC current flowing along the channel.

That is, when the strength code SCDI is [111] and the read data DOUT is at a logic high level, the pull-up driving control signal PUDCS becomes [000], so that the first to third resistors R1 connected in parallel are connected. The pull-up driver impedance ˜R3) is provided to a transmission line connected to the external pin 210 and data having a logic high level may be transmitted through the transmission line. In addition, when the strength code SCDI is [111] and the read data DOUT is at a logic low level, the pull-down driving control signal PDDCS becomes [111], so that the fourth to sixth resistors R4 to parallel are connected. The pull-down driver impedance configured by R6 is provided to a transmission line connected to the external pin 210, and data having a logic low level may be transmitted through the transmission line. In addition, when the strength code SCDI is [100] and the read data DOUT is at a logic high level, the pull-up driving control signal PUDCS becomes a pull-up configured with the first resistor R1. As the driver impedance is provided to the transmission line connected to the external pin 210, data having a logic high level may be transmitted through the transmission line. In addition, when the strength code SCDI is [100] and the read data DOUT is at a logic low level, the pull-down driving control signal PDDCS becomes [100], so the pull-down configured by the fourth resistor R4 is performed. As the driver impedance is provided to the transmission line connected to the external pin 210, data having a logic low level may be transmitted through the transmission line.

The first and second resistors R1 and R2 may have substantially the same resistance values, and the third resistor R3 may have a resistance value that is half of the second resistance. In addition, the fourth to sixth resistors R4 to R6 may have substantially the same resistance values as the first to third resistors R1 to R3, respectively. For example, each of the first resistor R1 and the second resistor R2 may have a resistance value of about 200 Ω, and the third resistor R3 may have a resistance value of about 100 200 Ω. In this case, if the read data (DOIT) is a logic high level and the strength code (SCDI) is [100], the pull-up driver impedance may have a resistance value of about 200 Ω, and the strength code (SCDI) is [110]. ], The pull-up driver impedance may have a resistance value of about 100 Ω, and when the strength code SCDI is [111], the pull-up driver impedance may have a resistance value of about 50 Ω.

In FIG. 6, each of the first to sixth resistors R1 to R6 is illustrated as one resistor, but each of the first to sixth resistors R1 to R6 may include a plurality of resistors connected in parallel and It can be implemented with transistors for controlling the connection of the resistors.

7 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention. The semiconductor memory device 400 of FIG. 7 may include the ODT circuit 100 of FIG. 1 and the data output buffer 400 of FIG. 4.

Referring to FIG. 7, the semiconductor memory device 400 may include a memory core 410, a data output buffer 300, a data input buffer 420, an address buffer 430, an ODT buffer 440, and a command decoder 450. , A latency circuit 460, a clock synchronization circuit 470, an inverter 480, and an ODT circuit 100.

The memory core 410 stores write data provided from the data input buffer 420, generates read data, and provides the read data to the data output buffer 300. The memory core 410 decodes a word line of the memory cell array 411 by decoding the row address RA received from the memory cell array 411 and the address buffer 430 including a plurality of memory cells that store data. A row decoder 412 for selecting, a column decoder 413 for selecting at least one bit line of the memory cell array 411 by decoding the column address CA received from the address buffer 430, and a selected memory It may include a sense amplifier 414 for sensing the data stored in the cells to generate the read data.

The address buffer 430 provides a row address RA to the row decoder 412 based on the address signal ADDR received from the memory controller through the address pin 240, and provides a column address (RA) to the column decoder 413. CA) can be provided. The command decoder 450 decodes the command signal CMD received from the memory controller through the command pin 230, for example, a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, and the like. As a result, a control signal corresponding to the command signal CMD may be generated. The semiconductor memory device 400 may further include a mode register for a mode register set and an extended mode register set. The clock synchronizing circuit 471 may receive the external clock signal CLK through the clock pin 250 and provide an internal clock signal synchronized with the external clock signal CLK to the latency circuit 460. The clock synchronization circuit 470 may include a delay lock loop (DLL) or a phase locked loop.

The data output buffer 300 and the data input buffer 420 are connected to the external data input / output pin 210. The data output buffer 300 transmits the read data to the memory controller through the data input / output pin 210, and the data input buffer 420 receives the data input / output pin 210 from the memory controller. Write data can be received. For convenience of description, FIG. 7 illustrates one data input / output pin 210, one data output buffer 300, and one data input buffer 420, but the semiconductor memory device 400 includes a plurality of data input / output pins. Data input buffers and data output buffers. In addition, the semiconductor memory device 400 may include a plurality of address pins and command pins.

The ODT circuit 100 is coupled to the data input / output pin 210 with the data output buffer 300 and the data input buffer 420. For convenience of description, FIG. 7 illustrates one data input / output pin 210 and one ODT circuit 100, but the semiconductor memory device 400 may include a plurality of data input / output pins and a plurality of ODT circuits connected thereto. It may include. In addition, the semiconductor memory device 400 may further include a data strobe pin, a data mask pin, an end data strobe pin, and the like, and may further include ODT circuits respectively connected thereto.

The ODT circuit 100 may vary the resistance value of the termination resistor in response to the strength code SCD received from the ODT buffer 440. The ODT buffer 440 may receive the strength code SCD from the memory controller through the ODT pin 220, and buffer the strength code SCD to provide the ODT circuit 100.

The ODT circuit 100 may be electrically disconnected from the data input / output pin 210 in response to the output enable signal OEN received from the latency circuit 460. When the command decoder 450 receives a read command from the memory device through the command pin 230, the command decoder 450 may generate a read mode signal RDMS. The latency circuit 460 receives the read mode signal RDMS from the command decoder 460, receives an internal clock signal synchronized with the external clock signal CLK from the clock synchronization circuit 470, and receives a data input / output pin. An output enable signal OEN having a logic high level may be generated while the read data is transmitted through 210.

The ODT circuit 100 may be electrically disconnected from the data input / output pin 210 in response to the output enable signal OEN in the read mode in which the read data is transmitted through the data input / output pin 210. . The ODT circuit 100 receives a termination resistor that varies according to a strength code SCD in response to a strength code SCD in a write mode through which the write data is received through the data input / output pin 210. Can be provided to

The data output buffer 300 is electrically from the data input / output pin 210 in response to the output enable signal OEN received from the latency circuit 460 (when the output enable signal OEN is disabled). Can be blocked. In addition, the data output buffer 300 inverts the read data while transmitting the data in response to the read data and the reverse strength code (SCDI) in the read mode in which the read data is transmitted through the data input / output pin 210. A driver impedance variable according to a strength code SCDI may be provided to the data transmission line. Inverted strength code (SCDI) is the strength code (SCD) is inverted by the inverter 480. Therefore, the strength code SCD and the inverted strength code SCD may reflect a data rate, that is, an operating frequency.

That is, in the semiconductor memory device of FIG. 7, in the write mode, the ODT circuit 100 may provide a termination resistor that varies according to the operating frequency to the data transmission line to reduce current consumption. In the read mode, the data output buffer 300 may operate at the operating frequency. The current consumption can be reduced by providing read data while providing a driver impedance that varies according to the data transmission line.

8 is a block diagram illustrating an ODT circuit according to another embodiment of the present invention.

Referring to FIG. 8, the ODT circuit 500 includes a terminator 510 and an adjuster 520. The termination 510 is connected to a power supply voltage Vs having a fixed voltage level. Termination 510 and adjustment 520 are connected to external pin 505 at adjustment node CN. The external pin 505 is connected to the external resistor R through the channel. Termination 510 provides a termination resistor that matches an external resistor R to a channel connected to an external pin 505 in response to a digital control code DCC. The adjusting unit 520 generates a digital control code DCC based on the voltage of the adjusting node CN and the reference voltage Vref and provides the digital control code DCC to the termination unit 510 so that the termination resistor provided from the termination unit 510 has a channel. Match with the external resistor (R) connected through. The external pin 505 may be a data input / output pin, a data strobe pin, a data mask pin, a termination data strobe pin, or the like. Here, the term “pin” broadly refers to an electrical interconnection to an integrated circuit and includes, for example, a pad or other electrical contact point on the integrated circuit.

The ODT circuit 500 of FIG. 8 changes the termination resistance of the termination portion 510 through the digital control code DCC such that the voltage level of the adjustment node CN is substantially equal to the level of the reference voltage Vref. The external resistor R matches the termination resistance of the termination portion 510.

FIG. 9 is a circuit diagram illustrating the ODT circuit of FIG. 8.

Referring to FIG. 9, the termination part 510 includes a plurality of PMOS transistors 511, 512, and 513 connected between a power supply voltage Vs having a fixed voltage level and the adjustment node CN. Each of the PMOS transistors 511, 512, and 513 is turned on / off by applying each bit of the digital control code DCC to the gate. As the PMOS transistors 511, 512, and 513 are turned on / off, the voltage level of the adjustment node CN varies. The PMOS transistors 511, 512, and 513 may have different sizes. For example, each of the PMOS transistors 511, 512, and 513 may have a size ratio of 4: 2: 1.

The adjusting unit 520 may include a comparator 521, a counter 522, and a register 523. The comparator 521 compares the voltage of the adjustment node CN with the reference voltage Vref and provides the comparison result as a matching signal MS to the counter 522. If the voltage level of the adjustment node CN is higher than the reference voltage Vref, a positive matching signal MS is provided to the counter 522. When the voltage level of the adjustment node CN is lower than the reference voltage Vref, a negative matching signal MS is provided to the counter 522. If the voltage level of the adjustment node CN is equal to the reference voltage Vref, a matching signal MS of "0" is provided to the counter 522. Here, the reference voltage Vref may be 1/2 of the power supply voltage Vs.

The counter 522 outputs a counting value CV, which increases or decreases according to the matching signal MS, to the register 523. For example, if a positive matching signal MS is provided to the counter 522, the counter 522 outputs an incremented counting value CV. For example, if a negative matching signal MS is provided to the counter 522, the counter 522 outputs a reduced counting value CV. Also, for example, if a matching signal MS of "0" is provided to the counter 522, the counter 522 maintains the counting value CV.

The register 523 stores the counting value CV and provides it to the termination 510 as a digital control code DCC. For example, when a positive matching signal MS is provided to the counter 522, the counter 522 outputs an incremented counting value CV so that the digital control code DCC is increased by one bit. That is, the bit having the high level among the digital control codes DCC is increased. Therefore, since the PMOS transistor turned off at the termination part 510 increases by one, the voltage level of the control node CN is lowered. That is, the termination resistance provided to the external pin 505 at the termination portion 510 is increased. For example, when a negative matching signal MS is provided to the counter 522, the counter 522 outputs a reduced counting value CV, so that the digital control code DCC is reduced by one bit. That is, the bit having the high level among the digital control codes DCC is reduced. Therefore, since the PMOS transistor turned on at the termination part 510 increases by one, the voltage level of the control node CN is increased.

In this manner, in the ODT circuit 500 of FIG. 9, when the on-die termination operation is performed, the external resistor R connected to the external pin 505 by comparing the voltage level of the adjustment node CN with the reference voltage Vref. ) Therefore, it is not necessary to adjust the level of the voltage applied to the gates of the PMOS transistors 511, 512, and 513, and simply turn on / off the PMOS transistors 511, 512, and 513 according to the digital control code DCC. Since the circuit is simple to implement, and only the PMOS transistors required for voltage level control of the PMOS transistors 511, 512, and 513 need to be turned on, current consumption can be reduced.

In addition, this on-die termination can be performed separately for each pin.

10 is a block diagram illustrating an off-chip driver (OCD) according to an embodiment of the present invention.

Referring to FIG. 10, the OCD 500 includes a terminator 560 and an adjuster 570. The termination 560 is connected to the adjustment node CN connected to the external pin 555. The external pin 555 is connected to the external resistor R through the channel. Termination 560 provides a driver impedance that matches the external resistor R to the channel connected to the external pin 555 in response to the digital control code DCC. The adjusting unit 570 is also connected to the adjusting node CN connected to the external pin 555. That is, the terminating portion 560 and the adjusting unit 570 are connected to the adjusting node CN in parallel with each other. The adjusting unit 570 generates a digital control code DCC based on the adjusting node CN voltage and the reference voltage Vref, and provides the digital control code DCC to the termination unit 560 so that the driver impedance provided from the termination unit 510 is used to control the channel. Match with external resistor (R) connected through. The external pin 555 may be a data input / output pin, a data strobe pin, a data mask pin, a termination data strobe pin, or the like. Here, the term “pin” broadly refers to an electrical interconnection to an integrated circuit and includes, for example, a pad or other electrical contact point on the integrated circuit.

The OCD 550 of FIG. 10 changes the driver impedance of the termination portion 560 through the digital control code DCC to match the external resistor R and the driver impedance. In addition, the OCD 550 of FIG. 10 may be connected to an external pin 555 separately from a data output buffer for outputting read data through an external pin to match the driver impedance when the read data is transmitted through the external pin. That is, the OCD 550 of FIG. 10 may be included in the data output buffer 300 of FIG. 7 or connected to the external pin 210 in parallel with the data output buffer 300 to provide a driver impedance matched to an external resistance. . In this case, the data output buffer 300 of FIG. 7 may not provide a driver impedance.

FIG. 11 is a circuit diagram illustrating the OCD of FIG. 10.

Referring to FIG. 11, the termination part 560 includes a plurality of NMOS transistors 561, 562, and 563 connected between the adjustment node CN and the ground voltage. Each of the NMOS transistors 561, 562, and 563 is turned on / off by applying each bit of the digital control code DCC to the gate. As the NMOS transistors 561, 562, and 553 are turned on / off, the driver impedance provided to the channel connected to the external pin 555 is changed. The NMOS transistors 561, 562, and 563 may have different sizes. For example, each of the NMOS transistors 561, 562, and 563 may have a size ratio of 4: 2: 1.

The adjusting unit 570 may include a comparator 571, a counter 572, and a register 573. The comparator 571 compares the voltage of the adjustment node CN with the reference voltage Vref and provides the comparison result as a matching signal MS to the counter 572. If the terminal 560 voltage level is higher than the reference voltage Vref, a positive matching signal MS is provided to the counter 572. If the terminal 560 voltage level is lower than the reference voltage Vref, a negative matching signal MS is provided to the counter 572. If the voltage level of the termination 560 is equal to the reference voltage Vref, a matching signal MS of "0" is provided to the counter 562. Here, the voltage level of the termination 560 is inversely proportional to the driver impedance provided at the termination 560. That is, if the driver impedance provided from the termination 560 is large, the voltage level of the termination 560 is low. If the driver impedance provided from the termination 560 is small, the voltage level of the termination 560 is high.

The counter 572 outputs a counting value CV, which increases or decreases according to the matching signal MS, to the register 573. For example, if a positive matching signal MS is provided to the counter 572, the counter 522 outputs a reduced counting value CV. For example, when a negative matching signal MS is provided to the counter 572, the counter 572 outputs an increased counting value CV. Also, for example, if a matching signal MS of " 0 " is provided to the counter 572, the counter 572 maintains the counting value CV.

The register 573 stores the counting value CV and provides it to the termination 560 as a digital control code DCC. For example, when a positive matching signal MS is provided to the counter 572, the counter 572 outputs a reduced counting value CV so that the digital control code DCC is reduced by one bit. That is, the bit having the high level among the digital control codes DCC is reduced. Therefore, since the NMOS transistor turned off at the termination 560 increases, the voltage level of the termination 560 is lowered. That is, the driver impedance provided to the external pin 505 at the termination portion 560 is increased. For example, when a negative matching signal MS is provided to the counter 572, the counter 572 outputs an increased counting value CV, so that the digital control code DCC is increased by one bit. That is, the bit having the high level among the digital control codes DCC is increased. Therefore, since the NMOS transistor turned on at the termination part 560 increases, the voltage level of the control node CN is increased. That is, the driver impedance provided to the external pin 505 at the termination portion 560 is reduced.

In this manner, in the OCD 500 of FIG. 11, when the driver operation is performed, the NMOS transistors 561, 562, and 563 connected between the external pin 555 and the controller 570 are selectively turned on. By matching the external resistor (R) connected to the external pin 555 and the driver impedance provided from the termination portion 560. Therefore, it is not necessary to adjust the level of the voltage applied to the gates of the NMOS transistors 561, 562, and 563, and simply turn the NMOS transistors 561, 562, and 563 on / off according to the digital control code DCC. Since the circuit is simple to implement, and only the NMOS transistors necessary for voltage level control of the NMOS transistors 561, 562, and 563 need to be turned on, current consumption can be reduced.

In addition, this driver impedance calibration can be performed separately for each pin.

12 is a block diagram illustrating a memory module according to an example embodiment.

Referring to FIG. 12, the memory module 600 includes a first memory rank 610 and a second memory rank 620.

The first memory rank 610 and the second memory rank 620 receive the first chip select signal CS1 and the second chip select signal CS2, respectively, and the first chip select signal CS1 and the second chip. It may be selectively driven in response to the selection signal CS2. The first memory rank 610 and the second memory rank 620 may be disposed on the same side of the memory module 600, and may be disposed on different sides. 10 illustrates a memory module 600 including two memory ranks 610 and 620, the memory module 600 may include one or more memory ranks.

Each of the first memory rank 610 and the second memory rank 620 may include a plurality of semiconductor memory devices. The plurality of semiconductor memory devices may be the semiconductor memory device 400 of FIG. 7 that receives a strength code SCD from an memory controller through an ODT pin.

13A to 13F illustrate examples of a memory module according to example embodiments.

Referring to FIG. 13A, the memory module 700a may be an unbuffered dual in-line memory module (UDIMM). The memory module 700a may include a plurality of semiconductor memory devices that provide an ODT or driver impedance to the data transmission lines DQ. The semiconductor memory devices may be connected to data transmission lines DQ, respectively. In addition, the semiconductor memory devices may be connected to the command / address transmission lines CA in a tree structure. In one embodiment, in data transfer and command / address transfer, pseudo-differential signaling utilizing a reference data voltage and a reference command / address voltage from a predetermined power supply voltage in the memory controller or memory module may be utilized. Can be.

Referring to FIG. 13B, the memory module 700b may be a UDIMM. The memory module 700b may include a plurality of semiconductor memory devices that provide an ODT or driver impedance to the data transmission lines DQ, and a module termination resistor 701 connected to one end of the command / address transmission lines CA. Can be. Command / address transmission lines CA may be connected to the semiconductor memory devices in a fly-by daisy-chain topology. Read / write leveling may be performed in the memory module 700b.

Referring to FIG. 13C, the memory module 700c may be a registered dual in-line memory module (RDIMM). The memory module 700c is connected to a plurality of semiconductor memory devices that provide an ODT or driver impedance to the data transmission lines DQ, command / address transmission lines CA, and provides a command / address signal to the semiconductor memory devices. The module termination resistors 712 and 713 connected to both ends of the command / address register 711 and the command / address transmission lines CA may be included. The command / address register 711 may be connected to the semiconductor memory devices in a daisy-chain manner.

Referring to FIG. 13D, the memory module 700d may be an RDIMM. The memory module 700d is connected to a plurality of semiconductor memory devices that provide an ODT or driver impedance to the data transmission lines DQ, command / address transmission lines CA, and provides a command / address signal to the semiconductor memory devices. And a module termination resistor 722 connected to one end of the command / address register 721 and the command / address transmission lines CA. The command / address register 721 may be connected to the semiconductor memory devices in a fly-by daisy-chain manner. Read / write leveling may be performed in the memory module 700d.

Referring to FIG. 13E, the memory module 700e may be a fully buffered dual in-line memory module (FBDIMM). The memory module 700e receives a high-speed packet from a plurality of semiconductor memory devices providing an ODT or driver impedance to data transmission lines, and a memory controller, converts the packet into a command / address signal and data, and converts the semiconductor memory to the semiconductor memory. Hub 731 providing the devices. For example, the hub 731 may be an advanced memory buffer (AMB).

Referring to FIG. 13F, the memory module 700f may be a Load Reduced Dual In-line Memory Module (LRDIMM). The memory module 700f receives a command / address signal and data from a plurality of semiconductor memory devices providing an ODT or driver impedance to data transmission lines, and a plurality of signal lines from a memory controller, and receives the command / address signal and the A buffer 741 may be provided to buffer data and provide the same to the semiconductor memory devices. Data transmission lines between the buffer 741 and the plurality of semiconductor memory devices may be connected in a point-to-point manner. In addition, the command / address transmission lines between the buffer 741 and the plurality of semiconductor memory devices may be connected in a multi-drop method, a daisy-chain method, or a fly-by daisy-chain method. Since the buffer 741 buffers both the command / address signal and the data, the memory controller may interface with the memory module 700f by driving only the load of the buffer 741. Accordingly, the memory module 700f may include a greater number of memory devices and memory ranks, and the memory system may include a greater number of memory modules.

14 is a diagram illustrating a memory system according to an embodiment of the present invention.

Referring to FIG. 14, the memory system 800 includes a memory controller 810 and at least one memory module 820 and 830.

The first memory module 820 and the second memory module 830 are connected to the memory controller 810 through the bus 840. Each of the first and second memory modules 820 and 830 may be the memory module 600 of FIG. 10 or the memory modules 700a, 700b, 700c, 700d, 700e, and 700f of FIGS. 11A through 11F. .

The first memory module 820 includes at least one memory rank R1 and R2, and the second memory module 830 includes at least one memory rank R3 and R4. In one embodiment, the memory ranks R1, R2, R3, R4 may be connected in a multi-drop manner for transmitting and receiving data and / or address signals over the same transmission line. Each of the memory ranks R1, R2, R3, and R4 (ie, each of the semiconductor memory devices included in the memory rank) may improve signal fidelity by providing a termination resistor or a driver impedance to the data transmission line. In an embodiment, the memory controller 810 may also perform an ODT and perform a pull-up termination operation by using a pull-up resistor (RTT) connected between the power supply voltage VDDQ and the transmission line.

As such, the on-die termination circuit, the data output buffer, and the semiconductor memory device according to the embodiments of the present invention consume current by varying the termination resistance or driver impedance provided to the data transmission line according to the strength code reflecting the data rate. Can be reduced and signal fidelity can be improved.

The present invention can be usefully used in any semiconductor memory device, memory module and memory system.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

Claims (10)

A termination resistor connected to an external pin and providing a termination resistor to a transmission line connected to the external pin; And
And a termination controller connected to the termination resistor and configured to vary a resistance value of the termination resistor in response to a plurality of bits of strength code reflecting a data rate. The semiconductor memory device of claim 1, wherein the termination controller decreases the resistance value of the termination resistor as the data rate is increased, and increases the resistance value of the termination resistor as the data rate is decreased. Die termination circuit. The terminal of claim 1, wherein the termination controller is further configured to generate a plurality of bit termination control signals that are activated in response to the strength code and the output enable signal.
The terminating resistor unit,
A plurality of transistors each connected to a power supply voltage and turned on in response to each bit of the termination control signal; And
And a plurality of resistors coupled between each of the plurality of transistors and the external pin. A termination connected between a power supply voltage having a fixed voltage level and an adjustment node coupled to an external pin and providing a termination resistor to a channel connected to the external pin in response to a plurality of bits of digital control code; And
An adjusting unit connected to the adjusting node, wherein the adjusting unit changes the value of each bit of the digital control code based on a result of comparing the voltage of the adjusting node with a reference voltage to match the termination resistor with an external resistor connected to the external pin. An on-die termination circuit of a semiconductor memory device comprising.  5. The terminal of claim 4, wherein the termination part includes a plurality of PMOS transistors connected between the power supply voltage and the adjustment node, and each bit of the digital control code is applied to a gate of the PMOS transistors. On-die termination circuit of semiconductor memory device. A driver connected to an external pin and providing a driver impedance to the transmission line while performing a driver operation for providing read data to a memory controller through a transmission line connected to the external pin; And
A driving control signal connected to the driving unit, controlling the driving unit to perform the driver operation in response to an output enable signal, and combining a read code with a strength code reflecting the data rate to generate a driving control signal for controlling the driving unit; And a controller, wherein the driver impedance is varied according to the strength code. The method of claim 6, wherein the output enable signal is activated in the read mode,
The control unit generates a pull-up driving control signal and a pull-down driving control signal by combining the read data and the strength code, and the pull-up driving control signal and the drive unit in response to the output enable signal. A data output buffer of a semiconductor memory device, characterized by providing a pull-down driving control signal. The method of claim 6, wherein the driving unit
A pull-up driver connected between a power supply voltage and the external pin and receiving the pull-up driving control signal from the controller; And
And a pull-down driver connected between a ground voltage and the external pin and receiving the pull-down driving control signal from the controller. The method of claim 6,
And said power supply voltage is 0.2V. A memory core that stores data and generates read data based on the stored data; And
And a data output buffer for outputting the read data provided from the memory core to a memory controller through an external pin and providing a variable driver impedance in response to a plurality of bits of strength code reflecting a data rate on the transmission line in a read mode. A semiconductor memory device.

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