KR101765060B1 - On-die termination circuit, data output buffer, semiconductor memory device - Google Patents

Abstract

An on-die termination (ODT) circuit of a semiconductor memory device includes a termination resistor portion and a termination control portion. The termination resistor portion is connected to an external pin and provides a termination resistance to a transmission line connected to the external pin. The termination control unit is connected to the termination resistance unit and varies a resistance value of the termination resistance in response to a plurality of bit length code reflecting the data rate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an on-die termination circuit, a data output buffer, and a semiconductor memory device,

The present invention relates to on-die termination, and more particularly, to an on-die termination circuit, a data output buffer, and a semiconductor memory device.

On-die termination (ODT) has been introduced to improve signal integrity by minimizing signal reflection at the interface between the memory controller and the semiconductor memory device. The ODT circuit can suppress signal reflections by providing a termination resistor (RTT) matched to the impedance of the transmission line.

As the operating voltage decreases, there is a need to reduce power consumption in such ODT circuits.

In order to solve the above problems, it is an object of the present invention to provide an on-die termination circuit capable of reducing power consumption.

Another object of the present invention is to provide a data output buffer capable of reducing power consumption.

Still another object of the present invention is to provide a semiconductor memory device including the data output buffer.

To achieve the above object, an on-die termination (ODT) circuit of a semiconductor memory device includes a termination resistor portion and a termination control portion. The termination resistor portion is connected to an external pin and provides a termination resistance to a transmission line connected to the external pin. The termination control unit is connected to the termination resistance unit and varies a resistance value of the termination resistance in response to a plurality of bit length code reflecting the data rate.

In one embodiment, the termination controller may decrease the resistance value of the termination resistance as the data rate increases, and may increase the resistance value of the termination resistance as the data rate decreases.

In one embodiment, the termination control unit may generate a plurality of bits of termination control signal that are activated in response to the length code and the output enable signal. A plurality of transistors each of which is connected to a power supply voltage and is turned on in response to each bit of the termination control signal; And a plurality of resistors coupled between each of the plurality of transistors and the external pin.

According to another aspect of the present invention, there is provided an on-die termination circuit including a termination part and an adjustment part. The termination is coupled between a power supply voltage having a fixed voltage level and an adjustment node coupled to the external pin and provides a termination resistance to the channel coupled to the external pin in response to the plurality of bits of the digital control code. Wherein the adjustment unit is connected to the adjustment node and changes the bit value of the digital control code based on a result of comparing the voltage of the adjustment node with the reference voltage so that the termination resistance is matched with the external resistance connected to the external pin do.

In one embodiment, the termination includes a plurality of PMOS transistors coupled between the power supply voltage and the tuning node, and each bit of the digital control code may be applied to a gate of the PMOS transistors.

In order to achieve the other object, the data output buffer of the semiconductor memory device includes a driver and a control unit. The driving unit is connected to an external pin and provides a driver impedance to the transmission line while performing a driver operation to supply read data to a memory controller through a transmission line connected to the external pin. The control unit is connected to the driving unit and controls the driving unit to perform the driver operation in response to an output enable signal. The driving unit controls the driving unit by combining the read data with the data code, . The driver impedance is varied according to the length code.

In one embodiment, the output enable signal is activated in a read mode, and the control unit combines the read data with the strength code to generate a pull-up driving control signal and a pull-down driving control signal, And may provide the pull-up driving control signal and the pull-down driving control signal to the driving unit in response to an enable signal.

A pull-up driver connected between the power supply voltage and the external pin and receiving the pull-up driving control signal from the control unit; And a pull-down driver connected between the ground voltage and the external pin and receiving the pull-down driving control signal from the control unit.

The power supply voltage may be 0.2V.

According to another aspect of the present invention, a semiconductor memory device includes a memory core and a data output buffer. The memory core stores data and generates read data based on the stored data. The data output buffer outputs the read data provided from the memory core to the memory controller via an external pin and provides a variable driver impedance in response to a plurality of bit string codes reflecting a data rate on the transmission line in a read mode .

According to embodiments of the present invention, current consumption can be reduced by providing a termination resistance or driver impedance that varies according to the data rate.

1 is a block diagram illustrating an on-die termination (ODT) circuit in accordance with an embodiment of the present invention.
FIGs. 2A and 2B show a string code providing circuit according to embodiments of the present invention. FIG.
3 is a circuit diagram showing an example of the ODT circuit of Fig.
4 is a block diagram illustrating a data output buffer according to an embodiment of the present invention.
5 is a block diagram showing the data output buffer of Fig.
6 is a circuit diagram showing the data output buffer of FIG.
7 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
8 is a block diagram illustrating an ODT circuit according to another embodiment of the present invention.
9 is a circuit diagram showing the ODT circuit of Fig.
10 is a block diagram illustrating an off-chip driver (OCD) according to an embodiment of the present invention.
11 is a circuit diagram showing the OCD of FIG.
12 is a block diagram illustrating a memory module according to an embodiment of the present invention.
13A-13F illustrate examples of memory modules according to embodiments of the present invention.
Figure 14 is a diagram illustrating a memory system in accordance with one embodiment of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Similar reference numerals have been used for the components in describing each drawing.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram illustrating an on-die termination (ODT) circuit in accordance with an embodiment of the present invention.

Referring to FIG. 1, the ODT circuit 100 includes a termination control unit 110 and a termination resistance unit 120.

The termination resistance portion 120 is connected to the external pin 210. The termination resistance portion 120 provides a termination resistance to a transmission line connected to the external fin 210. [ The external pin 210 may be a data input / output pin, a data strobe pin, a data mask pin, a termination data strobe pin, or the like. As used herein, the term " pin " refers broadly to electrical interconnections to an integrated circuit, including for example a pad or other electrical contact on an integrated circuit.

The termination resistor portion 120 may perform a pull-up termination operation that provides the termination resistor connected between the power supply voltage and the external pin 210. When the terminating resistor unit 120 performs the pull-up termination operation, the voltage of the transmission line connected to the external pin can be maintained at the power supply voltage. Accordingly, since the current flows in the terminating resistor unit 120 and the transmission line only when data having a low level is transmitted to the transmission line, the terminating resistor unit 120 performing the pull- The power consumption can be reduced as compared with the conventional center termination operation in which the current path is formed and the DC current is consumed.

The termination control unit 110 is connected to the termination resistance unit 120. The termination control unit 110 varies the resistance value of the termination resistance in response to a plurality of bits of strength code (SCD) reflecting the data rate. Here, the data rate refers to the operating frequency (opreating frequency) of the semiconductor memory device in which the ODT circuit 100 is included, or the toggle rate of data input to the semiconductor memory device via the external pin 210. Also, a plurality of bit string Tm (strength) codes (SCD) may be input from the memory controller via the control pin. For example, the control pin may be an ODT pin. The CD may be generated in a semiconductor memory device including the ODT circuit 100 (for example, EMRS, etc.).

The termination control unit 110 may generate the termination control signal TCS that controls the termination resistance unit 120 based on the string code SCD and the output enable signal OEN. The output enable signal OEN may be activated in a read mode in which data is output through a transmission line connected to the external pin 210. When the output enable signal OEN is activated, the termination control unit 110 may generate a termination control signal TCS that controls the termination resistance unit 120 so as not to provide the termination resistance. For example, the termination control unit 110 generates a termination control signal TCS having a predetermined logic level in response to the activated output enable signal OEN, and the termination resistance unit 120 generates the termination control signal TCS having the predetermined logic level The termination resistor and the external pin 210 may be disconnected in response to a termination control signal TCS having a terminal control signal TCS.

When the output enable signal OEN is deactivated, the termination control unit 110 may generate a termination control signal TCS that controls the termination resistance unit 120 to provide the termination resistance. In addition, the termination control unit 110 can change the logic level of the termination control signal TCS so as to vary the resistance value of the terminating resistor in response to the length code TCS. In response to the termination control signal TCS, for example, when the length code TCS indicates that the operating frequency is in the first range, the termination resistance section 120 is controlled to provide a termination resistance having a first resistance value . In addition, in response to the termination control signal TCS, the termination resistance portion 120 can be controlled to provide a termination resistance having a second resistance value when the stringency code TCS indicates that the operating frequency is in the first range . Here, if the first range is faster than the second range, the first resistance value may be smaller than the second resistance value.

FIGs. 2A and 2B show a string code providing circuit according to embodiments of the present invention. FIG.

Referring to FIG. 2A, the streaming code providing circuit 10 may be implemented with an extended mode register set (EMRS). The EMRS 10 is provided with data rate information (DRI), that is, an operating frequency (FOP), and provides a plurality of bits of the scale code (SCD) according to the operating frequency (FOP). The EMRS 10 may be included in the semiconductor memory device or may be included in the memory controller outside the semiconductor memory device.

Referring to FIG. 2B, the string code providing circuit 20 may include a plurality of comparators 21, 22, and 23. The comparator 21 compares the operating frequency FOP with the first reference frequency FR1 and outputs a first length code SCD1 according to the comparison result. The comparator 22 compares the operating frequency FOP with the second reference frequency FR2 and outputs a second length code SCD2 according to the comparison result. The comparator 23 compares the operating frequency FOP with the third reference frequency FR3 and outputs the third string code SCD3 according to the result. For example, when the first reference frequency FR1 is lower than the second reference frequency FR2 and the second reference frequency FR2 is lower than the third frequency FR3, the operating frequency FOP is lower than the first reference frequency FR1 ) And the second reference frequency FR2, SCD1 may be a low level, SCD2 may be a high level, and SCD3 may be a high level. That is, the string code (SCD) can be [011]. If the operating frequency FOP is between the second reference frequency FR2 and the third reference frequency FR3, the string code SCD may be [001]. Also, if the operating frequency is higher than the third reference frequency FR3, the length code SCD may be [000].

3 is a circuit diagram showing an example of the ODT circuit of Fig.

3, the termination controller 110 may include a first selector 111, a second selector 112, and a third selector 113. Each of the first selector 111, the second selector 112 and the third selector 113 may be implemented as a multiplexer. The termination resistance part 120 is connected to the external fin 210 and includes a first transistor 121, a first resistor Rl, a second transistor 122, a second resistor R 2, a third transistor 123, And a third resistor R3.

The first selector 111 includes a first input terminal connected to the power supply voltage VDDQ, a second input terminal connected to the ground voltage VSSQ, a selection terminal to which the output enable signal OEN is applied, (TCS1) is output. The first selector 111 may selectively output the power supply voltage VDDQ or the first power code SCD1 as the first termination control signal TCS1 in response to the output enable signal OEN.

The first transistor 121 may have a source coupled to the power supply voltage VDDQ, a gate coupled to the output terminal of the first selector 111, and a drain coupled to the first resistor R1. The first resistor Rl may be connected between the first transistor 121 and the external pin 210. The first transistor 121 may be turned on or off in response to the first terminal control signal TCS1 and the first resistor R1 may be turned on or off according to the ON / OFF state of the first transistor 121. [ As shown in Fig.

The second selector 112 includes a first input terminal connected to the power supply voltage VDDQ, a second input terminal connected to the ground voltage VSSQ, a selection terminal to which the output enable signal OEN is applied, And the output terminal TCS2 is output. The third selector 112 may selectively output the power supply voltage VDDQ or the second strength code SCD2 as the second terminal control signal TCS2 in response to the output enable signal OEN.

The second transistor 122 may have a source coupled to the power supply voltage VDDQ, a gate coupled to the output terminal of the second selector 112, and a drain coupled to the second resistor R2. The second resistor R2 may be connected between the second transistor 122 and the external pin 210. [ The second transistor 122 may be turned on / off in response to the second terminal control signal TCS2 and the second resistor R2 may be turned on / off in response to the ON / OFF state of the second transistor 122, As shown in Fig.

The third selector 113 includes a first input terminal connected to the power supply voltage VDDQ, a second input terminal connected to the ground voltage VSSQ, a selection terminal to which the output enable signal OEN is applied, And an output terminal to which the output terminal TCS3 is output. The third selector 113 may selectively output the power source voltage VDDQ or the third power source code SCD3 as the third terminal control signal TCS3 in response to the output enable signal OEN.

The third transistor 123 may have a source coupled to the power supply voltage VDDQ, a gate coupled to the output terminal of the third selector 113, and a drain coupled to the second resistor R2. The third resistor R3 may be connected between the third transistor 123 and the external pin 210. The third transistor 123 may be turned on and off in response to the third terminal control signal TCS3 and the third resistor R3 may be turned on or off in response to the on / As shown in Fig.

When the output enable signal OEN is activated in a read mode in which data is output through a transmission line connected to the external pin 210, the first selector 111 selects the power supply voltage VCC as the first terminal control signal TCS1, The second selector 112 outputs the power supply voltage VDDQ as the second terminal control signal TCS2 and the third selector 113 outputs the power supply voltage VDDQ as the third terminal control signal TCS2, (VDDQ). The first to third transistors 121, 122 and 123 are turned off in response to the first to third termination control signals TCS1, TCS2 and TCS3 having logic high levels, respectively. The first to third resistors R1, R2 and R3 may be electrically disconnected from the external pin 210 by the first through third transistors 121, 122 and 123 turned off, respectively. Accordingly, the ODT circuit 100 may not perform the termination operation in the read mode.

When the output enable signal OEN is inactivated, the first to third selectors 111, 112 and 113 output the first to third longitudinal control signals TCS1, TCS2 and TCS3, respectively, And outputs the codes SCD1, SCD2 and SCD3. The first to third transistors 121, 122 and 123 are turned on / off according to the logic levels of the first to third string codes SCD1, SCD2 and SCD3, respectively. The first to third resistors R1, R2 and R3 are electrically connected / disconnected from the external pin 210 by the first to third transistors 121, 122 and 123 turned on / off, respectively. Can be blocked.

For example, when the length code SCD is [011], only the first transistor 121 is turned on and only the first resistor R1 is electrically connected to the external pin 210. [ Accordingly, the termination resistance portion 120 can provide a termination resistance composed of the first resistor R1. The first transistor 121 and the second transistor 122 are turned on and the first resistor R1 and the second resistor R2 are electrically connected to the external pin 210. [ Lt; / RTI > Accordingly, the termination resistance portion 120 may provide a termination resistance composed of a first resistor R1 and a second resistor R2 connected in parallel. For example, if the length code is [000], the first to third transistors 121, 122 and 123 are turned on and the first to third resistors R1, R2 and R3 are electrically connected to the external pin 210 Lt; / RTI > Accordingly, the termination resistance portion 120 may provide a termination resistance composed of first to third resistors R1, R2, and R3 connected in parallel. Here, the first and second resistors R1 and R2 may have substantially the same resistance value, and the third resistor R3 may have a resistance value that is half of the second resistance. For example, each of the first resistor R1 and the second resistor R2 may have a resistance value of about 200 OMEGA, and the third resistor R3 may have a resistance value of about 100 200 OMEGA. In this case, if the lengthwise code (SCD) is [011], the termination resistance may have a resistance value of about 200 Ω, and when the lengthwise code (SCD) is [001], the termination resistance may have a resistance value of about 100 Ω And when the lengthwise code (SCD) is [000], the termination resistance may have a resistance value of about 50 [Omega].

Although the first to third resistors R1, R2 and R3 are shown as one resistor in FIG. 2, each of the first to third resistors R1, R2, and R3 may include a plurality And transistors for controlling the connection of the resistors.

As described above, the length code SCD reflects the data rate or the operating frequency (FOP, toggle rate of data), and therefore, when the data rate is high (that is, when the length code SCD is [000] ), It is possible to charge and discharge the channel in a short time by lowering the termination resistance. In addition, when the data rate is low (ie, when the length code (SCD) is [011]), the termination resistance can be increased to reduce the DC current flowing along the channel to reduce current consumption.

4 is a block diagram illustrating a data output buffer according to an embodiment of the present invention.

Referring to FIG. 4, the data output buffer 300 includes a controller 310 and a driver 350.

The driving unit 350 is connected to the external pin 210. The driving unit 350 provides a driver impedance to the transmission line while performing a driver operation to supply read data DOUT to the memory controller through a transmission line connected to the external pin 210. The external pin 210 may be a data input / output pin, a data strobe pin, or the like, which can be input and output. The driver 1120 may perform the pull-up termination operation as the termination operation.

The control unit 310 is connected to the driving unit 350. The control unit 310 controls the driving unit 350 to perform the driving operation in response to the output enable signal OEN and combines the read data DOUT with the data code SCDI reflecting the data rate, And a driving control signal DCS for controlling the driving control signal DCS. The driver impedance is varied according to the length code SCDI.

5 is a block diagram showing the data output buffer of Fig.

Referring to FIG. 5, the data output buffer 300 includes a controller 310 and a driver 320. The control unit 310 includes a pre-driver 320 and a driving control unit 330. The driver 350 includes a pull-up driver 360 and a pull-down driver 370.

The pre-driver 320 receives the read data DOUT from the memory core, inverts the read data DOUT, and provides the inverted readout data DOUTB to the driving control unit 330. [ The driving control unit 330 generates the pull-up driving control signal PUDCS by combining the read data DOUT with the string of the data SCDI and the readout data DOUT and outputs the inverted readout data DOUTB and the string of length codes Up driving control signal PUDCS and the pull-down driving control signal PDDCS in response to an output enable signal OEN to a driving unit (not shown) 350).

The pull-up driver 360 performs a driving operation in response to the pull-up driving control signal PUDCS while varying the resistance value of the transmission line connected to the external pin 201 according to the pull-up driving control signal PUDCS Provides a pull-up driver impedance. The pull-down driver 370 performs driving operation in response to the pull-down driving control signal PDDCS while varying the resistance value according to the pull-down driving control signal PDDCS to the transmission line connected to the external pin 210 Provides full-down driver impedance.

6 is a circuit diagram showing the data output buffer of FIG.

Referring to FIG. 6, the pre-driver 320 may include an inverter 321. The driving control unit 330 includes first to third NAND gates 331 to 333, first to third selectors 334 to 336, first to third AND gates 341 to 343, And sixth selectors 344-346. The pull-up driver 360 may include first to third PMOS transistors 361 to 363 and first to third resistors R 1, R 2, and R 3. The first to third PMOS transistors 361 to 363 are connected to the power supply voltage VDDQ and the first to third resistors R1 to R3 are connected to the first to third PMOS transistors 361 To 363 and the external pin 210, respectively. The pull-down driver 370 may include first through third emmos transistors 371 through 373 and fourth through sixth resistors R4, R5 and R6. The first to third NMOS transistors 371 to 373 are respectively connected to the ground voltage VSSQ and the first to third NMOS transistors 371 to 373 are connected to the first to third NMOS transistors 371 to 373. [ To 373 and the external pin 210, respectively.

The inverter 321 can output the inverted readout data DOUTB by inverting the readout data DOUT received from the memory core. The first to third NAND gates 331 to 333 perform the NAND operation on the read data DOUT and the first to third string codes SCDI1, SCDI2 and SCDI3, respectively. The first to third AND gates 341 to 343 end AND the inverted readout data DOUTB and the first to third stringent codes SCDI1, SCDI2 and SCDI3, respectively. Each of the first to third selectors 334 to 336 receives the output enable signal OEN as a selection signal, receives the power supply voltage VDDQ as a first input signal, (331 to 333) as the second input signal. Each of the fourth to sixth selectors 344 to 346 receives the output enable signal OEN as a selection signal, receives the ground voltage VSSQ as a first input signal, And can receive the output of each of the first to fourth input terminals 341 to 343 as the second input signal.

When the output enable signal OEN is inactivated, each of the first to third selectors 334 to 336 outputs a pull-up driving control signal PUDCS of a high level, and the fourth to sixth selectors 344 To 346 may each output a low-level pull-down driving control signal PDDCS. Therefore, the first to third PMOS transistors 361 to 363 are turned off by the high level pull-up driving control signal PUDCS, and the pull-down driving control signal PNDCS 1 to the third NMOS transistors 371 to 373 are turned off. The first through third resistors R1, R2 and R3 are electrically isolated from the external pin 210 and the fourth through sixth resistors R4, R5 and R6 are electrically isolated from the external pin 210, As shown in Fig.

When the output enable signal OEN is activated in the read mode, each of the first to third selectors 334 to 336 outputs the output of each of the first to third NAND gates 331 to 333 to the pull- Up driver 360 as the signal PUDCS and each of the fourth to sixth selectors 344 to 346 outputs the output of each of the first to third AND gates 341 to 343 to the pull- Down driver 370 as the down driving control signal PNDCS.

In both of the readout operations, the pull-up driver 360 and the pull-down driver 370 can provide the driver impedance while performing a driving operation based on the read data DOUT. For example, when the read data DOUT has a logic high level, since the inverted readout data DOUTB has a logic low level, the outputs of the first to third AND gates 341 to 343 are the first to third All become logic low levels regardless of the string codes (SCDI1, SCDI2, SCDI3). Thus, each of the fourth to sixth selectors 344 to 346 can output a pull-down driving control signal PDDCS of low level. Accordingly, the first to third NMOS transistors 371 to 373 are turned on / off and the fourth to sixth resistors R4, R5 and R6 are electrically isolated from the external pin 210, respectively. Since the read data DOUT has a logic high level, the outputs of the NAND gates 334, 335 and 336 are logic levels opposite to those of the first to third string codes SCDI1, SCDI2 and SCDI3, . For example, if the length code SCDI is [100], the output of the NAND gates 334, 335, and 336 becomes [011]. Thus, the pull-up driving control signal PUDCS of [011] is applied to the pull-up driver 360. The first and second PMOS transistors 362 and 363 are turned off so that the first resistor R1 is electrically connected to the external pin 210 And the second and third resistors (R2, R3) are electrically disconnected from the external pin (210). Therefore, a data having a logic high level can be transmitted through the transmission line while the pull-up driver impedance composed of the first resistor R1 is provided to the transmission line connected with the external pin 210. [

For example, when the read data DOUT has a logic low level, the outputs of the first to third NAND gates 331 to 333 are output regardless of the first to third string codes SCDI1, SCDI2 and SCDI3 All become logic high levels. Thus, each of the first to third selectors 334 to 336 can output a pull-up driving control signal PUDCS of a high level. Accordingly, the first to third PMOS transistors 361 to 363 are turned on / off and the first to third resistors R1, R2, and R3 are electrically disconnected from the external pin 210, respectively. Since the read data DOUT has a logic low level, the outputs of the AND gates 344, 345 and 346 have the same logic level as the logic level of each of the first to third string codes SCD1, SCD2 and SCD3 I have. For example, if the length code SCDI is [100], the outputs of the AND gates 334, 335, and 336 are [100]. Thus, the pull-down driving control signal PDDCS of [100] is applied to the pull-down driver 370. The second and third NMOS transistors 372 and 373 are turned off so that the fourth resistor R4 is electrically connected to the external pin 210 And the fifth and sixth resistors R5 and R6 are electrically disconnected from the external pin 210. [ Therefore, a data having a logic low level can be transmitted through the transmission line while the pull-down driver impedance composed of the fourth resistor R4 is provided to the transmission line connected with the external pin 210. [

As described with reference to FIG. 4, when the data rate is high (that is, when the length code SCDI is smaller than the threshold value SCDI), the length code SCDI reflects the data rate or the operating frequency (FOP, [111]), it is possible to charge and discharge the channel in a short time by reducing the termination resistance. In addition, when the data rate is low (ie, when the length of the SCDI is [100]), the termination resistance may be increased to reduce the DC current flowing along the channel to reduce current consumption.

That is, when the length code SCDI is [111] and the read data DOUT is logic high level, the pull-up driving control signal PUDCS becomes [000] so that the first through third resistors R1 To R3 may be provided to a transmission line connected to the external pin 210 so that data having a logic high level can be transmitted through the transmission line. The pull-down driving control signal PDDCS becomes [111] when the length code SCDI is [111] and the read data DOUT is at the logic low level, so that the fourth through sixth resistors R4- R6 may be provided to a transmission line connected to the external pin 210 so that data having a logic low level can be transmitted through the transmission line. In addition, since the pull-up driving control signal PUDCS is [011] when the length code SCDI is [100] and the read data DOUT is a logic high level, the pull- Data having a logic high level can be transmitted through the transmission line while a driver impedance is provided to a transmission line connected to the external pin 210. [ Down drive control signal PDDCS becomes [100] if the intensity code SCDI is [100] and the read data DOUT is at the logic low level, so that the pull- A driver impedance may be provided to a transmission line connected to the external pin 210, and data having a logic low level may be transmitted through the transmission line.

Here, the first and second resistors R1 and R2 may have substantially the same resistance value, and the third resistor R3 may have a resistance value that is half of the second resistance. The fourth to sixth resistors R4 to R6 may have substantially the same resistance value as the first to third resistors R1 to R3, respectively. For example, each of the first resistor R1 and the second resistor R2 may have a resistance value of about 200 OMEGA, and the third resistor R3 may have a resistance value of about 100 200 OMEGA. In this case, the full-up driver impedance may have a resistance value of about 200 OMEGA when the read data DOIT is a logic high level and the string code SCDI is [100] ], The pull-up driver impedance can have a resistance value of about 100 [Omega], and the full-up driver impedance can have a resistance value of about 50 [Omega] when the lengthwise code (SCDI) is [111].

Although the first to sixth resistors R1 to R6 are shown as one resistor in FIG. 6, each of the first to sixth resistors R1 to R6 may include a plurality of resistors connected in parallel, And transistors for controlling the connection of the resistors.

7 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention. The semiconductor memory device 400 of FIG. 7 may include the ODT circuit 100 of FIG. 1 and the data output buffer 400 of FIG.

7, the semiconductor memory device 400 includes a memory core 410, a data output buffer 300, a data input buffer 420, an address buffer 430, an ODT buffer 440, a command decoder 450, A latency circuit 460, a clock synchronization circuit 470, an inverter 480 and an ODT circuit 100. [

The memory core 410 stores write data provided from the data input buffer 420, generates read data, and provides the read data to the data output buffer 300. The memory core 410 includes a memory cell array 411 including a plurality of memory cells for storing data, a memory cell array 411 for decoding the row address RA received from the address buffer 430 and storing the word line of the memory cell array 411 A column decoder 413 for decoding the column address CA received from the address buffer 430 to select at least one bit line of the memory cell array 411, And a sense amplifier 414 for sensing the data stored in the cells and generating the read data.

The address buffer 430 provides the row address RA to the row decoder 412 based on the address signal ADDR received from the memory controller via the address pin 240 and provides the column decoder 413 with the column address CA). The command decoder 450 decodes the command signal CMD received via the command pin 230 from the memory controller, for example, a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, Thereby generating a control signal corresponding to the command signal CMD. The semiconductor memory device 400 may further include a mode register set for the mode register set and an extended mode register set. The clock synchronizing circuit 471 can receive the external clock signal CLK via the clock pin 250 and provide the internal clock signal synchronized with the external clock signal CLK to the latency circuit 460. [ Clock synchronization circuit 470 may include a delay locked loop (DLL) or phase locked loop.

The data output buffer 300 and the data input buffer 420 are connected to the external data input / output pin 210. The data output buffer 300 transmits the read data to the memory controller via the data input / output pin 210 and the data input buffer 420 receives the data from the memory controller via the data input / It is possible to receive the write data. 7 shows only one data input / output pin 210, a data output buffer 300 and a data input buffer 420 in FIG. 7, the semiconductor memory device 400 includes a plurality of data input / Data input buffers, and data output buffers. In addition, the semiconductor memory device 400 may include a plurality of address pins and command pins.

The ODT circuit 100 is connected to the data input / output pin 210 together with the data output buffer 300 and the data input buffer 420. 7, the semiconductor memory device 400 includes a plurality of data input / output pins and a plurality of ODT circuits connected to the data input / output pins 210 and the ODT circuits 100, respectively, for convenience of description. . In addition, the semiconductor memory device 400 may further include data strobe pins, data mask pins, termination data strobe pins, and the like, and may further include ODT circuits respectively connected to the data strobe pins, data mask pins, and termination data strobe pins.

The ODT circuit 100 may vary the resistance value of the termination resistor in response to the received length code SCD from the ODT buffer 440. [ The ODT buffer 440 receives the texture code SCD from the memory controller via the ODT pin 220 and buffers the texture code SCD to the ODT circuit 100.

The ODT circuit 100 may be electrically disconnected from the data input / output pin 210 in response to the output enable signal OEN received from the latency circuit 460. When the command decoder 450 receives the read command from the memory device via the command pin 230, the command decoder 450 can generate the read mode signal RDMS. The latency circuit 460 receives the read mode signal RDMS from the command decoder 460 and receives the internal clock signal synchronized with the external clock signal CLK from the clock synchronizing circuit 470, (OEN) having a logic high level during the transmission of the read data through the write enable signal line 210.

The ODT circuit 100 may be electrically disconnected from the data input / output pin 210 in response to the output enable signal OEN in the read mode in which the read data is transmitted through the data input / output pin 210 . The ODT circuit 100 outputs a termination resistance which varies in accordance with a length code (SCD) in response to a length code (SCD) in a writing mode in which the writing data is received via the data input / output pin 210, As shown in FIG.

The data output buffer 300 is electrically coupled to the data input / output pin 210 in response to an output enable signal OEN received from the latency circuit 460 (if the output enable signal OEN is disabled) Can be blocked. In addition, the data output buffer 300 transmits the read data in response to the read data and the inverted description code (SCDI) in the read mode in which the read data is transmitted through the data input / output pin 210, And can provide a driver impedance that varies according to the length code SCDI to the data transmission line. The inverted length code (SCDI) is that the length code (SCD) is inverted by the inverter (480). Thus, the length code (SCD) and the inverted length code (SCDI) can reflect the data rate, or the operating frequency.

That is, in the semiconductor memory device of FIG. 7, in the write mode, the ODT circuit 100 provides the data transfer line with a termination resistance that varies according to the operating frequency to reduce the current consumption. In the read mode, It is possible to reduce current consumption by providing read data while providing a variable driver impedance to the data transmission line.

8 is a block diagram illustrating an ODT circuit according to another embodiment of the present invention.

Referring to FIG. 8, the ODT circuit 500 includes a terminating portion 510 and an adjusting portion 520. The termination 510 is connected to a supply voltage Vs having a fixed voltage level. The terminating portion 510 and the adjusting portion 520 are connected to the external pin 505 at the adjusting node CN. The external pin 505 is connected to the external resistor R through a channel. Termination 510 provides termination resistors that match the external resistor R in the channel coupled to the external pin 505 in response to the digital control code DCC. The adjusting unit 520 generates and provides a digital control code DCC to the terminating unit 510 based on the voltage of the adjusting node CN and the reference voltage Vref so that the terminating resistor provided at the terminating end 510 To match the external resistor (R) connected thereto. The external pin 505 may be a data input / output pin, a data strobe pin, a data mask pin, a termination data strobe pin, or the like. As used herein, the term " pin " refers broadly to electrical interconnections to an integrated circuit, including for example a pad or other electrical contact on an integrated circuit.

The ODT circuit 500 of Figure 8 changes the termination resistance of the termination 510 through the digital control code DCC such that the voltage level of the tuning node CN is substantially equal to the level of the reference voltage Vref And matches the external resistance R and the terminating resistance of the terminating end 510.

9 is a circuit diagram showing the ODT circuit of Fig.

9, the termination 510 includes a plurality of PMOS transistors 511, 512, and 513 connected between a power supply voltage Vs having a fixed voltage level and an adjustment node CN. Each of the PMOS transistors 511, 512, and 513 is turned on / off by applying each bit of the digital control code DCC to the gate. As the PMOS transistors 511, 512 and 513 are turned on / off, the voltage level of the tuning node CN changes. The PMOS transistors 511, 512, and 513 may have different sizes. For example, each of the PMOS transistors 511, 512, and 513 may have a size ratio of 4: 2: 1.

The adjustment unit 520 may include a comparator 521, a counter 522, and a register 523. [ The comparator 521 compares the voltage of the adjustment node CN with the reference voltage Vref and provides the comparison result to the counter 522 as the matching signal MS. A positive matching signal MS is provided to the counter 522 if the voltage level of the tuning node CN is higher than the reference voltage Vref. A negative matching signal MS is provided to the counter 522 if the voltage level of the tuning node CN is lower than the reference voltage Vref. A matching signal MS of "0" is provided to the counter 522 if the voltage level of the tuning node CN is equal to the reference voltage Vref. Here, the reference voltage Vref may be 1/2 of the power source voltage Vs.

The counter 522 outputs to the register 523 a count value CV which is increased or decreased in accordance with the matching signal MS. For example, if a positive matching signal MS is provided to the counter 522, the counter 522 outputs an incremented count value CV. For example, when a negative matching signal MS is provided to the counter 522, the counter 522 outputs a reduced count value CV. Also, for example, if a match signal MS of "0" is provided to the counter 522, the counter 522 maintains the count value CV.

The register 523 stores the count value CV and provides it to the terminal 510 as a digital control code DCC. For example, when a positive matching signal MS is provided to the counter 522, the counter 522 outputs an incremented count value CV, so that the digital control code DCC is incremented by one bit. That is, a bit having a high level in the digital control code DCC is increased. As a result, the voltage level of the tuning node CN is lowered because one more PMOS transistor is turned off at the terminal 510. That is, the termination resistance provided to the external pin 505 at the terminal end portion 510 increases. For example, if a negative matching signal MS is provided to the counter 522, the counter 522 outputs a reduced count value CV so that the digital control code DCC is reduced by one bit. That is, a bit having a high level in the digital control code DCC is reduced. As a result, the voltage level of the tuning node CN becomes higher because the number of the PMOS transistors that are turned on at the terminal 510 increases.

9, the ODT circuit 500 of FIG. 9 compares the voltage level of the adjustment node CN with the reference voltage Vref to determine the external resistance R ). Therefore, it is unnecessary to adjust the level of the voltage applied to the gates of the PMOS transistors 511, 512, and 513 and simply turns on the PMOS transistors 511, 512, and 513 according to the digital control code DCC. It is possible to simplify the circuit implementation and to turn on only the PMOS transistors necessary for the voltage level control among the PMOS transistors 511, 512 and 513, thereby reducing current consumption.

This on-die termination operation can be performed separately for each pin.

10 is a block diagram illustrating an off-chip driver (OCD) according to an embodiment of the present invention.

10, the OCD 500 includes a terminating unit 560 and an adjusting unit 570. The terminating end 560 is connected to an adjustment node (CN) connected to the external pin (555). The external pin 555 is connected to the external resistor R through the channel. Termination 560 provides a driver impedance that matches the external resistor R to the channel coupled to the external pin 555 in response to the digital control code DCC. The adjustment unit 570 is also connected to the adjustment node CN connected to the external pin 555. That is, the terminating unit 560 and the adjusting unit 570 are connected to the adjusting node CN in parallel with each other. The adjusting unit 570 generates and provides a digital control code DCC to the terminating unit 560 based on the adjusting node CN voltage and the reference voltage Vref so that the driver impedance provided at the terminating unit 510 To match the external resistor (R) connected thereto. The external pin 555 may be a data input / output pin, a data strobe pin, a data mask pin, a termination data strobe pin, or the like. As used herein, the term " pin " refers broadly to electrical interconnections to an integrated circuit, including for example a pad or other electrical contact on an integrated circuit.

The OCD 550 of FIG. 10 changes the driver impedance of the termination portion 560 through the digital control code DCC to match the external resistance R and the driver impedance. In addition, the OCD 550 of FIG. 10 is connected to the external pin 555 separately from the data output buffer for outputting the read data through the external pin, so that the driver impedance can be matched when the read data is transmitted through the external pin. 10 may be included in the data output buffer 300 of FIG. 7 or may be connected to the external pin 210 in parallel with the data output buffer 300 to provide a driver impedance that matches the external resistor . In this case, the data output buffer 300 of FIG. 7 may not provide the driver impedance.

11 is a circuit diagram showing the OCD of FIG.

Referring to FIG. 11, the termination portion 560 includes a plurality of the NMOS transistors 561, 562, 563 connected between the tuning node CN and the ground voltage. Each of the NMOS transistors 561, 562, and 563 is turned on / off by applying each bit of the digital control code DCC to the gate. The driver impedance provided to the channel connected to the external pin 555 is changed in turning on / off the emmos transistors 561, 562, and 553. The NMOS transistors 561, 562, and 563 may have different sizes. For example, each of the NMOS transistors 561, 562, and 563 may have a size ratio of 4: 2: 1.

The adjustment unit 570 may include a comparator 571, a counter 572, and a register 573. The comparator 571 compares the voltage of the adjustment node CN with the reference voltage Vref and provides the comparison result to the counter 572 as the matching signal MS. A positive matching signal MS is provided to the counter 572 if the voltage level of the terminal 560 is higher than the reference voltage Vref. A negative matching signal MS is provided to the counter 572 if the voltage level of the terminal 560 is lower than the reference voltage Vref. A matching signal MS of "0" is provided to the counter 562 if the voltage level of the terminal 560 is equal to the reference voltage Vref. Where the voltage level of the terminating end 560 is inversely proportional to the driver impedance provided at the terminating end 560. That is, if the driver impedance provided at the terminal end portion 560 is large, the voltage level of the terminal end portion 560 is low, and if the driver impedance provided at the terminal portion 560 is low, the voltage level of the terminal end portion 560 is high.

The counter 572 outputs to the register 573 a count value CV that increases or decreases in accordance with the matching signal MS. For example, if a positive matching signal MS is provided to the counter 572, the counter 522 outputs a reduced count value CV. For example, when a negative matching signal MS is provided to the counter 572, the counter 572 outputs an incremented count value CV. Also, for example, if a match signal MS of "0" is provided to the counter 572, the counter 572 maintains the count value CV.

The register 573 stores the count value CV and provides it to the terminal 560 as a digital control code DCC. For example, if a positive matching signal MS is provided to the counter 572, the counter 572 outputs a reduced count value CV, so that the digital control code DCC is reduced by one bit. That is, a bit having a high level in the digital control code DCC is reduced. Therefore, the voltage level of the terminating part 560 becomes lower because the number of the NMOS transistors turned off at the terminating part 560 increases. That is, the driver impedance provided to the external pin 505 at the terminal end portion 560 increases. For example, if a negative matching signal MS is provided to the counter 572, the counter 572 outputs an incremented count value CV, so that the digital control code DCC is incremented by one bit. That is, a bit having a high level in the digital control code DCC is increased. Therefore, the voltage level of the tuning node CN becomes higher because the number of the NMOS transistors turned on at the terminating end 560 increases. That is, the driver impedance provided to the external pin 505 at the terminal end portion 560 is reduced.

The OCD 500 of FIG. 11 selectively turns on the NMOS transistors 561, 562, and 563 connected between the external pin 555 and the adjusting unit 570, (R) connected to the external pin (555) and the driver impedance provided at the terminal (560). Therefore, it is unnecessary to adjust the level of the voltage applied to the gates of the NMOS transistors 561, 562, and 563 and simply turns the NMOS transistors 561, 562, and 563 in accordance with the digital control code DCC, The circuit is simple to implement and the NMOS transistors 561, 562 and 563, which are necessary for adjusting the voltage level, are turned on only, so that current consumption can be reduced.

This driver impedance calibration can also be done separately for each pin.

12 is a block diagram illustrating a memory module according to an embodiment of the present invention.

Referring to FIG. 12, the memory module 600 includes a first memory rank 610 and a second memory rank 620.

The first memory rank 610 and the second memory rank 620 receive the first chip select signal CS1 and the second chip select signal CS2 respectively and output the first chip select signal CS1 and the second chip select signal CS2, And may be selectively driven in response to the selection signal CS2. The first memory rank 610 and the second memory rank 620 may be disposed on the same side of the memory module 600 and may be disposed on different sides. Although FIG. 10 illustrates a memory module 600 that includes two memory ranks 610 and 620, the memory module 600 may include one or more memory ranks.

Each of the first memory rank 610 and the second memory rank 620 may comprise a plurality of semiconductor memory devices. The plurality of semiconductor memory devices may be the semiconductor memory device 400 of FIG. 7 receiving a texture code (SCD) from the memory controller via the ODT pin.

13A-13F illustrate examples of memory modules according to embodiments of the present invention.

Referring to FIG. 13A, the memory module 700a may be an unbuffered dual in-line memory module (UDIMM). Memory module 700a may include a plurality of semiconductor memory devices that provide ODT or driver impedance to data transmission lines DQ. The semiconductor memory devices may be connected to the data transmission lines DQ, respectively. In addition, the semiconductor memory devices may be connected in a tree structure to the command / address transmission lines CA. In one embodiment, pseudo-differential signaling using a reference data voltage and a reference command / address voltage from a given supply voltage in a memory controller or memory module is utilized for data transfer and command / address transfer .

Referring to FIG. 13B, the memory module 700b may be a UDIMM. Memory module 700b includes a plurality of semiconductor memory devices that provide ODT or driver impedance to data transmission lines DQ and a module termination resistor portion 701 coupled to one end of command / address transmission lines CA . The command / address transmission lines CA may be connected to the semiconductor memory devices in a fly-by daisy-chain topology. In the memory module 700b, read / write leveling can be performed.

Referring to FIG. 13C, the memory module 700c may be a Registered Dual In-line Memory Module (RDIMM). Memory module 700c is coupled to a plurality of semiconductor memory devices, command / address transmission lines CA and provides command / address signals to the semiconductor memory devices to provide ODT or driver impedances to data transmission lines DQ. And a module termination resistors 712 and 713 connected to both ends of the command / address register 711 and the command / address transmission lines CA. The command / address register 711 may be daisy-chained with the semiconductor memory devices.

13D, the memory module 700d may be an RDIMM. Memory module 700d is coupled to a plurality of semiconductor memory devices, command / address transmission lines CA and provides command / address signals to the semiconductor memory devices to provide ODT or driver impedances to data transmission lines DQ. And a module termination resistor portion 722 connected to one end of the command / address transmission lines CA. The command / address register 721 may be connected to the semiconductor memory devices in a fly-by-daisy-chain manner. In the memory module 700d, read / write leveling can be performed.

Referring to FIG. 13E, the memory module 700e may be a Fully Buffered Dual In-line Memory Module (FBDIMM). Memory module 700e includes a plurality of semiconductor memory devices for providing ODT or driver impedances to the data transmission lines and a memory module for receiving high speed packets from the memory controller and converting the packets into command / And a hub 731 for providing to the devices. For example, the hub 731 may be an Advanced Memory Buffer (AMB).

Referring to FIG. 13F, the memory module 700f may be a Load Reduced Dual In-line Memory Module (LRDIMM). Memory module 700f includes a plurality of semiconductor memory devices for providing ODT or driver impedances to data transmission lines and command / address signals and data from a memory controller via a plurality of signal lines, And a buffer 741 for buffering and providing data to the semiconductor memory devices. The data transfer lines between the buffer 741 and the plurality of semiconductor memory devices may be connected in a point-to-point manner. Also, the command / address transmission lines between the buffer 741 and the plurality of semiconductor memory devices may be connected in a multi-drop scheme, a daisy-chain scheme, or a fly-by-daisy-chain scheme. Since the buffer 741 buffers both the command / address signal and the data, the memory controller can interface with the memory module 700f by driving only the load of the buffer 741. [ Accordingly, memory module 700f may include a greater number of memory devices and memory ranks, and the memory system may include a greater number of memory modules.

Figure 14 is a diagram illustrating a memory system in accordance with one embodiment of the present invention.

14, a memory system 800 includes a memory controller 810, and at least one memory module 820, 830.

The first memory module 820 and the second memory module 830 are connected to the memory controller 810 via a bus 840. Each of the first memory module 820 and the second memory module 830 may be the memory module 600 of Figure 10 or the memory modules 700a, 700b, 700c, 700d, 700e, 700f of Figures 11a-11f .

The first memory module 820 includes at least one memory rank R1 and R2 and the second memory module 830 includes at least one memory rank R3 and R4. In one embodiment, memory ranks R1, R2, R3, R4 may be connected in a multi-drop manner to transmit and receive data and / or address signals over the same transmission line. Each of the memory ranks R1, R2, R3, R4 (i. E., Each of the semiconductor memory devices included in the memory rank) may provide a termination resistance or driver impedance to the data transmission line, thereby improving signal fidelity. In one embodiment, the memory controller 810 may also perform ODT and perform a pull-up termination operation using a pull-up resistor (RTT) connected between the power supply voltage VDDQ and the transmission line.

As described above, the on-die termination circuit, the data output buffer, and the semiconductor memory device according to the embodiments of the present invention vary the termination resistance or the driver impedance provided to the data transmission line according to the length code reflecting the data rate, Can be reduced and the signal fidelity can be improved.

The present invention can be usefully used in any semiconductor memory device, memory module, and memory system.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. It will be understood that the invention may be modified and varied without departing from the scope of the invention.

Claims (10)

A terminating resistor connected to the external pin and providing a terminating resistor to the transmission line connected to the external pin; And
And a termination control section connected to the termination resistance section and varying a resistance value of the termination resistance in response to a plurality of bit string codes reflecting a data rate,
Wherein the termination control section decreases the resistance value of the termination resistance as the data rate increases and increases the resistance value of the termination resistance as the data rate decreases. delete The semiconductor memory device according to claim 1, wherein the termination control unit generates a plurality of termination control signals activated in response to the length code and the output enable signal,
The termination resistor section,
A plurality of transistors each connected to a supply voltage and turned on in response to each bit of the termination control signal; And
And a plurality of resistors connected between each of the plurality of transistors and the external pin. A termination coupled between a power supply voltage having a fixed voltage level and an adjustment node coupled to the external pin and providing a termination resistance to a channel coupled to the external pin in response to the plurality of bits of the digital control code; And
And an adjustment unit connected to the adjustment node for changing each bit value of the digital control code based on a result of comparing the voltage of the adjustment node with a reference voltage to match the termination resistance with an external resistance connected to the external pin On termination circuit of a semiconductor memory device.  5. The method of claim 4, wherein the termination comprises a plurality of PMOS transistors coupled between the power supply voltage and the tuning node, wherein each bit of the digital control code is applied to a gate of the PMOS transistors On-die termination circuit of a semiconductor memory device. A driver connected to an external pin and providing a driver impedance to the transmission line while performing a driver operation for providing read data to a memory controller through a transmission line connected to the external pin; And
A driving unit connected to the driving unit and controlling the driving unit to perform the driver operation in response to an output enable signal and generating a driving control signal for controlling the driving unit by combining the read data with a data code reflecting the data rate Wherein the driver impedance is varied according to the length code. 7. The method of claim 6, wherein the output enable signal is activated in a read mode,
Up driving control signal and a pull-down driving control signal by combining the read data and the length code to generate a pull-up driving control signal and a pull-down driving control signal in response to the output enable signal, And provides the pull-down driving control signal. 8. The apparatus of claim 7, wherein the driving unit
A pull-up driver, connected between the power supply voltage and the external pin, for receiving the pull-up driving control signal from the control unit; And
And a pull-down driver connected between the ground voltage and the external pin for receiving the pull-down driving control signal from the control unit. 9. The method of claim 8,
Wherein the power supply voltage is 0.2V. A memory core for storing data and generating readout data based on the stored data; And
A data output circuit for outputting the read data provided from the memory core to a memory controller through a transmission line connected to an external pin and providing a variable driver impedance in response to a plurality of bit string codes reflecting a data rate in the transmission line in a read mode, Buffer,
The data output buffer
A driver connected to the external pin and providing the driver impedance to the transmission line while performing a driver operation for providing the read data to the memory controller; And
A driving unit connected to the driving unit and controlling the driving unit to perform the driver operation in response to an output enable signal and generating a driving control signal for controlling the driving unit by combining the read data with a data code reflecting the data rate And a control section.

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