KR20100001818A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
KR20100001818A
KR20100001818A KR1020080061889A KR20080061889A KR20100001818A KR 20100001818 A KR20100001818 A KR 20100001818A KR 1020080061889 A KR1020080061889 A KR 1020080061889A KR 20080061889 A KR20080061889 A KR 20080061889A KR 20100001818 A KR20100001818 A KR 20100001818A
Authority
KR
South Korea
Prior art keywords
pattern
hard mask
mask layer
layer pattern
forming
Prior art date
Application number
KR1020080061889A
Other languages
Korean (ko)
Inventor
구선영
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080061889A priority Critical patent/KR20100001818A/en
Publication of KR20100001818A publication Critical patent/KR20100001818A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE: A method for manufacturing semiconductor device is provided to form the active area by etching the semiconductor substrate to the etching mask. CONSTITUTION: The hard mask layer is formed on the semiconductor substrate(300). The photosensitive film is formed in the top of hard mask. The first photoresist pattern is formed with the exposure development process of using the mask of line and space pattern. The first hard mask layer pattern is formed by etching the hard mask layer. The second photosensitive pattern is formed by the exposure development process of using the mask. The second hard mask layer pattern is formed the second photosensitive pattern by etching the first hard mask layer pattern exposing to mask. The second photosensitive pattern is removed. The active area(345) is formed by etching the semiconductor substrate.

Description

Method for Forming Semiconductor Device {Method for Manufacturing Semiconductor Device}

1 is a photograph showing a method of forming a semiconductor device according to the prior art.

2A to 2D are layout views illustrating a method of forming a semiconductor device according to the prior art.

3A to 3C are layout views illustrating a method of forming a semiconductor device in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and after forming a first hard mask layer pattern having a line space shape on a semiconductor substrate, forming a photoresist pattern crossing the first hard mask layer and masking the photoresist pattern. A method of securing an overlay process margin is disclosed by etching a first hard mask layer pattern to form a second hard mask layer pattern, and etching a semiconductor substrate using the second hard mask layer pattern as an etch mask to form an active region. do.

Recent semiconductor memory devices. In particular, despite the increasing demand for large capacity of DRAM (DRAM) devices, the capacity increase of DRAM devices is also limited by the increase in chip size. Increasing chip size reduces the number of chips per wafer, which reduces device productivity. Therefore, in recent years, efforts have been made to change cell layouts to reduce cell area, and thus to integrate more memory cells on one wafer. As a result of these efforts, it has recently changed from an 8F2 layout to a 6F2 layout.

The trend of high integration of semiconductor devices is greatly influenced by the development of fine pattern formation technology, and the miniaturization of the photoresist pattern, which is widely used as a mask such as an etching or ion implantation process, is essential in the semiconductor device manufacturing process.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate, but is primarily proportional to the light source wavelength (λ) and process variable (k) of the reduced exposure apparatus used. Inversely proportional to the lens aperture (NA, numerical aperture) of the device.

In this case, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern, respectively. In order to form a fine pattern of about 0.5 μm or less, deep ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or ArF laser having a wavelength of 248 nm is used. An exposure apparatus used as a light source should be used.

In addition, apart from the reduction exposure apparatus, a process-based method is a method of using a phase shift mask as a photo mask or a separate thin film on the wafer to improve image contrast. A tri-layer resistor (hereinafter referred to as TLR), which is a method of contrast enhancement layer (CEL) or an intermediate layer such as spin on glass (SOG) between two layers of photoresist. Method or a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

1 is a photograph showing a problem of a method of forming a semiconductor device according to the prior art.

Referring to FIG. 1, after a line / space pattern 100 in an oblique direction, a hole pattern 110 is illustrated through an etching process.

At this time, in order to etch and separate the line / space pattern 100 by the diameter of the hole, the size of the hole must be large, and an overlay problem between the hole and the line / space pattern 100 occurs and the active area is attacked. This happens.

2A to 2D are layout views illustrating a method of forming a semiconductor device according to the prior art.

2A to 2D, FIG. 2A illustrates a line / space pattern 200 formed in an oblique direction, and FIG. 2B illustrates a hole pattern 210 that separates the line / space pattern 200 in an oblique direction. 2C illustrates an island pattern by crossing the patterns of FIGS. 2A and 2B, and FIG. 2D is an active region 220 formed by FIG. 2C.

In the method of forming a semiconductor device according to the prior art, as a highly integrated semiconductor device is developed, a pattern composed of 6F2 instead of 8F2 is formed in an oblique direction differently from 8F2.

Such 6F2 has difficulty in patterning in an oblique island pattern due to an overlay process margin problem.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and after forming a first hard mask layer pattern having a line space shape on a semiconductor substrate, forming a photoresist pattern crossing the first hard mask layer and masking the photoresist pattern. The second hard mask layer pattern is etched to form a second hard mask layer pattern, and the semiconductor substrate is etched using the second hard mask layer pattern as an etch mask to form an active region, thereby securing an overlay process margin. It is an object to provide a formation method.

The method for forming a semiconductor device according to the present invention,

Forming a first hard mask layer pattern on the semiconductor substrate;

Forming a photoresist pattern intersecting the first hard mask layer pattern on the first hard mask layer pattern and the semiconductor substrate;

Etching the first hard mask layer pattern exposing the photoresist pattern with an etch mask to form a second hard mask layer pattern; and

And etching the semiconductor substrate using the second hard mask layer pattern as an etch mask to form an active region.

Here, the first hard mask layer pattern is formed in a first direction,

The photoresist pattern is formed in a second direction,

The photoresist pattern is formed in a zigzag line / space form,

The photoresist pattern is formed in the form of a line / space in the vertical direction,

In the space of the photoresist pattern, an area crossing the first hard mask layer pattern may have a larger line width than other areas.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if it is mentioned that the layer is on another layer or substrate it may be formed directly on another layer or substrate, Alternatively, a third layer may be interposed therebetween.

Also, the same reference numerals throughout the specification represent the same components.

3A to 3C are layout views illustrating semiconductor devices formed in accordance with the present invention.

Referring to FIG. 3A, a hard mask layer (not shown) is formed on the semiconductor substrate 300.

Next, after the photosensitive film is formed on the hard mask layer, a first photosensitive film pattern (not shown) is formed by an exposure and development process using a mask having a line / space pattern.

Next, the hard mask layer is etched using the first photoresist pattern as a mask to form a first hard mask layer pattern 315.

Referring to FIG. 3B, after the first photoresist pattern is removed, a photoresist is formed on the entire surface, and then the second photoresist pattern 325 is formed by an exposure and development process using a mask that intersects the first hard mask layer pattern 315. ).

In this case, the shape of the second photoresist layer pattern 325 may be formed as in (i) to (v).

First, (i) is a state in which the second photosensitive film pattern 325 in the second direction that intersects the first hard mask layer pattern 315 in the first direction is formed.

In this case, the first hard mask layer pattern 315 may be formed to have a different slope from that of the second photoresist layer pattern 325.

(Ii) and (iii) are formed as shown in (iii), and the photoresist pattern 325 is formed to cross the first hard mask layer pattern 315 in a zigzag form.

(I) The second photosensitive film pattern 325 which crosses the first hard mask layer pattern 315 in the first direction is formed in the vertical direction.

(V) is formed as shown in (V), but the exposed first hard mask layer pattern 315 is formed in a pad form larger than other regions.

In a subsequent process, the first hard mask layer pattern 315 having the second photoresist pattern 325 exposed as a mask is etched to form a second hard mask layer pattern (not shown).

Referring to FIG. 3C, after removing the second photoresist layer pattern 325, the active region 345 is formed by etching the semiconductor substrate 300 using the second hard mask layer pattern as a mask.

     BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and after forming a first hard mask layer pattern having a line space shape on a semiconductor substrate, forming a photoresist pattern crossing the first hard mask layer and masking the photoresist pattern. Etching the first hard mask layer pattern to form a second hard mask layer pattern, and etching the semiconductor substrate using the second hard mask layer pattern as an etch mask to form an active region, thereby providing an overlay process margin securing effect do.

     In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

Forming a first hard mask layer pattern on the semiconductor substrate; Forming a photoresist pattern crossing the first hard mask layer pattern and the first hard mask layer pattern on the semiconductor substrate; Etching the first hard mask layer pattern exposing the photoresist pattern with an etch mask to form a second hard mask layer pattern; And And forming an active region by etching the semiconductor substrate using the second hard mask layer pattern as an etch mask. The method of claim 1, And the first hard mask layer pattern is formed in a first direction. The method of claim 1, The photosensitive film pattern is a semiconductor device forming method, characterized in that formed in the second direction. The method of claim 3, wherein The photosensitive film pattern is a method of forming a semiconductor device, characterized in that formed in a zigzag line / space form. The method of claim 3, wherein The photosensitive film pattern is a method of forming a semiconductor device, characterized in that formed in the form of a line / space in the vertical direction. The method of claim 5, wherein And a line width in the space of the photoresist pattern that crosses the first hard mask layer pattern is larger than that of other regions.
KR1020080061889A 2008-06-27 2008-06-27 Method for manufacturing semiconductor device KR20100001818A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080061889A KR20100001818A (en) 2008-06-27 2008-06-27 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080061889A KR20100001818A (en) 2008-06-27 2008-06-27 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20100001818A true KR20100001818A (en) 2010-01-06

Family

ID=41812080

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080061889A KR20100001818A (en) 2008-06-27 2008-06-27 Method for manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR20100001818A (en)

Similar Documents

Publication Publication Date Title
US7651950B2 (en) Method for forming a pattern of a semiconductor device
KR101068327B1 (en) Exposure mask and method for forming semiconductor device by using the same
KR101120181B1 (en) Method for Manufacturing Semiconductor Device
KR20100042941A (en) Methods of manufacturing a semiconductor device for photographing concurrently dpt area and non-dpt area by using one merging photomask
US20120214103A1 (en) Method for fabricating semiconductor devices with fine patterns
KR20100001818A (en) Method for manufacturing semiconductor device
US7087533B2 (en) Method for fabricating semiconductor device
KR100345367B1 (en) Fabricating method for semiconductor device
KR100290588B1 (en) Method for forming conductive film pattern in semiconductor device
KR101076794B1 (en) Method of fabricating semiconductor device
KR100333542B1 (en) Contact plug formation method of semiconductor device
KR20010080842A (en) A method of forming a line pattern
KR100709453B1 (en) Forming method for bit line of semiconductor device
JP2016152283A (en) Semiconductor device manufacturing method
KR100597765B1 (en) Method for fabricating semiconductor device
KR20060076661A (en) Manufacturing method for semiconductor device
KR20020002008A (en) Manufacturing method for semiconductor device
KR100419971B1 (en) Mask for forming pattern in fabricating semiconductor device and fabricating method thereof
KR20010037239A (en) Fabricating method for semiconductor device
KR20120041989A (en) Method for manufacturing semiconductor device
KR20060076677A (en) Method for manufacturing semiconductor device
KR20000045446A (en) Method for forming fine pattern of semiconductor device
KR20030000125A (en) Forming method for bitline of semiconductor device
JP2008182123A (en) Manufacturing method of semiconductor device
KR20060074975A (en) Layout method of semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination