KR100709453B1 - Forming method for bit line of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line in a semiconductor device. The process is simplified by forming a contact plug and a bit line without forming a bit line contact hole pattern, thereby simplifying the process. In addition, it is a technology that improves the electrical characteristics and reliability of the device by increasing the contact area between the contact plug and the bit line, which favors high integration of the device.

Description

Forming method for bit line of semiconductor device

1A to 1E are plan views illustrating a bit line forming method of a semiconductor device according to the related art.

2A to 2F are plan views illustrating a method of forming a bit line of a semiconductor device in accordance with a first embodiment of the present invention.

3 is a plan view illustrating a method of securing insulation between bit lines in a method of forming a bit line of a semiconductor device according to the present invention;

4A to 4C are plan views illustrating a bit line forming method of a semiconductor device in accordance with a second embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

10, 20: semiconductor substrate 11, 21: device isolation region

12, 22, 42: active area 13, 23, 43: word line

14, 24, 31, 44: contact plug 15, 27, 45: interlayer insulating film

16: bit line contact hole 17, 25, 47: bit line

26: recessed contact plug 46: trench

The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to a method for forming a bit line of a semiconductor device in which a bit line is formed without forming a bit line contact hole pattern after forming a contact plug during bit line patterning. will be.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. In order to form a fine pattern of 0.5 μm or less, the micrometer has a limit of about μm, and an exposure apparatus using an ultraviolet ray having a small wavelength, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source or a process As a method of imaging, a method of using a phase inversion mask as an exposure mask and a method of forming a separate thin film on the wafer which can improve image contrast can be used. Tri layer resist (hereinafter referred to as TLR) method, which is interposed between an intermediate layer such as spin on glass (SOG), between the two layers of photoresist, or selectively on top of the photoresist. It has been developed, such as silico-migration method for implanting lowering the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings is reduced in size as the device is integrated, and the distance between the wiring and the peripheral wiring is reduced, and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.

1A to 1E are plan views illustrating a bit line forming method of a semiconductor device according to the prior art.

First, an isolation region 11 and an active region 12 are formed in the semiconductor substrate 10. (See Figure 1A)

Next, a word line 13 is formed to cross the active region 12. A mask insulating film pattern (not shown) is stacked on the word line 13. (See FIG. 1B)

A contact plug 14 is then formed which is connected to the portion intended as the bit line contact and the storage electrode contact.

Next, an interlayer insulating film 15 is formed over the entire surface. (See Figure 1C)

Next, the interlayer insulating layer 15 is etched using a bit line contact mask that exposes a portion of the contact plug 14 that is intended as a bit line contact, to form a bit line contact hole 16. (See FIG. 1D)                         

Next, a bit line 17 connected to the contact plug 14 through the bit line contact hole 16 is formed. (See Figure 1E)

As described above, in the method of forming a bit line of a semiconductor device according to the related art, as the semiconductor device becomes highly integrated, the size of the pattern decreases, but in the case of the contact hole pattern, a PSM (phase shift mask) or a resist flow process is performed. Since it is difficult to form a small contact hole below a certain level through the short circuit between the devices there is a problem that reduces the operating characteristics and reliability of the device.

The present invention, in order to solve the above problems of the prior art, without forming a bit line contact hole pattern, forming a bit line after contact plug formation and recessing the contact plug a predetermined thickness, or after the contact plug formation damascene process The purpose of the present invention is to provide a method for forming a bit line of a semiconductor device which prevents a short circuit between devices by forming a bit line, thereby improving operation characteristics and reliability of the device.

A bit line forming method of a semiconductor device according to the present invention for achieving the above object,

Forming a device isolation region defining an active region on the semiconductor substrate;

Forming a word line on an active region of the semiconductor substrate;

Forming a contact plug in the active region, the contact plug being connected to a portion of the active region as a bit line contact and a storage electrode contact;

Forming a bit line connected to a portion of the contact plug, the bit line contact being defined;

Recessing a predetermined thickness of contact plugs other than the contact plugs connected to the bit lines;

A first feature is to include a step of forming an interlayer insulating film over the entire surface.

A bit line forming method of a semiconductor device according to the present invention for achieving the above object,

Forming a device isolation region defining an active region on the semiconductor substrate;

Forming a word line on an active region of the semiconductor substrate;

Forming a contact plug connected to the bit line contact and the storage electrode contact in the active region;

Forming an interlayer insulating film over the entire surface;

Etching the interlayer insulating layer with an etch mask using a bit line mask to form a trench for exposing a portion intended for a bit line and a portion intended for a bit line contact among the contact plugs;

A second feature is a step of forming a bit line connected to the contact plug through the trench.

Hereinafter, with reference to the accompanying drawings will be described in detail.                     

2A to 2F are plan views illustrating a bit line forming method of a semiconductor device according to a first embodiment of the present invention.

First, an isolation region 21 and an active region 22 are formed in the semiconductor substrate 20. (See Figure 2A)

Next, a word line 23 is formed to cross the active region 22. A mask insulating layer pattern (not shown) is stacked on the word line 23. At this time, the mask insulating film pattern is formed of a SiON film or a nitride film. (See Figure 2b)

A contact plug 24 is then formed which is connected to the portions intended as bit line contacts and storage electrode contacts. The contact plug 24 is formed of a polycrystalline silicon layer or a metal material such as tungsten or TiN. (See Figure 2c)

Next, a bit line 25 is formed to be connected to a portion of the contact plug 24 to be a bit line contact. A mask insulating film pattern is stacked on the bit line 25. (See FIG. 2D)

Then, the contact plugs 24 other than the contact plugs 24 connected to the bit lines 25 are recessed by a predetermined thickness so that the distance between the bit lines 25 and the contact plugs 24 intended for the storage electrode contacts. To secure. The recessed contact plug 26 is formed by a wet etching process or a dry etching process. (See Figure 2E)

Next, an interlayer insulating film 27 is formed over the entire surface. (See Figure 2f)

3 is a plan view illustrating a method for securing insulation between bit lines in the method of forming a bit line of a semiconductor device according to the present invention. The bit line 25 may be adjusted by a mask process during the formation of the contact plug 31. To prevent a short circuit.

4A to 4C are plan views illustrating a method of forming a bit line of a semiconductor device in accordance with a second embodiment of the present invention.

First, the active region 42, the word line 43, and the contact plug 44 are formed by performing the process up to FIG. 2C.

Next, an interlayer insulating film 45 is formed over the entire surface. (See Figure 4A)

Next, the interlayer insulating layer 45 is etched using a bit line mask as an etch mask to form a trench 46 exposing portions of the contact plugs 44 to be bit lines and bit line contacts. (See Figure 4b)

Next, a bit line 47 is formed to be connected to the contact plug 44 through the trench 46. (See Figure 4c)

As described above, in the method of forming a bit line of a semiconductor device according to the present invention, a contact plug and a bit line are not formed, and a contact hole pattern having a size that is difficult to resolve is not formed by forming a contact plug and a bit line. It is advantageous to improve the electrical characteristics and reliability of the device by simplifying the structure, facilitating high integration of the device, and increasing the contact area between the contact plug and the bit line.

Claims (6)

Forming a device isolation region defining an active region on the semiconductor substrate; Forming a word line on an active region of the semiconductor substrate; Forming a contact plug connected to the bit line contact and the storage electrode contact in the active region; Forming a bit line connected to a portion of the contact plug, the bit line contact being defined; Recessing a predetermined thickness of contact plugs other than the contact plugs connected to the bit lines; A method of forming a bit line in a semiconductor device comprising the step of forming an interlayer insulating film over the entire surface. The method of claim 1, And forming a mask insulating film pattern on the word line and the bit line. The method of claim 1, The contact plug is a bit line forming method of a semiconductor device, characterized in that formed of a polysilicon layer or a metal material. Forming a device isolation region defining an active region on the semiconductor substrate; Forming a word line on an active region of the semiconductor substrate; Forming a contact plug connected to the bit line contact and the storage electrode contact in the active region; Forming an interlayer insulating film over the entire surface; Etching the interlayer insulating layer with an etch mask using a bit line mask to form a trench for exposing a portion intended for a bit line and a portion intended for a bit line contact among the contact plugs; And forming a bit line connected to the contact plug through the trench. The method of claim 4, wherein And forming a mask insulating film pattern on the word line and the bit line. The method of claim 4, wherein The contact plug is a bit line forming method of a semiconductor device, characterized in that formed of a polysilicon layer or a metal material.

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