KR100527568B1 - Manufacturing method for semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a landing plug is formed in a lower interlayer insulating film, an upper interlayer insulating film and an etch barrier layer are sequentially formed, a bit line contact hole is formed, and a contact plug conductive layer is coated. And, in forming the contact plug by the CMP process, by minimizing the CMP damage of the barrier metal layer by the etch barrier layer to compensate for the damage of the barrier metal layer of the contact plug as shown in Figure 6 resulting in disconnection or bit line It is possible to prevent the resistance increase of the etch barrier layer to prevent the damage of the lower portion of the bit line W layer due to the oxygen barrier to prevent pattern defects, increased bit line resistance and voids.

Description

Manufacturing method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to minimize the loss of barrier metal layer of a bit line contact plug, to prevent the occurrence of defects in a subsequent process, and to increase the contact resistance or the increase of the bit line capacitance, thereby increasing process yield It relates to a method for manufacturing a semiconductor device that can improve the reliability of the device.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV), for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photosensitive film has been developed to lower the resolution limit.

In addition, the contact hole connecting the upper and lower conductive wirings has a larger design rule than the above line / space pattern. As the device becomes more integrated, the size of the contact hole and the distance between the peripheral wirings are reduced, and the contact hole diameter and The aspect ratio, which is the ratio of depths, increases. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, accurate and strict alignment between the masks in the contact forming process is required, so that the process margin is reduced or the process must be performed without any margin.

These contact holes can be used for misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, The mask is formed by considering factors such as registration between the masks.

As a method of forming the contact hole as described above, there are a direct etching method, a method using a sidewall spacer, a SAC method, and the like.

In the above method, the direct etching method and the sidewall spacer forming method cannot be used for manufacturing a device having a design rule of 0.3 μm or less in the current technology level, and thus there is a limitation in high integration of the device.

In addition, the SAC method, which is designed to overcome the limitations of the lithography process in forming contact holes, can be divided into polysilicon layer, nitride film, or oxynitride film, depending on the material used as the etch barrier layer. Can be used as an etch shield.

Although not shown, a method of manufacturing a semiconductor device of a bit line contact having a landing plug according to the related art is as follows.

First, a gate oxide layer forming a predetermined substructure on a semiconductor substrate, for example, a device isolation oxide layer and a metal oxide semi conductor field effect transistor (hereinafter referred to as a MOS FET), and a hard mask layer pattern overlapping each other. After forming the gate electrode, an insulating spacer made of a nitride film is formed on sidewalls of the hard mask layer pattern and the gate electrode.

Then, after applying the lower interlayer insulating film to the entire surface of the structure, and then planarizing, by forming a landing plug contact hole by patterning the lower interlayer insulating film by a photolithography process using an etching mask for landing plugs, After filling the contact hole by applying a conductive layer for landing plug on the surface, the conductive layer is etched to form a landing plug separated into each contact hole.

Thereafter, an upper interlayer insulating film is applied to the entire surface of the structure, and then the upper interlayer insulating film on the portion of the landing plug, which is supposed to be a bitline contact, is removed to form a bitline contact hole.

Then, the Ti / TiN layer, which is a barrier metal layer, and the W layer, which is a plug material, are sequentially applied to the entire surface of the structure to fill the contact hole, and then the back layer and the barrier metal layer are sequentially etched back to form a bit line contact plug. do.

In the method of manufacturing a semiconductor device according to the related art as described above, the barrier metal layer inside the contact hole is severely damaged during the etch back process of the barrier metal layer after W etching to form the bit line contact plug, as shown in FIGS. 1 to 3. The barrier metal layer is lost, and a core is formed at the center of W, thereby causing electrical disconnection, or increasing the capacitance of a subsequent bit line, thereby decreasing process yield and device reliability.

Furthermore, in devices having a design rule of 0.1 μm or less, the barrier metal layer occupies a thickness of 30% or more of the contact plug material, thereby increasing the occurrence of defects.

In addition, another problem of the prior art is that the W layer formed on the interlayer insulating film made of an oxide film is destroyed by the polymer formed on the W side during the etching process due to the influence of oxygen inside the interlayer insulating film, as shown in FIG. There is another problem that the lower portion of the lower slope is formed to increase the resistance or a pattern defect occurs.

The present invention has been made to solve the above problems, and an object of the present invention is to minimize the damage of the barrier metal layer when forming the bit line contact plug, thereby resulting in electrical disconnection or deterioration of device characteristics due to increased capacitance of the bit line. It is to provide a method of manufacturing a semiconductor device that can prevent the.

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming a lower interlayer insulating film having a landing plug on a semiconductor substrate having a predetermined lower structure;

Forming an insulating film on the lower interlayer insulating film, the insulating film having an etch ratio different from the lower interlayer insulating film and having an etch barrier layer;

Forming a contact hole by etching the insulating layer by a photolithography process using a contact mask;

Sequentially forming a barrier metal layer and a contact plug conductive layer on the entire surface of the structure, and using a CMP process using an additive in a slurry for colloidal oxide film based on SiO ₂ , until the etch barrier layer is exposed. Etching the plug conductive layer and the barrier metal layer in sequence, the contact plug is formed so as not to damage the barrier metal layer in the bit line contact hole.

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In another aspect of the present invention, the barrier metal layer is a Ti, TiN or Ti / TiN laminated structure, the interlayer insulating film is BPSG, PE-TEOS, LP-TEOS or HDP, the CMP process is an additive to the slurry for the oxide film Etched using, the CMP slurry is a colloidal type of pH 1-9, SiO ₂ base, the CMP slurry is characterized in that the acid slurry contains about 0.5-8w% of the fruit or 0.01-10wt% citric acid do.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

5A to 5E are diagrams illustrating a process of manufacturing a semiconductor device according to the present invention, which is an example of a bit line contact device having a landing plug.

First, as described above in the related art, a gate oxide film 12 of the MOS FET is formed on the semiconductor substrate 10, and the gate electrode overlapping the hard mask layer 16 pattern on the gate oxide film 12. After the 14 is formed, an insulating spacer 18 made of a nitride film is formed on the sidewalls of the hard mask layer 16 pattern and the gate electrode 14, and then the lower interlayer insulating film 20 is formed on the entire surface of the structure. Apply and flatten the top. The hard mask layer 16 is formed of a nitride film to prevent damage to the gate and a short circuit between the wirings in a subsequent process, and the gate electrode 14 is formed of a low W or tungsten silicide layered on polycrystalline silicon. As the resist structure, the thickness of the hard mask layer 16 pattern is further increased to pattern it, thereby increasing the aspect ratio. In addition, an etch barrier layer may be formed before the lower interlayer insulating layer 20 is applied. (See FIG. 5A).

Then, the lower interlayer insulating layer 20 is patterned to form a landing plug contact hole by a photolithography process using an etching mask for landing plug, and a landing plug conductive layer is applied to the entire surface of the structure to fill the contact hole. Thereafter, the conductive layer is etched by etching, CMP, or the like to form a landing plug 22 having a conductive layer pattern separated into respective contact holes. (See FIG. 5B).

An insulating film is then formed on the entire surface of the structure. In this case, the insulating layer may be provided with any one selected from the etch barrier layer 26 alone or the stacked structure of the upper interlayer insulating layer 24 and the etch barrier layer 26. After applying the upper interlayer insulating film 24 of an oxide film material, an etching barrier layer 26 for CMP stop is formed on the upper interlayer insulating film 24 of a nitride film material, for example, Si ₃ N ₄ , SiOxNy, In the landing plug 22, the etch barrier layer 26 and the upper interlayer insulating layer 24, which are supposed to be bit line contacts, are sequentially removed by a photolithography method using a contact mask to form bit line contact holes. Ti. On the entire surface of the structure. The barrier metal layer 28 having a TiN or Ti / TiN stacked structure and the W layer 30 which is a plug material are sequentially applied to fill the bit line contact hole. The upper interlayer insulating layer 24 may be formed of BPSG, PE-TEOS, LP-TEOS, or HDP, and the etch barrier layer 26 of the nitride film may be formed of Si ₃ N _4, SiON, or the like. (See FIG. 5C).

Thereafter, the W layer 30 and the barrier metal layer 28 are sequentially CMP to form a bit line contact plug having a pattern of the W layer 30 and the barrier metal layer 28. In this case, when the CMP process is etched using an additive in an oxide film slurry rather than an metal layer etching slurry, a CMP barrier is formed by the etching barrier layer 26, and the damage of the metal layer may be minimized. The oxide film slurry is a colloidal type of SiO ₂ base, and the slurry for oxide film may contain about 0.5-8 wt% of fruit tree or 0.01-10 wt% of citric acid. (See FIG. 5D).

Then, the bit line conductive layer 32 of W material is formed on the entire surface of the structure, and the bit line pattern is formed by patterning the conductive layer 32 by a photolithography process using a bit line patterning mask. In this case, the W may be prevented from being inclined reversely by the etching barrier layer 26. (See FIG. 5E).

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As described above, in the method of manufacturing a semiconductor device according to the present invention, a landing plug is formed in a lower interlayer insulating film, an upper interlayer insulating film and an etch barrier layer are sequentially formed, a bit line contact hole is formed, and a contact plug conductive material is formed. Since the layer was applied and the contact plug was formed by the CMP process, the etch barrier layer minimizes the damage of the barrier metal layer during the CMP process and compensates for the damage of the barrier metal layer of the contact plug as shown in FIG. The resistance of the bit line can be prevented from increasing, and the etch barrier layer becomes an oxygen barrier to prevent the lower portion of the bit line W layer from being damaged, thereby preventing pattern defects, increasing the resistance of the bit line, and generating voids.

1 is a cross-sectional SEM photograph of a semiconductor device according to the prior art.

2 is a CD-SEM photograph of a semiconductor device according to the prior art.

3 is a TEM photograph of a semiconductor device according to the prior art.

Figure 4 is a SEM photograph after the formation of the bit line of the semiconductor device according to the prior art.

5a to 5e is a manufacturing process diagram of a semiconductor device according to the present invention.

6 is a TEM photograph of a semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10 semiconductor substrate 12 gate oxide film

14 gate electrode 16 hard mask layer

18: insulating spacer 20: lower interlayer insulating film

22: landing plug 24: upper interlayer insulating film

26: etching barrier layer 28: barrier metal layer

30: W layer 32: conductive layer for bit line

Claims (9)

Forming a lower interlayer insulating film having a landing plug on a semiconductor substrate having a predetermined lower structure; Forming an insulating film on the lower interlayer insulating film, the insulating film having an etch ratio different from the lower interlayer insulating film and having an etch barrier layer; Forming a contact hole by etching the insulating layer by a photolithography process using a contact mask; Sequentially forming a barrier metal layer and a contact plug conductive layer on the entire surface of the structure; In the CMP process using an additive in the SiO ₂ based colloidal oxide film slurry, the contact plug conductive layer and the barrier metal layer are sequentially etched until the etching barrier layer is exposed, and the barrier metal layer in the bit line contact hole is etched. A method of manufacturing a semiconductor device comprising the step of forming a contact plug so as not to be damaged. The method of claim 1, The barrier metal layer is a manufacturing method of a semiconductor device, characterized in that the Ti, TiN or Ti / TiN laminated structure. The method of claim 1, The interlayer insulating film is a semiconductor device manufacturing method, characterized in that formed in one selected from the group consisting of BPSG, PE-TEOS, LP-TEOS and HDP. delete The method of claim 1, The CMP slurry is a method for manufacturing a semiconductor device, characterized in that pH 1-9. The method of claim 1, The CMP slurry is a manufacturing method of a semiconductor device, characterized in that containing about 0.5-8wt% fruit tree in the slurry. The method of claim 1, The CMP slurry is a manufacturing method of a semiconductor device, characterized in that containing 0.01-10wt% citric acid in the slurry. The method of claim 1, And the insulating film has a lamination structure of an etch barrier layer alone, an upper interlayer insulating film, and an etch barrier layer. The method of claim 8, The etching barrier layer is a semiconductor device manufacturing method, characterized in that formed of Si ₃ N ₄ or SiOxNy material.